/* collection of junk waiting time to sort out
- Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
- Contributed by Red Hat.
+ Copyright (C) 1998-2020 Free Software Foundation, Inc.
+ Contributed by Red Hat
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef FRV_SIM_H
#define FRV_SIM_H
#include "sim-options.h"
-/* Not defined in the cgen cpu file for access restriction purposes. */
-#define H_SPR_ACC0 1408
-#define H_SPR_ACC63 1471
-#define H_SPR_ACCG0 1472
-#define H_SPR_ACCG63 1535
-
-/* gdb register numbers. */
-#define GR_REGNUM_MAX 63
-#define FR_REGNUM_MAX 127
-#define PC_REGNUM 128
-#define LR_REGNUM 145
+/* True if SPR is the number of accumulator or accumulator guard register. */
+#define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535)
/* Initialization of the frv cpu. */
void frv_initialize (SIM_CPU *, SIM_DESC);
extern QI frvbf_set_icc_for_shift_left (SIM_CPU *, SI, SI, QI);
extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
+/* Insn semantics. */
extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
+extern SI frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
+extern SI frvbf_iacc_cut (SIM_CPU *, DI, SI);
extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
/* Hardware/device support.
??? Will eventually want to move device stuff to config files. */
-/* Support for the MCCR register (Cache Control Register) is needed in order
- for overlays to work correctly with the scache: cached instructions need
- to be flushed when the instruction space is changed at runtime. */
-
-/* These were just copied from another port and are necessary to build, but
- but don't appear to be used. */
-#define MCCR_ADDR 0xffffffff
-#define MCCR_CP 0x80
-/* not supported */
-#define MCCR_CM0 2
-#define MCCR_CM1 1
-
-/* sim_core_attach device argument. */
-extern device frv_devices;
-
-/* FIXME: Temporary, until device support ready. */
-struct _device { int foo; };
-
/* maintain the address of the start of the previous VLIW insn sequence. */
extern IADDR previous_vliw_pc;
+extern CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot;
/* Hardware status. */
#define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
#define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
#define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
+#define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >> 1) & 1)
+#define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >> 8) & 7)
+#define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
#define GET_MSR_EMCI(msr) ( \
((msr) >> 24) & 0x1 \
)
+#define GET_MSR_MPEM(msr) ( \
+ ((msr) >> 27) & 0x1 \
+)
#define GET_MSR_SRDAV(msr) ( \
((msr) >> 28) & 0x1 \
)
struct frv_interrupt_queue_element *
frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
+struct frv_interrupt_queue_element *
+frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
+
+struct frv_interrupt_queue_element *
+frv_queue_float_disabled_interrupt (SIM_CPU *);
+
+struct frv_interrupt_queue_element *
+frv_queue_media_disabled_interrupt (SIM_CPU *);
+
struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);