Decouple inferior_ptid/inferior_thread(); dup ptids in thread list (PR 25412)

[deliverable/binutils-gdb.git] / sim / frv / mloop.in

diff --git a/sim/frv/mloop.in b/sim/frv/mloop.in
index 2d1726da573649457dd6f3cbc56b878cdae1f4d0..41d7a0d2a592e4c7dae077b67f16b3b66e31aee2 100644 (file)
--- a/sim/frv/mloop.in
+++ b/sim/frv/mloop.in
@@ -1,22 +1,21 @@
 # Simulator main loop for frv. -*- C -*-
-# Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+# Copyright (C) 1998-2020 Free Software Foundation, Inc.
 # Contributed by Red Hat.
 #
 # This file is part of the GNU Simulators.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
 # Syntax:
 # /bin/sh mainloop.in command
@@ -93,8 +92,8 @@ execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
            }
          else
            model_insn = FRV_INSN_NO_MODELING;
-         TRACE_INSN_INIT (current_cpu, abuf, 1);
-         TRACE_INSN (current_cpu, idesc->idata,
+         CGEN_TRACE_INSN_INIT (current_cpu, abuf, 1);
+         CGEN_TRACE_INSN (current_cpu, idesc->idata,
                      (const struct argbuf *) abuf, abuf->addr);
        }
 #if WITH_SCACHE
@@ -117,7 +116,7 @@ execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
                cycles = 1;
              @cpu@_model_insn_after (current_cpu, sc->last_insn_p, cycles);
            }
-         TRACE_INSN_FINI (current_cpu, abuf, 1);
+         CGEN_TRACE_INSN_FINI (current_cpu, abuf, 1);
        }
     }
 
@@ -391,10 +390,12 @@ static void
   switch (STATE_ARCHITECTURE (sd)->mach)
     {
     case bfd_mach_fr400:
+    case bfd_mach_fr450:
       simulate_dual_insn_prefetch (current_cpu, vpc, 8);
       break;
     case bfd_mach_frvtomcat:
     case bfd_mach_fr500:
+    case bfd_mach_fr550:
     case bfd_mach_frv:
       simulate_dual_insn_prefetch (current_cpu, vpc, 16);
       break;
@@ -454,6 +455,7 @@ cat <<EOF
   int first_insn_p = 1;
   int last_insn_p = 0;
   int ninsns;
+  CGEN_ATTR_VALUE_ENUM_TYPE slot;
 
   /* If the timer is enabled, then enable model profiling.  This is because
      the timer needs accurate cycles counts to work properly.  */
@@ -465,6 +467,7 @@ cat <<EOF
   vliw = CPU_VLIW (current_cpu);
   frv_vliw_reset (vliw, STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach,
                   CPU_ELF_FLAGS (current_cpu));
+  frv_current_fm_slot = UNIT_NIL;
 
   for (ninsns = 0; ! last_insn_p && ninsns < FRV_VLIW_SIZE; ++ninsns)
     {
@@ -484,6 +487,9 @@ cat <<EOF
       if (! error)
         frv_vliw_setup_insn (current_cpu, insn);
       frv_detect_insn_access_interrupts (current_cpu, sc);
+      slot = (*vliw->current_vliw)[vliw->next_slot - 1];
+      if (slot >= UNIT_FM0 && slot <= UNIT_FM3)
+        frv_current_fm_slot = slot;
 
       vpc = execute (current_cpu, sc, FAST_P);