Add the operand encoding types for the new Armv8.2-a back-ported instructions. These...

[deliverable/binutils-gdb.git] / sim / iq2000 / cpu.h

diff --git a/sim/iq2000/cpu.h b/sim/iq2000/cpu.h
index 9150577eab6525c6c8f2d681cdd8b1fed2822f0a..88310867087de013bf54267bfc3236e9edd4eac4 100644 (file)
--- a/sim/iq2000/cpu.h
+++ b/sim/iq2000/cpu.h
@@ -2,23 +2,22 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright 1996-2017 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -32,6 +31,12 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Maximum number of instructions that can be executed in parallel.  */
 #define MAX_PARALLEL_INSNS 1
 
+/* The size of an "int" needed to hold an instruction word.
+   This is usually 32 bits, but some architectures needs 64 bits.  */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
 /* CPU state information.  */
 typedef struct {
   /* Hardware elements.  */
@@ -78,7 +83,7 @@ typedef struct {
 union sem_fields {
   struct { /* no operands */
     int empty;
-  } fmt_empty;
+  } sfmt_empty;
   struct { /*  */
     IADDR i_jmptarg;
   } sfmt_j;
@@ -272,7 +277,7 @@ struct scache {
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+  f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 
 #define EXTRACT_IFMT_BBV_VARS \
   UINT f_opcode; \
@@ -285,7 +290,7 @@ struct scache {
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+  f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 
 #define EXTRACT_IFMT_BGEZ_VARS \
   UINT f_opcode; \
@@ -298,7 +303,7 @@ struct scache {
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+  f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 
 #define EXTRACT_IFMT_JALR_VARS \
   UINT f_opcode; \
@@ -431,7 +436,7 @@ struct scache {
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+  f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 
 #define EXTRACT_IFMT_CFC0_VARS \
   UINT f_opcode; \