Emit a warning when -z relro is unsupported

[deliverable/binutils-gdb.git] / sim / lm32 / cpu.h

diff --git a/sim/lm32/cpu.h b/sim/lm32/cpu.h
index 8b44fa37d663353d9719cf91456b2a5be0a82009..92492cd4d1290a6bfac6498765360fa5399ca77c 100644 (file)
--- a/sim/lm32/cpu.h
+++ b/sim/lm32/cpu.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2009 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,8 +17,7 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -32,6 +31,12 @@ This file is part of the GNU simulators.
 /* Maximum number of instructions that can be executed in parallel.  */
 #define MAX_PARALLEL_INSNS 1
 
+/* The size of an "int" needed to hold an instruction word.
+   This is usually 32 bits, but some architectures needs 64 bits.  */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
 /* CPU state information.  */
 typedef struct {
   /* Hardware elements.  */
@@ -73,7 +78,7 @@ typedef struct {
 union sem_fields {
   struct { /* no operands */
     int empty;
-  } fmt_empty;
+  } sfmt_empty;
   struct { /*  */
     IADDR i_call;
   } sfmt_bi;
@@ -192,7 +197,7 @@ struct scache {
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_imm = EXTRACT_LSB0_INT (insn, 32, 15, 16); \
+  f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
 
 #define EXTRACT_IFMT_ANDI_VARS \
   UINT f_opcode; \
@@ -242,7 +247,7 @@ struct scache {
 #define EXTRACT_IFMT_BI_CODE \
   length = 4; \
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_call = ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 25, 26)) << (6))) >> (4)))); \
+  f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4)))); \
 
 #define EXTRACT_IFMT_BE_VARS \
   UINT f_opcode; \
@@ -255,7 +260,7 @@ struct scache {
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
   f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_branch = ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (16))) >> (14)))); \
+  f_branch = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (16))) >> (14)))); \
 
 #define EXTRACT_IFMT_ORI_VARS \
   UINT f_opcode; \