SET_H_GR (30, ip);
/* Save and clear interrupt enable. */
SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
- CIA_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
+ CPU_PC_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
sim_stopped, SIM_SIGSEGV);
break;
SET_H_GR (30, ip);
/* Save and clear interrupt enable. */
SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
- CIA_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
+ CPU_PC_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
sim_stopped, SIM_SIGBUS);
break;