Don't write to inferior_ptid in corelow.c

[deliverable/binutils-gdb.git] / sim / m32r / arch.c

diff --git a/sim/m32r/arch.c b/sim/m32r/arch.c
index 39b9b9629da62e5db8fb18b1dc40a1f3d7a038bc..f1d38c3f96a779d03835958aee3d3bc6257ec48e 100644 (file)
--- a/sim/m32r/arch.c
+++ b/sim/m32r/arch.c
@@ -1,34 +1,40 @@
 /* Simulator support for m32r.
 
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-This file is part of the GNU Simulators.
+Copyright 1996-2020 Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+This file is part of the GNU simulators.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
 #include "sim-main.h"
-#include "cpu-sim.h"
-#include "cpu-opc.h"
-
-const MACH machs[] = {
-  { "m32r", 32, 32, & m32r_models[0], & m32r_imp_properties },
-/* start-sanitize-m32rx */
-  { "m32rx", 32, 32, & m32rx_models[0], & m32rx_imp_properties },
-/* end-sanitize-m32rx */
-  { 0 }
+#include "bfd.h"
+
+const SIM_MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_M32RBF
+  & m32r_mach,
+#endif
+#ifdef HAVE_CPU_M32RXF
+  & m32rx_mach,
+#endif
+#ifdef HAVE_CPU_M32R2F
+  & m32r2_mach,
+#endif
+  0
 };