-/* CPU family header for m32r.
+/* CPU family header for m32rbf.
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+THIS FILE IS MACHINE GENERATED WITH CGEN.
-This file is part of the GNU Simulators.
+Copyright 1996-2020 Free Software Foundation, Inc.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+This file is part of the GNU simulators.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef CPU_M32R_H
-#define CPU_M32R_H
+#ifndef CPU_M32RBF_H
+#define CPU_M32RBF_H
/* Maximum number of instructions that are fetched at a time.
This is for LIW type instructions sets (e.g. m32r). */
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
+/* The size of an "int" needed to hold an instruction word.
+ This is usually 32 bits, but some architectures needs 64 bits. */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
/* CPU state information. */
typedef struct {
/* Hardware elements. */
#define GET_H_GR(a1) CPU (h_gr)[a1]
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
/* control registers */
- SI h_cr[7];
-#define GET_H_CR(a1) CPU (h_cr)[a1]
-#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
+ USI h_cr[16];
+#define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
+#define SET_H_CR(index, x) \
+do { \
+m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
+;} while (0)
/* accumulator */
DI h_accum;
-#define GET_H_ACCUM() CPU (h_accum)
-#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
+#define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
+#define SET_H_ACCUM(x) \
+do { \
+m32rbf_h_accum_set_handler (current_cpu, (x));\
+;} while (0)
/* condition bit */
- UBI h_cond;
+ BI h_cond;
#define GET_H_COND() CPU (h_cond)
#define SET_H_COND(x) (CPU (h_cond) = (x))
- /* sm */
- UBI h_sm;
-#define GET_H_SM() CPU (h_sm)
-#define SET_H_SM(x) (CPU (h_sm) = (x))
- /* bsm */
- UBI h_bsm;
-#define GET_H_BSM() CPU (h_bsm)
-#define SET_H_BSM(x) (CPU (h_bsm) = (x))
- /* ie */
- UBI h_ie;
-#define GET_H_IE() CPU (h_ie)
-#define SET_H_IE(x) (CPU (h_ie) = (x))
- /* bie */
- UBI h_bie;
-#define GET_H_BIE() CPU (h_bie)
-#define SET_H_BIE(x) (CPU (h_bie) = (x))
- /* bcond */
- UBI h_bcond;
-#define GET_H_BCOND() CPU (h_bcond)
-#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
- /* bpc */
- SI h_bpc;
-#define GET_H_BPC() CPU (h_bpc)
-#define SET_H_BPC(x) (CPU (h_bpc) = (x))
+ /* psw part of psw */
+ UQI h_psw;
+#define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
+#define SET_H_PSW(x) \
+do { \
+m32rbf_h_psw_set_handler (current_cpu, (x));\
+;} while (0)
+ /* backup psw */
+ UQI h_bpsw;
+#define GET_H_BPSW() CPU (h_bpsw)
+#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
+ /* backup bpsw */
+ UQI h_bbpsw;
+#define GET_H_BBPSW() CPU (h_bbpsw)
+#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
+ /* lock */
+ BI h_lock;
+#define GET_H_LOCK() CPU (h_lock)
+#define SET_H_LOCK(x) (CPU (h_lock) = (x))
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
- /* CPU profiling state information. */
- struct {
- /* general registers */
- unsigned long h_gr;
- } profile;
-#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
-} M32R_CPU_DATA;
+} M32RBF_CPU_DATA;
+
+/* Cover fns for register access. */
+USI m32rbf_h_pc_get (SIM_CPU *);
+void m32rbf_h_pc_set (SIM_CPU *, USI);
+SI m32rbf_h_gr_get (SIM_CPU *, UINT);
+void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
+USI m32rbf_h_cr_get (SIM_CPU *, UINT);
+void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
+DI m32rbf_h_accum_get (SIM_CPU *);
+void m32rbf_h_accum_set (SIM_CPU *, DI);
+BI m32rbf_h_cond_get (SIM_CPU *);
+void m32rbf_h_cond_set (SIM_CPU *, BI);
+UQI m32rbf_h_psw_get (SIM_CPU *);
+void m32rbf_h_psw_set (SIM_CPU *, UQI);
+UQI m32rbf_h_bpsw_get (SIM_CPU *);
+void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
+UQI m32rbf_h_bbpsw_get (SIM_CPU *);
+void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
+BI m32rbf_h_lock_get (SIM_CPU *);
+void m32rbf_h_lock_set (SIM_CPU *, BI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN m32rbf_fetch_register;
+extern CPUREG_STORE_FN m32rbf_store_register;
-/* FIXME: length parm to decode() is currently unneeded. */
-extern DECODE *m32r_decode (SIM_CPU *, insn_t /*, int*/);
+typedef struct {
+ UINT h_gr;
+} MODEL_M32R_D_DATA;
+
+typedef struct {
+ int empty;
+} MODEL_TEST_DATA;
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } sfmt_empty;
+ struct { /* */
+ UINT f_uimm8;
+ } sfmt_clrpsw;
+ struct { /* */
+ UINT f_uimm4;
+ } sfmt_trap;
+ struct { /* */
+ IADDR i_disp24;
+ unsigned char out_h_gr_SI_14;
+ } sfmt_bl24;
+ struct { /* */
+ IADDR i_disp8;
+ unsigned char out_h_gr_SI_14;
+ } sfmt_bl8;
+ struct { /* */
+ SI* i_dr;
+ UINT f_hi16;
+ UINT f_r1;
+ unsigned char out_dr;
+ } sfmt_seth;
+ struct { /* */
+ ADDR i_uimm24;
+ SI* i_dr;
+ UINT f_r1;
+ unsigned char out_dr;
+ } sfmt_ld24;
+ struct { /* */
+ SI* i_sr;
+ UINT f_r2;
+ unsigned char in_sr;
+ unsigned char out_h_gr_SI_14;
+ } sfmt_jl;
+ struct { /* */
+ SI* i_sr;
+ INT f_simm16;
+ UINT f_r2;
+ UINT f_uimm3;
+ unsigned char in_sr;
+ } sfmt_bset;
+ struct { /* */
+ SI* i_dr;
+ UINT f_r1;
+ UINT f_uimm5;
+ unsigned char in_dr;
+ unsigned char out_dr;
+ } sfmt_slli;
+ struct { /* */
+ SI* i_dr;
+ INT f_simm8;
+ UINT f_r1;
+ unsigned char in_dr;
+ unsigned char out_dr;
+ } sfmt_addi;
+ struct { /* */
+ SI* i_src1;
+ SI* i_src2;
+ UINT f_r1;
+ UINT f_r2;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ unsigned char out_src2;
+ } sfmt_st_plus;
+ struct { /* */
+ SI* i_src1;
+ SI* i_src2;
+ INT f_simm16;
+ UINT f_r1;
+ UINT f_r2;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } sfmt_st_d;
+ struct { /* */
+ SI* i_dr;
+ SI* i_sr;
+ UINT f_r1;
+ UINT f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ unsigned char out_sr;
+ } sfmt_ld_plus;
+ struct { /* */
+ IADDR i_disp16;
+ SI* i_src1;
+ SI* i_src2;
+ UINT f_r1;
+ UINT f_r2;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } sfmt_beq;
+ struct { /* */
+ SI* i_dr;
+ SI* i_sr;
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_uimm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } sfmt_and3;
+ struct { /* */
+ SI* i_dr;
+ SI* i_sr;
+ INT f_simm16;
+ UINT f_r1;
+ UINT f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } sfmt_add3;
+ struct { /* */
+ SI* i_dr;
+ SI* i_sr;
+ UINT f_r1;
+ UINT f_r2;
+ unsigned char in_dr;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } sfmt_add;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
- unsigned int length;
- PCADDR addr;
- const struct cgen_insn *opcode;
- /* unsigned long insn; - no longer needed */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
/* cpu specific data follows */
- union {
- struct { /* e.g. add $dr,$sr */
- SI * f_r1;
- SI * f_r2;
- } fmt_0_add;
- struct { /* e.g. add3 $dr,$sr,$slo16 */
- SI * f_r1;
- SI * f_r2;
- HI f_simm16;
- } fmt_1_add3;
- struct { /* e.g. and3 $dr,$sr,$uimm16 */
- SI * f_r1;
- SI * f_r2;
- USI f_uimm16;
- } fmt_2_and3;
- struct { /* e.g. or3 $dr,$sr,$ulo16 */
- SI * f_r1;
- SI * f_r2;
- UHI f_uimm16;
- } fmt_3_or3;
- struct { /* e.g. addi $dr,$simm8 */
- SI * f_r1;
- SI f_simm8;
- } fmt_4_addi;
- struct { /* e.g. addv3 $dr,$sr,$simm16 */
- SI * f_r1;
- SI * f_r2;
- SI f_simm16;
- } fmt_5_addv3;
- struct { /* e.g. addx $dr,$sr */
- SI * f_r1;
- SI * f_r2;
- } fmt_6_addx;
- struct { /* e.g. bc $disp8 */
- IADDR f_disp8;
- } fmt_7_bc8;
- struct { /* e.g. bc $disp24 */
- IADDR f_disp24;
- } fmt_8_bc24;
- struct { /* e.g. beq $src1,$src2,$disp16 */
- SI * f_r1;
- SI * f_r2;
- IADDR f_disp16;
- } fmt_9_beq;
- struct { /* e.g. beqz $src2,$disp16 */
- SI * f_r2;
- IADDR f_disp16;
- } fmt_10_beqz;
- struct { /* e.g. bl $disp8 */
- IADDR f_disp8;
- } fmt_11_bl8;
- struct { /* e.g. bl $disp24 */
- IADDR f_disp24;
- } fmt_12_bl24;
- struct { /* e.g. bra $disp8 */
- IADDR f_disp8;
- } fmt_13_bra8;
- struct { /* e.g. bra $disp24 */
- IADDR f_disp24;
- } fmt_14_bra24;
- struct { /* e.g. cmp $src1,$src2 */
- SI * f_r1;
- SI * f_r2;
- } fmt_15_cmp;
- struct { /* e.g. cmpi $src2,$simm16 */
- SI * f_r2;
- SI f_simm16;
- } fmt_16_cmpi;
- struct { /* e.g. cmpui $src2,$uimm16 */
- SI * f_r2;
- USI f_uimm16;
- } fmt_17_cmpui;
- struct { /* e.g. div $dr,$sr */
- SI * f_r1;
- SI * f_r2;
- } fmt_18_div;
- struct { /* e.g. jl $sr */
- SI * f_r2;
- } fmt_19_jl;
- struct { /* e.g. jmp $sr */
- SI * f_r2;
- } fmt_20_jmp;
- struct { /* e.g. ld $dr,@$sr */
- SI * f_r1;
- SI * f_r2;
- } fmt_21_ld;
- struct { /* e.g. ld $dr,@($slo16,$sr) */
- SI * f_r1;
- SI * f_r2;
- HI f_simm16;
- } fmt_22_ld_d;
- struct { /* e.g. ldb $dr,@$sr */
- SI * f_r1;
- SI * f_r2;
- } fmt_23_ldb;
- struct { /* e.g. ldb $dr,@($slo16,$sr) */
- SI * f_r1;
- SI * f_r2;
- HI f_simm16;
- } fmt_24_ldb_d;
- struct { /* e.g. ldh $dr,@$sr */
- SI * f_r1;
- SI * f_r2;
- } fmt_25_ldh;
- struct { /* e.g. ldh $dr,@($slo16,$sr) */
- SI * f_r1;
- SI * f_r2;
- HI f_simm16;
- } fmt_26_ldh_d;
- struct { /* e.g. ld24 $dr,$uimm24 */
- SI * f_r1;
- ADDR f_uimm24;
- } fmt_27_ld24;
- struct { /* e.g. ldi $dr,$simm8 */
- SI * f_r1;
- SI f_simm8;
- } fmt_28_ldi8;
- struct { /* e.g. ldi $dr,$slo16 */
- SI * f_r1;
- HI f_simm16;
- } fmt_29_ldi16;
- struct { /* e.g. machi $src1,$src2 */
- SI * f_r1;
- SI * f_r2;
- } fmt_30_machi;
- struct { /* e.g. mv $dr,$sr */
- SI * f_r1;
- SI * f_r2;
- } fmt_31_mv;
- struct { /* e.g. mvfachi $dr */
- SI * f_r1;
- } fmt_32_mvfachi;
- struct { /* e.g. mvfc $dr,$scr */
- SI * f_r1;
- UINT f_r2;
- } fmt_33_mvfc;
- struct { /* e.g. mvtachi $src1 */
- SI * f_r1;
- } fmt_34_mvtachi;
- struct { /* e.g. mvtc $sr,$dcr */
- UINT f_r1;
- SI * f_r2;
- } fmt_35_mvtc;
- struct { /* e.g. nop */
- int empty;
- } fmt_36_nop;
- struct { /* e.g. rac */
- int empty;
- } fmt_37_rac;
- struct { /* e.g. seth $dr,$hi16 */
- SI * f_r1;
- UHI f_hi16;
- } fmt_38_seth;
- struct { /* e.g. slli $dr,$uimm5 */
- SI * f_r1;
- USI f_uimm5;
- } fmt_39_slli;
- struct { /* e.g. st $src1,@($slo16,$src2) */
- SI * f_r1;
- SI * f_r2;
- HI f_simm16;
- } fmt_40_st_d;
- struct { /* e.g. trap $uimm4 */
- USI f_uimm4;
- } fmt_41_trap;
- } fields;
-#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
- unsigned long h_gr_get;
- unsigned long h_gr_set;
-#endif
+ union sem semantic;
+ int written;
+ union sem_fields fields;
};
/* A cached insn.
- This is also used in the non-scache case. In this situation we assume
- the cache size is 1, and do a few things a little differently. */
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
struct scache {
- IADDR next;
- union {
-#if ! WITH_SEM_SWITCH_FULL
- SEMANTIC_FN *sem_fn;
-#endif
-#if ! WITH_SEM_SWITCH_FAST
-#if WITH_SCACHE
- SEMANTIC_CACHE_FN *sem_fast_fn;
-#else
- SEMANTIC_FN *sem_fast_fn;
-#endif
-#endif
-#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
-#ifdef __GNUC__
- void *sem_case;
-#else
- int sem_case;
-#endif
-#endif
- } semantic;
struct argbuf argbuf;
};
/* Macros to simplify extraction, reading and semantic code.
These define and assign the local vars that contain the insn's fields. */
-#define EXTRACT_FMT_0_ADD_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_ADD_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_0_ADD_CODE \
+#define EXTRACT_IFMT_ADD_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-#define EXTRACT_FMT_1_ADD3_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_ADD3_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
- int f_simm16; \
+ INT f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_1_ADD3_CODE \
+#define EXTRACT_IFMT_ADD3_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_2_AND3_VARS \
- /* Instruction fields. */ \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_AND3_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
-#define EXTRACT_FMT_2_AND3_CODE \
+#define EXTRACT_IFMT_AND3_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_3_OR3_VARS \
- /* Instruction fields. */ \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_OR3_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
-#define EXTRACT_FMT_3_OR3_CODE \
+#define EXTRACT_IFMT_OR3_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_4_ADDI_VARS \
- /* Instruction fields. */ \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADDI_VARS \
UINT f_op1; \
UINT f_r1; \
- int f_simm8; \
+ INT f_simm8; \
unsigned int length;
-#define EXTRACT_FMT_4_ADDI_CODE \
+#define EXTRACT_IFMT_ADDI_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
-#define EXTRACT_FMT_5_ADDV3_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_ADDV3_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
- int f_simm16; \
+ INT f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_5_ADDV3_CODE \
+#define EXTRACT_IFMT_ADDV3_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_6_ADDX_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- unsigned int length;
-#define EXTRACT_FMT_6_ADDX_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
-#define EXTRACT_FMT_7_BC8_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_BC8_VARS \
UINT f_op1; \
UINT f_r1; \
- int f_disp8; \
+ SI f_disp8; \
unsigned int length;
-#define EXTRACT_FMT_7_BC8_CODE \
+#define EXTRACT_IFMT_BC8_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-#define EXTRACT_FMT_8_BC24_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
UINT f_r1; \
- int f_disp24; \
+ SI f_disp24; \
unsigned int length;
-#define EXTRACT_FMT_8_BC24_CODE \
+#define EXTRACT_IFMT_BC24_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
-#define EXTRACT_FMT_9_BEQ_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
- int f_disp16; \
+ SI f_disp16; \
unsigned int length;
-#define EXTRACT_FMT_9_BEQ_CODE \
+#define EXTRACT_IFMT_BEQ_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
-
-#define EXTRACT_FMT_10_BEQZ_VARS \
- /* Instruction fields. */ \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
- int f_disp16; \
- unsigned int length;
-#define EXTRACT_FMT_10_BEQZ_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
-
-#define EXTRACT_FMT_11_BL8_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- int f_disp8; \
- unsigned int length;
-#define EXTRACT_FMT_11_BL8_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
-
-#define EXTRACT_FMT_12_BL24_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- int f_disp24; \
- unsigned int length;
-#define EXTRACT_FMT_12_BL24_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
-
-#define EXTRACT_FMT_13_BRA8_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- int f_disp8; \
- unsigned int length;
-#define EXTRACT_FMT_13_BRA8_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
-
-#define EXTRACT_FMT_14_BRA24_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- int f_disp24; \
+ SI f_disp16; \
unsigned int length;
-#define EXTRACT_FMT_14_BRA24_CODE \
+#define EXTRACT_IFMT_BEQZ_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
-#define EXTRACT_FMT_15_CMP_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_15_CMP_CODE \
+#define EXTRACT_IFMT_CMP_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-#define EXTRACT_FMT_16_CMPI_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- int f_simm16; \
- unsigned int length;
-#define EXTRACT_FMT_16_CMPI_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_17_CMPUI_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- UINT f_uimm16; \
- unsigned int length;
-#define EXTRACT_FMT_17_CMPUI_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_18_DIV_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_CMPI_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
- int f_simm16; \
+ INT f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_18_DIV_CODE \
+#define EXTRACT_IFMT_CMPI_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_19_JL_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- unsigned int length;
-#define EXTRACT_FMT_19_JL_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
-#define EXTRACT_FMT_20_JMP_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_DIV_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
+ INT f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_20_JMP_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+#define EXTRACT_IFMT_DIV_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
-#define EXTRACT_FMT_21_LD_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_JL_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_21_LD_CODE \
+#define EXTRACT_IFMT_JL_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-#define EXTRACT_FMT_22_LD_D_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_LD24_VARS \
UINT f_op1; \
UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- int f_simm16; \
+ UINT f_uimm24; \
unsigned int length;
-#define EXTRACT_FMT_22_LD_D_CODE \
+#define EXTRACT_IFMT_LD24_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_23_LDB_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- unsigned int length;
-#define EXTRACT_FMT_23_LDB_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
-#define EXTRACT_FMT_24_LDB_D_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_LDI16_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
- int f_simm16; \
+ INT f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_24_LDB_D_CODE \
+#define EXTRACT_IFMT_LDI16_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_25_LDH_VARS \
- /* Instruction fields. */ \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_MVFACHI_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_25_LDH_CODE \
+#define EXTRACT_IFMT_MVFACHI_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-#define EXTRACT_FMT_26_LDH_D_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_MVFC_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
- int f_simm16; \
- unsigned int length;
-#define EXTRACT_FMT_26_LDH_D_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_27_LD24_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_uimm24; \
- unsigned int length;
-#define EXTRACT_FMT_27_LD24_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
-
-#define EXTRACT_FMT_28_LDI8_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- int f_simm8; \
unsigned int length;
-#define EXTRACT_FMT_28_LDI8_CODE \
+#define EXTRACT_IFMT_MVFC_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-#define EXTRACT_FMT_29_LDI16_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_MVTACHI_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
- int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_29_LDI16_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_30_MACHI_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- unsigned int length;
-#define EXTRACT_FMT_30_MACHI_CODE \
+#define EXTRACT_IFMT_MVTACHI_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-#define EXTRACT_FMT_31_MV_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_MVTC_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_31_MV_CODE \
+#define EXTRACT_IFMT_MVTC_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-#define EXTRACT_FMT_32_MVFACHI_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_NOP_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_32_MVFACHI_CODE \
+#define EXTRACT_IFMT_NOP_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-#define EXTRACT_FMT_33_MVFC_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_SETH_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
+ UINT f_hi16; \
unsigned int length;
-#define EXTRACT_FMT_33_MVFC_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+#define EXTRACT_IFMT_SETH_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-#define EXTRACT_FMT_34_MVTACHI_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_SLLI_VARS \
UINT f_op1; \
UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
+ UINT f_shift_op2; \
+ UINT f_uimm5; \
unsigned int length;
-#define EXTRACT_FMT_34_MVTACHI_CODE \
+#define EXTRACT_IFMT_SLLI_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
+ f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
-#define EXTRACT_FMT_35_MVTC_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_ST_D_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
+ INT f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_35_MVTC_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+#define EXTRACT_IFMT_ST_D_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
-#define EXTRACT_FMT_36_NOP_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_TRAP_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
- UINT f_r2; \
+ UINT f_uimm4; \
unsigned int length;
-#define EXTRACT_FMT_36_NOP_CODE \
+#define EXTRACT_IFMT_TRAP_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-#define EXTRACT_FMT_37_RAC_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_CLRPSW_VARS \
UINT f_op1; \
UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
+ UINT f_uimm8; \
unsigned int length;
-#define EXTRACT_FMT_37_RAC_CODE \
+#define EXTRACT_IFMT_CLRPSW_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
-#define EXTRACT_FMT_38_SETH_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_BSET_VARS \
UINT f_op1; \
- UINT f_r1; \
+ UINT f_bit4; \
+ UINT f_uimm3; \
UINT f_op2; \
UINT f_r2; \
- UINT f_hi16; \
+ INT f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_38_SETH_CODE \
+#define EXTRACT_IFMT_BSET_CODE \
length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_39_SLLI_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_shift_op2; \
- UINT f_uimm5; \
- unsigned int length;
-#define EXTRACT_FMT_39_SLLI_CODE \
- length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
- f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
+ f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
-#define EXTRACT_FMT_40_ST_D_VARS \
- /* Instruction fields. */ \
+#define EXTRACT_IFMT_BTST_VARS \
UINT f_op1; \
- UINT f_r1; \
+ UINT f_bit4; \
+ UINT f_uimm3; \
UINT f_op2; \
UINT f_r2; \
- int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_40_ST_D_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_41_TRAP_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_uimm4; \
- unsigned int length;
-#define EXTRACT_FMT_41_TRAP_CODE \
+#define EXTRACT_IFMT_BTST_CODE \
length = 2; \
- f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
- f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
+ f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
-#endif /* CPU_M32R_H */
+#endif /* CPU_M32RBF_H */
projects / deliverable / binutils-gdb.git / blobdiff