THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2009 Free Software Foundation, Inc.
+Copyright 1996-2019 Free Software Foundation, Inc.
This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+ with this program; if not, see <http://www.gnu.org/licenses/>.
*/
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 2
+/* The size of an "int" needed to hold an instruction word.
+ This is usually 32 bits, but some architectures needs 64 bits. */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
/* CPU state information. */
typedef struct {
/* Hardware elements. */
union sem_fields {
struct { /* no operands */
int empty;
- } fmt_empty;
+ } sfmt_empty;
struct { /* */
UINT f_uimm8;
} sfmt_clrpsw;
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_AND3_VARS \
UINT f_op1; \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
- f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
+ f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_ADDV3_VARS \
UINT f_op1; \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_BC8_VARS \
UINT f_op1; \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
- f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
- f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_CMPZ_VARS \
UINT f_op1; \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_JC_VARS \
UINT f_op1; \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_MACHI_A_VARS \
UINT f_op1; \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_TRAP_VARS \
UINT f_op1; \
f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+ f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_BTST_VARS \
UINT f_op1; \