/* Simulator CPU header for m32r.
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+THIS FILE IS MACHINE GENERATED WITH CGEN.
-This file is part of the GNU Simulators.
+Copyright 1996-2020 Free Software Foundation, Inc.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+This file is part of the GNU simulators.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef M32R_CPUALL_H
#define M32R_CPUALL_H
-extern const IMP_PROPERTIES m32r_imp_properties;
+/* Include files for each cpu family. */
+
+#ifdef WANT_CPU_M32RBF
+#include "eng.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+#ifdef WANT_CPU_M32RXF
+#include "engx.h"
+#include "cpux.h"
+#include "decodex.h"
+#endif
+
+#ifdef WANT_CPU_M32R2F
+#include "eng2.h"
+#include "cpu2.h"
+#include "decode2.h"
+#endif
-extern const MODEL m32r_models[];
+extern const SIM_MACH m32r_mach;
+extern const SIM_MACH m32rx_mach;
+extern const SIM_MACH m32r2_mach;
#ifndef WANT_CPU
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
- unsigned int length;
- PCADDR addr;
- const struct cgen_insn *opcode;
- /* unsigned long insn; - no longer needed */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
/* cpu specific data follows */
};
#endif
#ifndef WANT_CPU
/* A cached insn.
- This is also used in the non-scache case. In this situation we assume
- the cache size is 1, and do a few things a little differently. */
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
struct scache {
- IADDR next;
- union {
-#if ! WITH_SEM_SWITCH_FULL
- SEMANTIC_FN *sem_fn;
-#endif
-#if ! WITH_SEM_SWITCH_FAST
-#if WITH_SCACHE
- SEMANTIC_CACHE_FN *sem_fast_fn;
-#else
- SEMANTIC_FN *sem_fast_fn;
-#endif
-#endif
-#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
-#ifdef __GNUC__
- void *sem_case;
-#else
- int sem_case;
-#endif
-#endif
- } semantic;
struct argbuf argbuf;
};
#endif