Revert last commit, build problems.

[deliverable/binutils-gdb.git] / sim / m32r / m32r-sim.h

diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h
index 1dd1878ccd5eb31a0bdbe01ef6a1a7ec7eeed367..b1c2410fd84bb91698b44b1a2b084bb89e68cb71 100644 (file)
--- a/sim/m32r/m32r-sim.h
+++ b/sim/m32r/m32r-sim.h
@@ -41,27 +41,29 @@ extern int m32r_decode_gdb_ctrl_regnum (int);
    FIXME: Eventually move to cgen.  */
 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
 
+extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
+extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
+extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
+extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
+
 extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
-#define GET_H_CR(regno) \
-  XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
-#define SET_H_CR(regno, val) \
-  XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
 
 extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
-#define GET_H_PSW() \
-  XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
-#define SET_H_PSW(val) \
-  XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
 
 extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
-#define GET_H_ACCUM() \
-  XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
-#define SET_H_ACCUM(val) \
-  XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
 
+extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
+extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
+extern UQI m32rxf_h_psw_get_handler (SIM_CPU *);
+extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
+extern DI m32rxf_h_accum_get_handler (SIM_CPU *);
+extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
+
+extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
+extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
 \f
 /* Misc. profile data.  */
 
@@ -128,6 +130,32 @@ do { \
 \f
 /* Additional execution support.  */
 
+/* Result of semantic function is one of
+   - next address, branch only
+   - NEW_PC_SKIP, sc/snc insn
+   - NEW_PC_2, 2 byte non-branch non-sc/snc insn
+   - NEW_PC_4, 4 byte non-branch insn
+   The special values have bit 1 set so it's cheap to distinguish them.
+   This works because all cti's are defined to zero the bottom two bits
+   Note that the m32rx no longer doesn't implement its semantics with
+   functions, so this isn't used.  It's kept around should it be needed
+   again.  */
+/* FIXME: replace 0xffff0001 with 1?  */
+#define NEW_PC_BASE 0xffff0001
+#define NEW_PC_SKIP NEW_PC_BASE
+#define NEW_PC_2 (NEW_PC_BASE + 2)
+#define NEW_PC_4 (NEW_PC_BASE + 4)
+#define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
+
+/* Modify "next pc" support to handle parallel execution.
+   This is for the non-pbb case.  The m32rx no longer implements this.
+   It's kept around should it be needed again.  */
+#if defined (WANT_CPU_M32RXF) && ! WITH_SCACHE_PBB_M32RXF
+#undef SEM_NEXT_VPC
+#define SEM_NEXT_VPC(abuf, len) (NEW_PC_BASE + (len))
+#undef SEM_SKIP_INSN
+#define SEM_SKIP_INSN(cpu, sc, vpcvar, yes) FIXME
+#endif
 \f
 /* Hardware/device support.
    ??? Will eventually want to move device stuff to config files.  */
@@ -189,7 +217,7 @@ do { \
 
 /* Start address and length of all device support.  */
 #define M32R_DEVICE_ADDR       0xff000000
-#define M32R_DEVICE_LEN                0x00ffffff
+#define M32R_DEVICE_LEN                0x01000000
 
 /* sim_core_attach device argument.  */
 extern device m32r_devices;