#ifndef M32R_SIM_H
#define M32R_SIM_H
-/* Register numbers used in gdb interface. */
+/* gdb register numbers */
+#define PSW_REGNUM 16
+#define CBR_REGNUM 17
+#define SPI_REGNUM 18
+#define SPU_REGNUM 19
+#define BPC_REGNUM 20
#define PC_REGNUM 21
#define ACCL_REGNUM 22
#define ACCH_REGNUM 23
+#define ACC1L_REGNUM 24
+#define ACC1H_REGNUM 25
+#define BBPSW_REGNUM 26
+#define BBPC_REGNUM 27
+
+extern int m32r_decode_gdb_ctrl_regnum (int);
+
+/* Cover macros for hardware accesses.
+ FIXME: Eventually move to cgen. */
+#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
+
+extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
+extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
+extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
+extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
+
+extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
+extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
+
+extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
+extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
+
+extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
+extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
+
+extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
+extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
+extern UQI m32rxf_h_psw_get_handler (SIM_CPU *);
+extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
+extern DI m32rxf_h_accum_get_handler (SIM_CPU *);
+extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
+
+extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
+extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
\f
/* Misc. profile data. */
unsigned int long_count;
/* Working area for computing cycle counts. */
- unsigned long insn_cycles;
+ unsigned long insn_cycles; /* FIXME: delete */
unsigned long cti_stall;
unsigned long load_stall;
unsigned long biggest_cycles;
+
+ /* Bitmask of registers loaded by previous insn. */
+ unsigned int load_regs;
+ /* Bitmask of registers loaded by current insn. */
+ unsigned int load_regs_pending;
} M32R_MISC_PROFILE;
/* Initialize the working area. */
do { \
if (PROFILE_INSN_P (cpu) \
&& (addr & 3) != 0) \
- ++ CPU_M32R_MISC_PROFILE (cpu).fillnop_count; \
+ ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
} while (0)
/* This is invoked by the execute section of mloop{,x}.in. */
#define PROFILE_COUNT_PARINSNS(cpu) \
do { \
if (PROFILE_INSN_P (cpu)) \
- ++ CPU_M32R_MISC_PROFILE (cpu).parallel_count; \
+ ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
} while (0)
/* This is invoked by the execute section of mloop{,x}.in. */
#define PROFILE_COUNT_SHORTINSNS(cpu) \
do { \
if (PROFILE_INSN_P (cpu)) \
- ++ CPU_M32R_MISC_PROFILE (cpu).short_count; \
+ ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
} while (0)
/* This is invoked by the execute section of mloop{,x}.in. */
#define PROFILE_COUNT_LONGINSNS(cpu) \
do { \
if (PROFILE_INSN_P (cpu)) \
- ++ CPU_M32R_MISC_PROFILE (cpu).long_count; \
+ ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
} while (0)
\f
#define GETTWI GETTSI
- NEW_PC_2, 2 byte non-branch non-sc/snc insn
- NEW_PC_4, 4 byte non-branch insn
The special values have bit 1 set so it's cheap to distinguish them.
- This works because all cti's are defined to zero the bottom two bits. */
+ This works because all cti's are defined to zero the bottom two bits
+ Note that the m32rx no longer doesn't implement its semantics with
+ functions, so this isn't used. It's kept around should it be needed
+ again. */
/* FIXME: replace 0xffff0001 with 1? */
#define NEW_PC_BASE 0xffff0001
#define NEW_PC_SKIP NEW_PC_BASE
#define NEW_PC_4 (NEW_PC_BASE + 4)
#define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
-/* start-sanitize-m32rx */
-/* Modify "next pc" handling to handle parallel execution. */
-#ifdef WANT_CPU_M32RX
-#undef SEM_NEXT_PC
-#define SEM_NEXT_PC(abuf, len) (NEW_PC_BASE + (len))
+/* Modify "next pc" support to handle parallel execution.
+ This is for the non-pbb case. The m32rx no longer implements this.
+ It's kept around should it be needed again. */
+#if defined (WANT_CPU_M32RXF) && ! WITH_SCACHE_PBB_M32RXF
+#undef SEM_NEXT_VPC
+#define SEM_NEXT_VPC(abuf, len) (NEW_PC_BASE + (len))
+#undef SEM_SKIP_INSN
+#define SEM_SKIP_INSN(cpu, sc, vpcvar, yes) FIXME
#endif
-/* end-sanitize-m32rx */
-
-/* This macro is emitted by the generator to record branch addresses. */
-#define BRANCH_NEW_PC(var, addr) \
-do { var = (addr); } while (0)
\f
-/* Hardware/device support. */
+/* Hardware/device support.
+ ??? Will eventually want to move device stuff to config files. */
/* Exception, Interrupt, and Trap addresses */
#define EIT_SYSBREAK_ADDR 0x10
#define MCCR_CM1 1
/* Serial device addresses. */
+#ifdef M32R_EVA /* orig eva board, no longer supported */
#define UART_INCHAR_ADDR 0xff102013
#define UART_OUTCHAR_ADDR 0xff10200f
#define UART_STATUS_ADDR 0xff102006
-#define UART_INPUT_EMPTY 0x4
-#define UART_OUTPUT_EMPTY 0x1
+/* Indicate ready bit is inverted. */
+#define UART_INPUT_READY0
+#else
+/* These are the values for the MSA2000 board.
+ ??? Will eventually need to move this to a config file. */
+#define UART_INCHAR_ADDR 0xff004009
+#define UART_OUTCHAR_ADDR 0xff004007
+#define UART_STATUS_ADDR 0xff004002
+#endif
+
+#define UART_INPUT_READY 0x4
+#define UART_OUTPUT_READY 0x1
/* Start address and length of all device support. */
#define M32R_DEVICE_ADDR 0xff000000
-#define M32R_DEVICE_LEN 0x00ffffff
+#define M32R_DEVICE_LEN 0x01000000
/* sim_core_attach device argument. */
extern device m32r_devices;
projects / deliverable / binutils-gdb.git / blobdiff