/* Main simulator entry points specific to the M32R.
- Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This program is free software; you can redistribute it and/or modify
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sim-main.h"
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
#include "sim-options.h"
#include "libiberty.h"
#include "bfd.h"
+#ifdef HAVE_STRING_H
+#include <string.h>
+#else
+#ifdef HAVE_STRINGS_H
+#include <strings.h>
+#endif
+#endif
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+
static void free_state (SIM_DESC);
static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
sim_open (kind, callback, abfd, argv)
SIM_OPEN_KIND kind;
host_callback *callback;
- struct _bfd *abfd;
+ struct bfd *abfd;
char **argv;
{
- char c;
SIM_DESC sd = sim_state_alloc (kind, callback);
+ char c;
+ int i;
/* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
return 0;
}
+#ifdef HAVE_DV_SOCKSER /* FIXME: was done differently before */
+ if (dv_sockser_install (sd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+#endif
+
#if 0 /* FIXME: 'twould be nice if we could do this */
/* These options override any module options.
Obviously ambiguity should be avoided, however the caller may wish to
/* Allocate core managed memory if none specified by user.
Use address 4 here in case the user wanted address 0 unmapped. */
if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
- sim_do_commandf (sd, "memory region 0,0x%lx", M32R_DEFAULT_MEM_SIZE);
+ sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE);
/* check for/establish the reference program image */
if (sim_analyze_program (sd,
return 0;
}
- /* If both cpu model and state architecture are set, ensure they're
- compatible. If only one is set, set the other. If neither are set,
- use the default model. STATE_ARCHITECTURE is the bfd_arch_info data
- for the selected "mach" (bfd terminology). */
- {
- SIM_CPU *cpu = STATE_CPU (sd, 0);
-
- if (! STATE_ARCHITECTURE (sd)
- /* Only check cpu 0. STATE_ARCHITECTURE is for that one only. */
- && ! CPU_MACH (cpu))
- {
- /* Set the default model. */
- const MODEL *model = sim_model_lookup (WITH_DEFAULT_MODEL);
- sim_model_set (sd, NULL, model);
- }
- if (STATE_ARCHITECTURE (sd)
- && CPU_MACH (cpu))
- {
- if (strcmp (STATE_ARCHITECTURE (sd)->printable_name,
- MACH_NAME (CPU_MACH (cpu))) != 0)
- {
- sim_io_eprintf (sd, "invalid model `%s' for `%s'\n",
- MODEL_NAME (CPU_MODEL (cpu)),
- STATE_ARCHITECTURE (sd)->printable_name);
- free_state (sd);
- return 0;
- }
- }
- else if (STATE_ARCHITECTURE (sd))
- {
- /* Use the default model for the selected machine.
- The default model is the first one in the list. */
- const MACH *mach = sim_mach_lookup (STATE_ARCHITECTURE (sd)->printable_name);
- sim_model_set (sd, NULL, MACH_MODELS (mach));
- }
- else
- {
- STATE_ARCHITECTURE (sd) = bfd_scan_arch (MACH_NAME (CPU_MACH (cpu)));
- }
- }
-
/* Establish any remaining configuration options. */
if (sim_config (sd) != SIM_RC_OK)
{
return 0;
}
- /* Initialize various cgen things not done by common framework. */
- cgen_init (sd);
-
- /* Open a copy of the opcode table. */
- STATE_OPCODE_TABLE (sd) = m32r_cgen_opcode_open (STATE_ARCHITECTURE (sd)->mach,
- CGEN_ENDIAN_BIG);
- m32r_cgen_init_dis (STATE_OPCODE_TABLE (sd));
-
+ /* Open a copy of the cpu descriptor table. */
{
- int c;
-
- for (c = 0; c < MAX_NR_PROCESSORS; ++c)
+ CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
+ CGEN_ENDIAN_BIG);
+ for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
- /* Only needed for profiling, but the structure member is small. */
- memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c)), 0,
- sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c))));
- /* Hook in callback for reporting these stats */
- PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, c)))
- = print_m32r_misc_cpu;
+ SIM_CPU *cpu = STATE_CPU (sd, i);
+ CPU_CPU_DESC (cpu) = cd;
+ CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
}
+ m32r_cgen_init_dis (cd);
}
+ /* Initialize various cgen things not done by common framework.
+ Must be done after m32r_cgen_cpu_open. */
+ cgen_init (sd);
+
+ for (c = 0; c < MAX_NR_PROCESSORS; ++c)
+ {
+ /* Only needed for profiling, but the structure member is small. */
+ memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
+ sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i))));
+ /* Hook in callback for reporting these stats */
+ PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, i)))
+ = print_m32r_misc_cpu;
+ }
+
/* Store in a global so things like sparc32_dump_regs can be invoked
from the gdb command line. */
current_state = sd;
SIM_DESC sd;
int quitting;
{
- m32r_cgen_opcode_close (STATE_OPCODE_TABLE (sd));
+ m32r_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
sim_module_uninstall (sd);
}
\f
SIM_RC
sim_create_inferior (sd, abfd, argv, envp)
SIM_DESC sd;
- struct _bfd *abfd;
+ struct bfd *abfd;
char **argv;
char **envp;
{
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