+2002-03-07 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * interrupts.c (interrupts_reset): New function, setup interrupt
+ vector address according to cpu mode.
+ (interrupts_initialize): Move reset portion to the above.
+ (interrupt_names): New table to give a name to interrupts.
+ (idefs): Handle pulse accumulator interrupts.
+ (interrupts_info): Print the interrupt history.
+ (interrupt_option_handler): New function.
+ (interrupt_options): New table of options.
+ (interrupts_update_pending): Keep track of when interrupts are
+ raised and implement breakpoint-on-raise-interrupt.
+ (interrupts_process): Keep track of when interrupts are taken
+ and implement breakpoint-on-interrupt.
+ * interrupts.h (struct interrupt_history): Define.
+ (struct interrupt): Keep track of the interrupt history.
+ (interrupts_reset): Declare.
+ (interrupts_initialize): Update prototype.
+ * m68hc11_sim.c (cpu_reset): Reset interrupts.
+ (cpu_initialize): Cleanup.
+
+2001-07-28 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * dv-m68hc11eepr.c (m68hc11eepr_info): Fix print of current write
+ address.
+ (m68hc11eepr_port_event): Fix detach/attach logic.
+
+2001-07-22 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * Makefile.in (SIM_OBJS): Remove sim-resume.o
+ * interp.c (sim_resume): New function from sim-resume.c, install
+ the stepping event after having processed the pending ticks.
+ (has_stepped): Likewise.
+ (sim_info): Produce an output only if verbose or STATE_VERBOSE_P.
+
+2001-07-10 Andrew Cagney <ac131313@redhat.com>
+
+ * Makefile.in (gencode): Provide explicit path to gencode.c.
+
+2001-05-20 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * Makefile.in (M68HC11_OBJS): Add m68hc12int.o.
+ (m68hc12int.c): Generate using gencode -m6812.
+ (m68hc11int.c): Likewise with -m6811.
+
+ * gencode.c (m6811_opcode_patterns): New patterns for 68HC12.
+ (m6811_page1_opcodes): Remove duplicate entries.
+ (m6811_page2_opcodes): Likewise.
+ (m6811_page3_opcodes): Likewise.
+ (m6811_page4_opcodes): Likewise.
+ (m6812_page1_opcodes): New table for 68HC12 instructions.
+ (m6812_page2_opcodes): Likewise.
+ (gen_fetch_operands): New modes [] and &[] for 68HC12 operands.
+ (gen_save_result): Likewise.
+ (gen_interpreter_for_table): Handle 68HC11 and 68HC12 opcodes.
+ (cmp_opcode): New function for opcode comparision.
+ (prepare_table): Sort the opcodes.
+ (gen_interpreter): Prepare all the tables and generate either
+ a 68HC11 or a 68HC12 simulator.
+ (main): New options -m6811 and -m6812.
+
+ * m68hc11_sim.c (cpu_single_step): Use pointer to cpu interpretor.
+ (cpu_special): Simulation of some 68HC12 instructions.
+ (cpu_exg): New function.
+ (cpu_dbcc): Likewise.
+ (cpu_fetch_relbranch16): Likewise.
+ (cpu_push_all): Push according to 68HC11 or 68HC12.
+ (cpu_move16): Likewise.
+ (cpu_move8): Likewise.
+ (cpu_get_indexed_operand16): Likewise.
+ (cpu_get_indexed_operand8): Likewise.
+ (cpu_get_indexed_operand_addr): Likewise.
+ (cpu_set_reg, cpu_set_dst_reg, cpu_get_src_reg, cpu_get_reg): Likewise.
+ (cpu_reset): Setup INIT register according to architecture.
+
+ * sim-main.h (M6811_Special): Add 68HC12 specific instructions.
+ (_sim_cpu): Keep track of the cpu being simulated.
+ (cpu_get_tmp3, cpu_get_tmp2, cpu_set_tmp3, cpu_set_tmp2): New.
+ (cpu_m68hc11_push_uintxx): Rename of cpu_push_uintxx.
+ (cpu_m68hc11_pop_uint8): Likewise.
+ (cpu_m68hc12_push_uintxx): New functions for 68HC12.
+ (cpu_m68hc12_pop_uintxx): Likewise.
+ (cpu_exg, cpu_dbcc, cpu_move8, cpu_move16): Likewise,
+ (cpu_fetch_relbranch16): Likewise.
+ (cpu_interp_m6811): Rename of cpu_interp.
+ (cpu_interp_m6812): New function.
+ * interp.c (free_state): New function.
+ (dev_list_68hc12): New table.
+ (sim_board_reset): Reset depending on the cpu (HC11 or HC12).
+ (sim_hw_configure): New function.
+ (sim_prepare_for_program): New function.
+ (sim_open): Use above new functions.
+ (sim_close): Call free_state().
+ (sim_info): Print info according to cpu.
+ (sim_create_inferior): Use sim_prepare_for_program.
+ (sim_do_command): Configure the hardware after a change of the
+ architecture.
+
+2001-05-20 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * dv-m68hc11sio.c (m68hc11sio_tx_poll): Always check for
+ pending interrupts.
+ * interrupts.c (interrupts_process): Keep track of the last number
+ of masked insn cycles.
+ (interrupts_initialize): Clear last number of masked insn cycles.
+ (interrupts_info): Report them.
+ (interrupts_update_pending): Compute clear and set masks of
+ interrupts and clear the interrupt bits before setting them
+ (due to SCI interrupt sharing).
+ * interrupts.h (struct interrupts): New members last_mask_cycles
+ and xirq_last_mask_cycles.
+
+2000-11-26 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * dv-m68hc11.c (m68hc11cpu_io_read_buffer): Use attach_size
+ instead of a hard-coded value.
+ (m68hc11cpu_io_write_buffer): Likewise.
+ (dv_m68hc11_descriptor): Define a 68hc12 device.
+ * dv-m68hc11eepr.c (dv_m68hc11eepr_descriptor): Likewise.
+ * dv-m68hc11tim.c (dv_m68hc11tim_descriptor): Likewise.
+ * dv-m68hc11spi.c (dv_m68hc11spi_descriptor): Likewise.
+ * dv-m68hc11sio.c (dv_m68hc11sio_descriptor): Likewise.
+
+2000-11-22 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * dv-m68hc11.c (attach_m68hc11_regs): Register a delete handler.
+ (m68hc11cpu_delete): Delete handler to detach the address space.
+
+2000-11-24 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * dv-m68hc11eepr.c (attach_m68hc11eepr_regs): Use hw_malloc.
+ * dv-nvram.c (attach_nvram_regs): Use hw_free and hw_malloc
+ instead of free and malloc.
+
+2000-09-11 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * Makefile.in: Was missing from initial patch.
+
2000-09-10 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* interp.c (sim_store_register): Remove soft register hack.
projects / deliverable / binutils-gdb.git / blobdiff