+2002-02-27 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (mipsV): New model name. Also, add it to
+ all instructions and functions where it is appropriate.
+
+2002-02-18 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen: For all functions and instructions, list model
+ names that support that instruction one per line.
+
+2002-02-11 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen: Add some additional comments about supported
+ models, and about which instructions go where.
+ (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
+ order as is used in the rest of the file.
+
+2002-02-11 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
+ indicating that ALU32_END or ALU64_END are there to check
+ for overflow.
+ (DADD): Likewise, but also remove previous comment about
+ overflow checking.
+
+2002-02-10 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
+ DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
+ JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
+ SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
+ ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
+ fields (i.e., add and move commas) so that they more closely
+ match the MIPS ISA documentation opcode partitioning.
+
+2002-02-10 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (ADDI): Print immediate value.
+ (BREAK): Print code.
+ (DADDIU, DSRAV, DSRLV): Print correct instruction name.
+ (SLL): Print "nop" specially, and don't run the code
+ that does the shift for the "nop" case.
+
+2001-11-17 Fred Fish <fnf@redhat.com>
+
+ * sim-main.h (float_operation): Move enum declaration outside
+ of _sim_cpu struct declaration.
+
2001-04-12 Jim Blandy <jimb@redhat.com>
* mips.igen (CFC1, CTC1): Pass the correct register numbers to
projects / deliverable / binutils-gdb.git / blobdiff