-start-sanitize-tx19
-Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
+2002-06-02 Chris Demetriou <cgd@broadcom.com>
+ Ed Satterthwaite <ehs@broadcom.com>
+
+ * mips.igen (mdmx): New (pseudo-)model.
+ * mdmx.c, mdmx.igen: New files.
+ * Makefile.in (SIM_OBJS): Add mdmx.o.
+ * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
+ New typedefs.
+ (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
+ (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
+ (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
+ (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
+ (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
+ (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
+ (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
+ (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
+ (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
+ (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
+ (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
+ (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
+ (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
+ (qh_fmtsel): New macros.
+ (_sim_cpu): New member "acc".
+ (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
+ (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
+
+2002-05-01 Chris Demetriou <cgd@broadcom.com>
+
+ * interp.c: Use 'deprecated' rather than 'depreciated.'
+ * sim-main.h: Likewise.
+
+2002-05-01 Chris Demetriou <cgd@broadcom.com>
+
+ * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
+ which wouldn't compile anyway.
+ * sim-main.h (unpredictable_action): New function prototype.
+ (Unpredictable): Define to call igen function unpredictable().
+ (NotWordValue): New macro to call igen function not_word_value().
+ (UndefinedResult): Remove.
+ * interp.c (undefined_result): Remove.
+ (unpredictable_action): New function.
+ * mips.igen (not_word_value, unpredictable): New functions.
+ (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
+ (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
+ (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
+ NotWordValue() to check for unpredictable inputs, then
+ Unpredictable() to handle them.
- * configure.in (tx19, sim_use_gen): Switch to igen.
- * configure: Re-build.
+2002-02-24 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen: Fix formatting of calls to Unpredictable().
+
+2002-04-20 Andrew Cagney <ac131313@redhat.com>
+
+ * interp.c (sim_open): Revert previous change.
+
+2002-04-18 Alexandre Oliva <aoliva@redhat.com>
+
+ * interp.c (sim_open): Disable chunk of code that wrote code in
+ vector table entries.
+
+2002-03-19 Chris Demetriou <cgd@broadcom.com>
+
+ * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
+ (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
+ unused definitions.
+
+2002-03-19 Chris Demetriou <cgd@broadcom.com>
+
+ * cp1.c: Fix many formatting issues.
+
+2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
+
+ * cp1.c (fpu_format_name): New function to replace...
+ (DOFMT): This. Delete, and update all callers.
+ (fpu_rounding_mode_name): New function to replace...
+ (RMMODE): This. Delete, and update all callers.
+
+2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
+
+ * interp.c: Move FPU support routines from here to...
+ * cp1.c: Here. New file.
+ * Makefile.in (SIM_OBJS): Add cp1.o to object list.
+ (cp1.o): New target.
+
+2002-03-12 Chris Demetriou <cgd@broadcom.com>
+
+ * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
+ * mips.igen (mips32, mips64): New models, add to all instructions
+ and functions as appropriate.
+ (loadstore_ea, check_u64): New variant for model mips64.
+ (check_fmt_p): New variant for models mipsV and mips64, remove
+ mipsV model marking fro other variant.
+ (SLL) Rename to...
+ (SLLa) this.
+ (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
+ for mips32 and mips64.
+ (DCLO, DCLZ): New instructions for mips64.
+
+2002-03-07 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
+ immediate or code as a hex value with the "%#lx" format.
+ (ANDI): Likewise, and fix printed instruction name.
+
+2002-03-05 Chris Demetriou <cgd@broadcom.com>
+
+ * sim-main.h (UndefinedResult, Unpredictable): New macros
+ which currently do nothing.
+
+2002-03-05 Chris Demetriou <cgd@broadcom.com>
+
+ * sim-main.h (status_UX, status_SX, status_KX, status_TS)
+ (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
+ (status_CU3): New definitions.
+
+ * sim-main.h (ExceptionCause): Add new values for MIPS32
+ and MIPS64: MDMX, MCheck, CacheErr. Update comments
+ for DebugBreakPoint and NMIReset to note their status in
+ MIPS32 and MIPS64.
+ (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
+ (SignalExceptionCacheErr): New exception macros.
+
+2002-03-05 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
+ * sim-main.h (COP_Usable): Define, but for now coprocessor 1
+ is always enabled.
+ (SignalExceptionCoProcessorUnusable): Take as argument the
+ unusable coprocessor number.
+
+2002-03-05 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen: Fix formatting of all SignalException calls.
+
+2002-03-05 Chris Demetriou <cgd@broadcom.com>
+
+ * sim-main.h (SIGNEXTEND): Remove.
+
+2002-03-04 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen: Remove gencode comment from top of file, fix
+ spelling in another comment.
+
+2002-03-04 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (check_fmt, check_fmt_p): New functions to check
+ whether specific floating point formats are usable.
+ (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
+ (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
+ (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
+ Use the new functions.
+ (do_c_cond_fmt): Remove format checks...
+ (C.cond.fmta, C.cond.fmtb): And move them into all callers.
+
+2002-03-03 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen: Fix formatting of check_fpu calls.
+
+2002-03-03 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (FLOOR.L.fmt): Store correct destination register.
+
+2002-03-03 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen: Remove whitespace at end of lines.
+
+2002-03-02 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (loadstore_ea): New function to do effective
+ address calculations.
+ (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
+ do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
+ CACHE): Use loadstore_ea to do effective address computations.
+
+2002-03-02 Chris Demetriou <cgd@broadcom.com>
+
+ * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
+ * mips.igen (LL, CxC1, MxC1): Likewise.
+
+2002-03-02 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
+ CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
+ FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
+ MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
+ NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
+ SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
+ Don't split opcode fields by hand, use the opcode field values
+ provided by igen.
+
+2002-03-01 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (do_divu): Fix spacing.
+
+ * mips.igen (do_dsllv): Move to be right before DSLLV,
+ to match the rest of the do_<shift> functions.
+
+2002-03-01 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
+ DSRL32, do_dsrlv): Trace inputs and results.
+
+2002-03-01 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (CACHE): Provide instruction-printing string.
+
+ * interp.c (signal_exception): Comment tokens after #endif.
+
+2002-02-28 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
+ (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
+ NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
+ ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
+ CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
+ C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
+ SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
+ LWC1, SWC1): Add "f" to filter, since these are FP instructions.
+
+2002-02-28 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (DSRA32, DSRAV): Fix order of arguments in
+ instruction-printing string.
+ (LWU): Use '64' as the filter flag.
+
+2002-02-28 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (SDXC1): Fix instruction-printing string.
+
+2002-02-28 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
+ filter flags "32,f".
+
+2002-02-27 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (PREFX): This is a 64-bit instruction, use '64'
+ as the filter flag.
+
+2002-02-27 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
+ add a comma) so that it more closely match the MIPS ISA
+ documentation opcode partitioning.
+ (PREF): Put useful names on opcode fields, and include
+ instruction-printing string.
+
+2002-02-27 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (check_u64): New function which in the future will
+ check whether 64-bit instructions are usable and signal an
+ exception if not. Currently a no-op.
+ (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
+ DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
+ DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
+ LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
+
+ * mips.igen (check_fpu): New function which in the future will
+ check whether FPU instructions are usable and signal an exception
+ if not. Currently a no-op.
+ (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
+ CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
+ CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
+ LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
+ MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
+ NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
+ ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
+ SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
+
+2002-02-27 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (do_load_left, do_load_right): Move to be immediately
+ following do_load.
+ (do_store_left, do_store_right): Move to be immediately following
+ do_store.
+
+2002-02-27 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (mipsV): New model name. Also, add it to
+ all instructions and functions where it is appropriate.
+
+2002-02-18 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen: For all functions and instructions, list model
+ names that support that instruction one per line.
+
+2002-02-11 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen: Add some additional comments about supported
+ models, and about which instructions go where.
+ (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
+ order as is used in the rest of the file.
+
+2002-02-11 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
+ indicating that ALU32_END or ALU64_END are there to check
+ for overflow.
+ (DADD): Likewise, but also remove previous comment about
+ overflow checking.
+
+2002-02-10 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
+ DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
+ JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
+ SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
+ ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
+ fields (i.e., add and move commas) so that they more closely
+ match the MIPS ISA documentation opcode partitioning.
+
+2002-02-10 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (ADDI): Print immediate value.
+ (BREAK): Print code.
+ (DADDIU, DSRAV, DSRLV): Print correct instruction name.
+ (SLL): Print "nop" specially, and don't run the code
+ that does the shift for the "nop" case.
+
+2001-11-17 Fred Fish <fnf@redhat.com>
+
+ * sim-main.h (float_operation): Move enum declaration outside
+ of _sim_cpu struct declaration.
+
+2001-04-12 Jim Blandy <jimb@redhat.com>
+
+ * mips.igen (CFC1, CTC1): Pass the correct register numbers to
+ PENDING_FILL. Use PENDING_SCHED directly to handle the pending
+ set of the FCSR.
+ * sim-main.h (COCIDX): Remove definition; this isn't supported by
+ PENDING_FILL, and you can get the intended effect gracefully by
+ calling PENDING_SCHED directly.
+
+2001-02-23 Ben Elliston <bje@redhat.com>
+
+ * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
+ already defined elsewhere.
+
+2001-02-19 Ben Elliston <bje@redhat.com>
+
+ * sim-main.h (sim_monitor): Return an int.
+ * interp.c (sim_monitor): Add return values.
+ (signal_exception): Handle error conditions from sim_monitor.
+
+2001-02-08 Ben Elliston <bje@redhat.com>
+
+ * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
+ (store_memory): Likewise, pass cia to sim_core_write*.
+
+2000-10-19 Frank Ch. Eigler <fche@redhat.com>
+
+ On advice from Chris G. Demetriou <cgd@sibyte.com>:
+ * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
+
+Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
+ * Makefile.in: Don't delete *.igen when cleaning directory.
+
+Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * m16.igen (break): Call SignalException not sim_engine_halt.
+
+Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ From Jason Eckhardt:
+ * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
+
+Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (MxC1, DMxC1): Fix printf formatting.
+
+2000-05-24 Michael Hayes <mhayes@cygnus.com>
+
+ * mips.igen (do_dmultx): Fix typo.
+
+Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
+
+2000-04-12 Frank Ch. Eigler <fche@redhat.com>
+
+ * sim-main.h (GPR_CLEAR): Define macro.
+
+Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (decode_coproc): Output long using %lx and not %s.
+
+2000-03-21 Frank Ch. Eigler <fche@redhat.com>
+
+ * interp.c (sim_open): Sort & extend dummy memory regions for
+ --board=jmr3904 for eCos.
+
+2000-03-02 Frank Ch. Eigler <fche@redhat.com>
+
+ * configure: Regenerated.
+
+Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
+
+ * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
+ calls, conditional on the simulator being in verbose mode.
+
+Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
+
+ * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
+ cache don't get ReservedInstruction traps.
+
+1999-11-29 Mark Salter <msalter@cygnus.com>
+
+ * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
+ to clear status bits in sdisr register. This is how the hardware works.
+
+ * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
+ being used by cygmon.
+
+1999-11-11 Andrew Haley <aph@cygnus.com>
+
+ * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
+ instructions.
+
+Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
+
+ * mips.igen (MULT): Correct previous mis-applied patch.
+
+Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
+
+ * mips.igen (delayslot32): Handle sequence like
+ mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
+ correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
+ (MULT): Actually pass the third register...
+
+1999-09-03 Mark Salter <msalter@cygnus.com>
+
+ * interp.c (sim_open): Added more memory aliases for additional
+ hardware being touched by cygmon on jmr3904 board.
+
+Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
+
+ * interp.c (sim_store_register): Handle case where client - GDB -
+ specifies that a 4 byte register is 8 bytes in size.
+ (sim_fetch_register): Ditto.
+
+1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
+
+ Implement "sim firmware" option, inspired by jimb's version of 1998-01.
+ * interp.c (firmware_option_p): New global flag: "sim firmware" given.
+ (idt_monitor_base): Base address for IDT monitor traps.
+ (pmon_monitor_base): Ditto for PMON.
+ (lsipmon_monitor_base): Ditto for LSI PMON.
+ (MONITOR_BASE, MONITOR_SIZE): Removed macros.
+ (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
+ (sim_firmware_command): New function.
+ (mips_option_handler): Call it for OPTION_FIRMWARE.
+ (sim_open): Allocate memory for idt_monitor region. If "--board"
+ option was given, add no monitor by default. Add BREAK hooks only if
+ monitors are also there.
+
+Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
+
+ * interp.c (sim_monitor): Flush output before reading input.
+
+Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * tconfig.in (SIM_HANDLES_LMA): Always define.
+
+Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ From Mark Salter <msalter@cygnus.com>:
+ * interp.c (BOARD_BSP): Define. Add to list of possible boards.
+ (sim_open): Add setup for BSP board.
+
+Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (MULT, MULTU): Add syntax for two operand version.
+ (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
+ them as unimplemented.
+
+1999-05-08 Felix Lee <flee@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
+
+Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
+
+ * configure.in: Any mips64vr5*-*-* target should have
+ -DTARGET_ENABLE_FR=1.
+ (default_endian): Any mips64vr*el-*-* target should default to
+ LITTLE_ENDIAN.
+ * configure: Re-generate.
+
+1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * mips.igen (ldl): Extend from _16_, not 32.
+
+Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
+
+ * interp.c (sim_store_register): Force registers written to by GDB
+ into an un-interpreted state.
+
+1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
+
+ * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
+ CPU, start periodic background I/O polls.
+ (tx3904sio_poll): New function: periodic I/O poller.
+
+1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
+
+Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
+
+ * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
+ case statement.
+
+1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
+ (load_word): Call SIM_CORE_SIGNAL hook on error.
+ (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
+ starting. For exception dispatching, pass PC instead of NULL_CIA.
+ (decode_coproc): Use COP0_BADVADDR to store faulting address.
+ * sim-main.h (COP0_BADVADDR): Define.
+ (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
+ (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
+ (_sim_cpu): Add exc_* fields to store register value snapshots.
+ * mips.igen (*): Replace memory-related SignalException* calls
+ with references to SIM_CORE_SIGNAL hook.
+
+ * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
+ fix.
+ * sim-main.c (*): Minor warning cleanups.
+
+1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * m16.igen (DADDIU5): Correct type-o.
+
+Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
+
+ * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
+ variables.
+
+Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
+
+ * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
+ to include path.
+ (interp.o): Add dependency on itable.h
+ (oengine.c, gencode): Delete remaining references.
+ (BUILT_SRC_FROM_GEN): Clean up.
+
+1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * vr4run.c: New.
+ * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
+ tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
+ tmp-run-hack) : New.
+ * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
+ DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
+ Drop the "64" qualifier to get the HACK generator working.
+ Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
+ * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
+ qualifier to get the hack generator working.
+ (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
+ (DSLL): Use do_dsll.
+ (DSLLV): Use do_dsllv.
+ (DSRA): Use do_dsra.
+ (DSRL): Use do_dsrl.
+ (DSRLV): Use do_dsrlv.
+ (BC1): Move *vr4100 to get the HACK generator working.
+ (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
+ get the HACK generator working.
+ (MACC) Rename to get the HACK generator working.
+ (DMACC,MACCS,DMACCS): Add the 64.
+
+1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
+ * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
+
+1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
+
+ * mips/interp.c (DEBUG): Cleanups.
+
+1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
+
+ * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
+ (tx3904sio_tickle): fflush after a stdout character output.
+
+1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (sim_close): Uninstall modules.
+
+Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h, interp.c (sim_monitor): Change to global
+ function.
+
+Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (vr4100): Only include vr4100 instructions in
+ simulator.
+ * configure: Re-generate.
+ * m16.igen (*): Tag all mips16 instructions as also being vr4100.
+
+Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
+ * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
+ true alternative.
+
+ * configure.in (sim_default_gen, sim_use_gen): Replace with
+ sim_gen.
+ (--enable-sim-igen): Delete config option. Always using IGEN.
+ * configure: Re-generate.
+
+ * Makefile.in (gencode): Kill, kill, kill.
+ * gencode.c: Ditto.
+
+Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
+ bit mips16 igen simulator.
+ * configure: Re-generate.
+
+ * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
+ as part of vr4100 ISA.
+ * vr.igen: Mark all instructions as 64 bit only.
+
+Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
+ Pacify GCC.
+
+Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
+ mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
+ * configure: Re-generate.
+
+ * m16.igen (BREAK): Define breakpoint instruction.
+ (JALX32): Mark instruction as mips16 and not r3900.
+ * mips.igen (C.cond.fmt): Fix typo in instruction format.
+
+ * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
+
+Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
+ insn as a debug breakpoint.
+
+ * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
+ pending.slot_size.
+ (PENDING_SCHED): Clean up trace statement.
+ (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
+ (PENDING_FILL): Delay write by only one cycle.
+ (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
+
+ * sim-main.c (pending_tick): Clean up trace statements. Add trace
+ of pending writes.
+ (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
+ 32 & 64.
+ (pending_tick): Move incrementing of index to FOR statement.
+ (pending_tick): Only update PENDING_OUT after a write has occured.
+
+ * configure.in: Add explicit mips-lsi-* target. Use gencode to
+ build simulator.
+ * configure: Re-generate.
+
+ * interp.c (sim_engine_run OLD): Delete explicit call to
+ PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
+
+Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
+ interrupt level number to match changed SignalExceptionInterrupt
+ macro.
+
+Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * interp.c: #include "itable.h" if WITH_IGEN.
+ (get_insn_name): New function.
+ (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
+ * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
+
+Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * configure: Rebuilt to inhale new common/aclocal.m4.
+
+Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * dv-tx3904sio.c: Include sim-assert.h.
+
+Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * dv-tx3904sio.c: New file: tx3904 serial I/O module.
+ * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
+ Reorganize target-specific sim-hardware checks.
+ * configure: rebuilt.
+ * interp.c (sim_open): For tx39 target boards, set
+ OPERATING_ENVIRONMENT, add tx3904sio devices.
+ * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
+ ROM executables. Install dv-sockser into sim-modules list.
+
+ * dv-tx3904irc.c: Compiler warning clean-up.
+ * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
+ frequent hw-trace messages.
+
+Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * vr.igen (MulAcc): Identify as a vr4100 specific function.
+
+Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (IGEN_INCLUDE): Add vr.igen.
+
+ * vr.igen: New file.
+ (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
+ * mips.igen: Define vr4100 model. Include vr.igen.
+Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
+
+ * mips.igen (check_mf_hilo): Correct check.
+
+Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (interrupt_event): Add prototype.
+
+ * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
+ register_ptr, register_value.
+ (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
+
+ * sim-main.h (tracefh): Make extern.
+
+Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * dv-tx3904tmr.c: Deschedule timer event after dispatching.
+ Reduce unnecessarily high timer event frequency.
+ * dv-tx3904cpu.c: Ditto for interrupt event.
+
+Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
+ to allay warnings.
+ (interrupt_event): Made non-static.
+
+ * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
+ interchange of configuration values for external vs. internal
+ clock dividers.
+
+Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * mips.igen (BREAK): Moved code to here for
+ simulator-reserved break instructions.
+ * gencode.c (build_instruction): Ditto.
+ * interp.c (signal_exception): Code moved from here. Non-
+ reserved instructions now use exception vector, rather
+ than halting sim.
+ * sim-main.h: Moved magic constants to here.
+
+Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
+ register upon non-zero interrupt event level, clear upon zero
+ event value.
+ * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
+ by passing zero event value.
+ (*_io_{read,write}_buffer): Endianness fixes.
+ * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
+ (deliver_*_tick): Reduce sim event interval to 75% of count interval.
+
+ * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
+ serial I/O and timer module at base address 0xFFFF0000.
+
+Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
+
+ * mips.igen (SWC1) : Correct the handling of ReverseEndian
+ and BigEndianCPU.
+
+Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
+
+ * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
+ parts.
+ * configure: Update.
+
+Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * dv-tx3904tmr.c: New file - implements tx3904 timer.
+ * dv-tx3904{irc,cpu}.c: Mild reformatting.
+ * configure.in: Include tx3904tmr in hw_device list.
+ * configure: Rebuilt.
+ * interp.c (sim_open): Instantiate three timer instances.
+ Fix address typo of tx3904irc instance.
+
+Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * interp.c (signal_exception): SystemCall exception now uses
+ the exception vector.
+
+Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
+ to allay warnings.
+
+Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
+
+Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
+
+ * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
+ sim-main.h. Declare a struct hw_descriptor instead of struct
+ hw_device_descriptor.
+
+Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (do_store_left, do_load_left): Compute nr of left and
+ right bits and then re-align left hand bytes to correct byte
+ lanes. Fix incorrect computation in do_store_left when loading
+ bytes from second word.
+
+Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
+ * interp.c (sim_open): Only create a device tree when HW is
+ enabled.
+
+ * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
+ * interp.c (signal_exception): Ditto.
+
+Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c: Mark BEGEZALL as LIKELY.
+
+Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (ALU32_END): Sign extend 32 bit results.
+ * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
+
+Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
+ modules. Recognize TX39 target with "mips*tx39" pattern.
+ * configure: Rebuilt.
+ * sim-main.h (*): Added many macros defining bits in
+ TX39 control registers.
+ (SignalInterrupt): Send actual PC instead of NULL.
+ (SignalNMIReset): New exception type.
+ * interp.c (board): New variable for future use to identify
+ a particular board being simulated.
+ (mips_option_handler,mips_options): Added "--board" option.
+ (interrupt_event): Send actual PC.
+ (sim_open): Make memory layout conditional on board setting.
+ (signal_exception): Initial implementation of hardware interrupt
+ handling. Accept another break instruction variant for simulator
+ exit.
+ (decode_coproc): Implement RFE instruction for TX39.
+ (mips.igen): Decode RFE instruction as such.
+ * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
+ * interp.c: Define "jmr3904" and "jmr3904debug" board types and
+ bbegin to implement memory map.
+ * dv-tx3904cpu.c: New file.
+ * dv-tx3904irc.c: New file.
+
+Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
+
+ * mips.igen (check_mt_hilo): Create a separate r3900 version.
+
+Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
+
+ * tx.igen (madd,maddu): Replace calls to check_op_hilo
+ with calls to check_div_hilo.
+
+Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
+
+ * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
+ Replace check_op_hilo with check_mult_hilo and check_div_hilo.
+ Add special r3900 version of do_mult_hilo.
+ (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
+ with calls to check_mult_hilo.
+ (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
+ with calls to check_div_hilo.
+
+Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
+ Document a replacement.
+
+Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * interp.c (sim_monitor): Make mon_printf work.
+
+Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * sim-main.h (INSN_NAME): New arg `cpu'.
+
+Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
+
+ * acconfig.h: New file.
+ * configure.in: Reverted change of Apr 24; use sinclude again.
+
+Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
+
+ * configure.in: Don't call sinclude.
+
+Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
+
+ * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
+
+Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (ERET): Implement.
+
+ * interp.c (decode_coproc): Return sign-extended EPC.
+
+ * mips.igen (ANDI, LUI, MFC0): Add tracing code.
+
+ * interp.c (signal_exception): Do not ignore Trap.
+ (signal_exception): On TRAP, restart at exception address.
+ (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
+ (signal_exception): Update.
+ (sim_open): Patch V_COMMON interrupt vector with an abort sequence
+ so that TRAP instructions are caught.
+
+Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (struct hilo_access, struct hilo_history): Define,
+ contains HI/LO access history.
+ (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
+ (HIACCESS, LOACCESS): Delete, replace with
+ (HIHISTORY, LOHISTORY): New macros.
+ (CHECKHILO): Delete all, moved to mips.igen
-end-sanitize-tx19
-start-sanitize-sky
-Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
+ * gencode.c (build_instruction): Do not generate checks for
+ correct HI/LO register usage.
- * interp.c (decode_coproc): Make COP2 branch code compile after
- igen signature changes.
+ * interp.c (old_engine_run): Delete checks for correct HI/LO
+ register usage.
+
+ * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
+ check_mf_cycles): New functions.
+ (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
+ do_divu, domultx, do_mult, do_multu): Use.
+
+ * tx.igen ("madd", "maddu"): Use.
-end-sanitize-sky
Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
* mips.igen (DSRAV): Use function do_dsrav.
* m16run.c (sim_engine_run): Restore CIA after handling an event.
-start-sanitize-tx19
- * mips.igen (mtc0): Valid tx19 instruction.
-
-end-sanitize-tx19
* sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
functions.
* sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
(IMEM16): Drop NR argument from macro.
-start-sanitize-sky
-Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
-
- * interp.c (decode_coproc): Add proper 1000000 bit-string at top
- of VU lower instruction.
-
-end-sanitize-sky
-start-sanitize-sky
-Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
-
- * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
- instead of QUADWORD.
-
- * sim-main.h: Removed attempt at allowing 128-bit access.
-
-end-sanitize-sky
-start-sanitize-sky
-Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
-
- * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
-
- * interp.c (decode_coproc): Refer to VU CIA as a "special"
- register, not as a "misc" register. Aha. Add activity
- assertions after VCALLMS* instructions.
-
-end-sanitize-sky
-start-sanitize-sky
-Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
-
- * interp.c (decode_coproc): Do not apply superfluous E (end) flag
- to upper code of generated VU instruction.
-
-end-sanitize-sky
-start-sanitize-sky
-Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
-
- * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
-
- * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
- for TARGET_SKY.
-
- * r5900.igen (SQC2): Thinko.
-
-end-sanitize-sky
-start-sanitize-sky
-Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
-
- * interp.c (*): Adapt code to merged VU device & state structs.
- (decode_coproc): Execute COP2 each macroinstruction without
- pipelining, by stepping VU to completion state. Adapted to
- read_vu_*_reg style of register access.
-
- * mips.igen ([SL]QC2): Removed these COP2 instructions.
-
- * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
-
- * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
-
-end-sanitize-sky
Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
* Makefile.in (SIM_OBJS): Add sim-main.o.
* mips.igen (r3900): r3900 does not support 64 bit integer
operations.
-start-sanitize-sky
-Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
-
- * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
-
-end-sanitize-sky
-start-sanitize-sky
-Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
-
- * interp.c (decode_coproc): Continuing COP2 work.
- (cop_[ls]q): Make sky-target-only.
-
- * sim-main.h (COP_[LS]Q): Make sky-target-only.
-end-sanitize-sky
Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
* configure.in (mipstx39*-*-*): Use gencode simulator rather
than igen one.
* configure : Rebuild.
-start-sanitize-sky
-Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
-
- * interp.c (decode_coproc): Added a missing TARGET_SKY check
- around COP2 implementation skeleton.
-
-end-sanitize-sky
-start-sanitize-sky
-Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
-
- * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
-
- * interp.c (sim_{load,store}_register): Use new vu[01]_device
- static to access VU registers.
- (decode_coproc): Added skeleton of sky COP2 (VU) instruction
- decoding. Work in progress.
-
- * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
- overlapping/redundant bit pattern.
- (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
- progress.
-
- * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
- status register.
-
- * interp.c (cop_lq, cop_sq): New functions for future 128-bit
- access to coprocessor registers.
-
- * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
-end-sanitize-sky
Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* interp.c (Max, Min): Comment out functions. Not yet used.
-start-sanitize-vr4320
-Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
-
-end-sanitize-vr4320
Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
configurable settings for stand-alone simulator.
-start-sanitize-sky
- * configure.in: Added --with-sim-gpu2 option to specify path of
- sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
- links/compiles stand-alone simulator with this library.
-
- * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
-end-sanitize-sky
* configure.in: Added X11 search, just in case.
* configure: Regenerated.
* interp.c (sim_write, sim_read, load_memory, store_memory):
Replace sim_core_*_map with read_map, write_map, exec_map resp.
-start-sanitize-vr4320
-Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
-
- * vr4320.igen (clz,dclz) : Added.
- (dmac): Replaced 99, with LO.
-
-end-sanitize-vr4320
-start-sanitize-vr5400
-Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
-
-end-sanitize-vr5400
-start-sanitize-vr4320
-Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
-
- * vr4320.igen: New file.
- * Makefile.in (vr4320.igen) : Added.
- * configure.in (mips64vr4320-*-*): Added.
- * configure : Rebuilt.
- * mips.igen : Correct the bfd-names in the mips-ISA model entries.
- Add the vr4320 model entry and mark the vr4320 insn as necessary.
-
-end-sanitize-vr4320
Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
* sim-main.h (GETFCC): Return an unsigned value.
-start-sanitize-r5900
- * r5900.igen: Use an unsigned array index variable `i'.
- (QFSRV): Ditto for variable bytes.
-
-end-sanitize-r5900
Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
* mips.igen (DIV): Fix check for -1 / MIN_INT.
(DADD): Result destination is RD not RT.
-start-sanitize-r5900
- * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
- (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
- divide.
-
-end-sanitize-r5900
Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
* sim-main.h (HIACCESS, LOACCESS): Always define.
* mips.igen (CxC1): Add tracing.
-start-sanitize-r5900
-Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * r5900.igen (StoreFP): Delete.
- (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
- New functions.
- (rsqrt.s, sqrt.s): Implement.
- (r59cond): New function.
- (C.COND.S): Call r59cond in assembler line.
- (cvt.w.s, cvt.s.w): Implement.
-
- * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
- instruction set.
-
- * sim-main.h: Define an enum of r5900 FCSR bit fields.
-
-end-sanitize-r5900
-start-sanitize-r5900
-Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * r5900.igen: Add tracing to all p* instructions.
-
-Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * interp.c (sim_store_register, sim_fetch_register): Pull swifty
- to get gdb talking to re-aranged sim_cpu register structure.
-
-end-sanitize-r5900
Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
* sim-main.h (Max, Min): Declare.
* mips.igen (BC1): Add tracing.
-start-sanitize-vr5400
-Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * mdmx.igen: Tag all functions as requiring either with mdmx or
- vr5400 processor.
-
-end-sanitize-vr5400
-start-sanitize-r5900
-Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
- to 32.
- (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
-
- * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
-
- * r5900.igen: Rewrite.
-
- * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
- struct.
- (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
- Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
-
-end-sanitize-r5900
Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
* interp.c Added memory map for stack in vr4100
* Makefile.in (SIM_NO_ALL): Define.
(tmp-m16): Generate both 16 bit and 32 bit simulator engines.
-start-sanitize-tx19
- * m16.igen: Mark all mips16 insns as being part of the tx19 insn
- set.
-
-end-sanitize-tx19
Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure.in (mips_fpu_bitsize): For tx39, restrict floating
* configure: Regenerated to track ../common/aclocal.m4 changes.
-start-sanitize-vr5400
- * mdmx.igen: Mark all instructions as 64bit/fp specific.
-
-end-sanitize-vr5400
Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (ColdReset): Call PENDING_INVALIDATE.
address_translation): Ditto
(decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
-start-sanitize-vr5400
- * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
- `sd'.
- (ByteAlign): Use StoreFPR, pass args in correct order.
-
-end-sanitize-vr5400
-start-sanitize-r5900
-Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure.in (sim_igen_filter): For r5900, configure as SMP.
-
-end-sanitize-r5900
Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
-start-sanitize-r5900
- * configure.in (sim_igen_filter): For r5900, use igen.
- * configure: Re-generate.
-
-end-sanitize-r5900
* interp.c (sim_engine_run): Add `nr_cpus' argument.
* mips.igen (model): Map processor names onto BFD name.
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
-start-sanitize-vr5400
-Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
- bit values.
-
-end-sanitize-vr5400
-start-sanitize-vr5400
-Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
-
- * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
- vr5400 with the vr5000 as the default.
-
-end-sanitize-vr5400
Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
* mips.igen (MSUB): Fix to work like MADD.
* gencode.c (MSUB): Similarly.
-start-sanitize-vr5400
-Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
- vr5400.
-
-end-sanitize-vr5400
Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* mips.igen (LWC1): Correct assembler - lwc1 not swc1.
-start-sanitize-vr5400
- * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
- (value_cc, store_cc): Implement.
-
- * sim-main.h: Add 8*3*8 bit accumulator.
-
- * vr5400.igen: Move mdmx instructins from here
- * mdmx.igen: To here - new file. Add/fix missing instructions.
- * mips.igen: Include mdmx.igen.
- * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
-
-end-sanitize-vr5400
Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-main.h (sim-fpu.h): Include.
* mips.igen: Delay slot branches add OFFSET to NIA not CIA.
(MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
- (start-sanitize-r5900):
- (LWXC1, SWXC1): Delete from r5900 instruction set.
- (end-sanitize-r5900):
(MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
PENDING_FILL versions of instructions. Simplify.
(X): New function.
* sim-main.h (IPC): Delete.
- start-sanitize-vr5400
- * vr5400.igen (vr): Add missing cia argument to value_fpr.
- (do_select): Rename function select.
- end-sanitize-vr5400
* interp.c (signal_exception, store_word, load_word,
address_translation, load_memory, store_memory, cache_op,
* interp.c (address_translation): Delete parameter HOST.
-start-sanitize-tx49
-Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
-
- * gencode.c: Add tx49 configury and insns.
- * configure.in: Add tx49 configury.
- * configure: Update.
-
-end-sanitize-tx49
Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
* mips.igen:
igen. Replace with configuration variables sim_igen_flags /
sim_m16_flags.
- start-sanitize-r5900
- * r5900.igen: New file. Copy r5900 insns here.
- end-sanitize-r5900
- start-sanitize-vr5400
- * vr5400.igen: New file.
- end-sanitize-vr5400
* m16.igen: New file. Copy mips16 insns here.
* mips.igen: From here.
Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
- start-sanitize-vr5400
- * mips.igen: Tag all mipsIV instructions with vr5400 model.
-
- * configure.in: Add mips64vr5400 target.
- * configure: Re-generate.
-
- end-sanitize-vr5400
* Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
to top.
(tmp-igen, tmp-m16): Pass -I srcdir to igen.
Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
-start-sanitize-r5900
- * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
- ...): Move to sim-main.h
-
-end-sanitize-r5900
* interp.c (sync_operation): Rename from SyncOperation, make
global, add SD argument.
(prefetch): Rename from Prefetch, make global, add SD argument.
* configure: Regenerated to track ../common/aclocal.m4 changes.
-start-sanitize-r5900
-Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * interp.c (MAX_REG): Allow up-to 128 registers.
- (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
- (REGISTER_SA): Ditto.
- (sim_open): Initialize register_widths for r5900 specific
- registers.
- (sim_fetch_register, sim_store_register): Check for request of
- r5900 specific SA register. Check for request for hi 64 bits of
- r5900 specific registers.
-
-end-sanitize-r5900
Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
* configure: Regenerated.
* gencode.c: Add r3900 (tx39).
-start-sanitize-tx19
- * gencode.c: Fix some configuration problems by improving
- the relationship between tx19 and tx39.
-end-sanitize-tx19
Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
constants.
(build_instruction): Ditto for LL.
-start-sanitize-tx19
-Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
-
- * mips/configure.in, mips/gencode: Add tx19/r1900.
-
-end-sanitize-tx19
Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
* configure: Regenerated to track ../common/aclocal.m4 changes.
-start-sanitize-r5900
-Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * gencode.c (build_instruction): For "pabsw" and "pabsh", check
- for overflow due to ABS of MININT, set result to MAXINT.
- (build_instruction): For "psrlvw", signextend bit 31.
-
-end-sanitize-r5900
Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
(sim_load): Move call to sim_config from here.
(sim_open): To here. Check return status.
-start-sanitize-r5900
- * gencode.c (build_instruction): Do not define x8000000000000000,
- x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
-
-end-sanitize-r5900
-start-sanitize-r5900
-Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * gencode.c (build_instruction): For "pdivw", "pdivbw" and
- "pdivuw" check for overflow due to signed divide by -1.
-
-end-sanitize-r5900
Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
* gencode.c (build_instruction): Two arg MADD should
not assign result to $0.
-start-sanitize-r5900
-Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
-
- * gencode.c (build_instruction): For "ppac5" use unsigned
- arrithmetic so that the sign bit doesn't smear when right shifted.
- (build_instruction): For "pdiv" perform sign extension when
- storing results in HI and LO.
- (build_instructions): For "pdiv" and "pdivbw" check for
- divide-by-zero.
- (build_instruction): For "pmfhl.slw" update hi part of dest
- register as well as low part.
- (build_instruction): For "pmfhl" portably handle long long values.
- (build_instruction): For "pmfhl.sh" correctly negative values.
- Store half words 2 and three in the correct place.
- (build_instruction): For "psllvw", sign extend value after shift.
-
-end-sanitize-r5900
Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
* sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
* interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
signed8, unsigned8 et.al. types.
-start-sanitize-r5900
- * gencode.c (build_instruction): For PMULTU* do not sign extend
- registers. Make generated code easier to debug.
-
-end-sanitize-r5900
* interp.c (SUB_REG_FETCH): Handle both little and big endian
hosts when selecting subreg.
-start-sanitize-r5900
-Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
-
- * gencode.c (type_for_data_len): For 32bit operations concerned
- with overflow, perform op using 64bits.
- (build_instruction): For PADD, always compute operation using type
- returned by type_for_data_len.
- (build_instruction): For PSUBU, when overflow, saturate to zero as
- actually underflow.
-
-end-sanitize-r5900
Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
-start-sanitize-r5900
- * gencode.c (build_instruction): Handle "pext5" according to
- version 1.95 of the r5900 ISA.
-
- * gencode.c (build_instruction): Handle "ppac5" according to
- version 1.95 of the r5900 ISA.
-
-end-sanitize-r5900
* interp.c (sim_engine_run): Reset the ZERO register to zero
regardless of FEATURE_WARN_ZERO.
* gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
* interp.c: Implement the ERET and mt/f sr instructions.
-start-sanitize-r5900
-Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * gencode.c (build_instruction): For paddu, extract unsigned
- sub-fields.
-
- * gencode.c (build_instruction): Saturate padds instead of padd
- instructions.
-
-end-sanitize-r5900
Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (SignalException): Don't bother restarting an
in argv form.
(other sim_*): New SIM_DESC argument.
-start-sanitize-r5900
-Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
-
- * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
- Change values to avoid overloading DOUBLEWORD which is tested
- for all insns.
- * gencode.c: reinstate "offending code".
-
-end-sanitize-r5900
Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
* interp.c: Fix printing of addresses for non-64-bit targets.
(pr_addr): Add function to print address based on size.
-start-sanitize-r5900
- * gencode.c: #ifdef out offending code until a permanent fix
- can be added. Code is causing build errors for non-5900 mips targets.
-end-sanitize-r5900
-start-sanitize-r5900
-Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
-
- * gencode.c (process_instructions): Correct test for ISA dependent
- architecture bits in isa field of MIPS_DECODE.
-
-end-sanitize-r5900
Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
* interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
-start-sanitize-r5900
-Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
-
- * gencode.c (MIPS_DECODE): Correct instruction feature flags for
- PMADDUW.
-
-end-sanitize-r5900
Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
* gencode.c (build_mips16_operands): Correct computation of base
address for extended PC relative instruction.
-start-sanitize-r5900
-Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
-
- * Makefile.in, configure, configure.in, gencode.c,
- interp.c, support.h: add r5900.
-
-end-sanitize-r5900
Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
* interp.c (mips16_entry): Add support for floating point cases.
projects / deliverable / binutils-gdb.git / blobdiff