+start-sanitize-sky
+Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
+ instead of QUADWORD.
+
+ * sim-main.h: Removed attempt at allowing 128-bit access.
+
+end-sanitize-sky
+start-sanitize-sky
+ Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
+
+ * interp.c (decode_coproc): Refer to VU CIA as a "special"
+ register, not as a "misc" register. Aha. Add activity
+ assertions after VCALLMS* instructions.
+
+end-sanitize-sky
+start-sanitize-sky
+ Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Do not apply superfluous E (end) flag
+ to upper code of generated VU instruction.
+
+end-sanitize-sky
+start-sanitize-sky
+Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
+
+ * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
+ for TARGET_SKY.
+
+ * r5900.igen (SQC2): Thinko.
+
+end-sanitize-sky
+start-sanitize-sky
+Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (*): Adapt code to merged VU device & state structs.
+ (decode_coproc): Execute COP2 each macroinstruction without
+ pipelining, by stepping VU to completion state. Adapted to
+ read_vu_*_reg style of register access.
+
+ * mips.igen ([SL]QC2): Removed these COP2 instructions.
+
+ * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
+
+ * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
+
+end-sanitize-sky
+Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add sim-main.o.
+
+ * sim-main.h (address_translation, load_memory, store_memory,
+ cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
+ as INLINE_SIM_MAIN.
+ (pr_addr, pr_uword64): Declare.
+ (sim-main.c): Include when H_REVEALS_MODULE_P.
+
+ * interp.c (address_translation, load_memory, store_memory,
+ cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
+ from here.
+ * sim-main.c: To here. Fix compilation problems.
+
+ * configure.in: Enable inlining.
+ * configure: Re-config.
+
+Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen: Include tx.igen.
+ * Makefile.in (IGEN_INCLUDE): Add tx.igen.
+ * tx.igen: New file, contains MADD and MADDU.
+
+ * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
+ the hardwired constant `7'.
+ (store_memory): Ditto.
+ (LOADDRMASK): Move definition to sim-main.h.
+
+ mips.igen (MTC0): Enable for r3900.
+ (ADDU): Add trace.
+
+ mips.igen (do_load_byte): Delete.
+ (do_load, do_store, do_load_left, do_load_write, do_store_left,
+ do_store_right): New functions.
+ (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
+
+ configure.in: Let the tx39 use igen again.
+ configure: Update.
+
+Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
+ not an address sized quantity. Return zero for cache sizes.
+
+Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (r3900): r3900 does not support 64 bit integer
+ operations.
+
+start-sanitize-sky
+Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
+
+end-sanitize-sky
+start-sanitize-sky
+Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Continuing COP2 work.
+ (cop_[ls]q): Make sky-target-only.
+
+ * sim-main.h (COP_[LS]Q): Make sky-target-only.
+end-sanitize-sky
+Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
+
+ * configure.in (mipstx39*-*-*): Use gencode simulator rather
+ than igen one.
+ * configure : Rebuild.
+
+start-sanitize-sky
+Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Added a missing TARGET_SKY check
+ around COP2 implementation skeleton.
+
+end-sanitize-sky
+start-sanitize-sky
+Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
+
+ * interp.c (sim_{load,store}_register): Use new vu[01]_device
+ static to access VU registers.
+ (decode_coproc): Added skeleton of sky COP2 (VU) instruction
+ decoding. Work in progress.
+
+ * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
+ overlapping/redundant bit pattern.
+ (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
+ progress.
+
+ * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
+ status register.
+
+ * interp.c (cop_lq, cop_sq): New functions for future 128-bit
+ access to coprocessor registers.
+
+ * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
+end-sanitize-sky
+Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
+
+Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (Max, Min): Comment out functions. Not yet used.
+
+start-sanitize-vr4320
+Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
+
+end-sanitize-vr4320
+Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
+ configurable settings for stand-alone simulator.
+
+start-sanitize-sky
+ * configure.in: Added --with-sim-gpu2 option to specify path of
+ sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
+ links/compiles stand-alone simulator with this library.
+
+ * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
+end-sanitize-sky
+ * configure.in: Added X11 search, just in case.
+
+ * configure: Regenerated.
+
+Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_write, sim_read, load_memory, store_memory):
+ Replace sim_core_*_map with read_map, write_map, exec_map resp.
+
+start-sanitize-vr4320
+Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
+
+ * vr4320.igen (clz,dclz) : Added.
+ (dmac): Replaced 99, with LO.
+
+end-sanitize-vr4320
+start-sanitize-vr5400
+Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
+
+end-sanitize-vr5400
+start-sanitize-vr4320
+Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
+
+ * vr4320.igen: New file.
+ * Makefile.in (vr4320.igen) : Added.
+ * configure.in (mips64vr4320-*-*): Added.
+ * configure : Rebuilt.
+ * mips.igen : Correct the bfd-names in the mips-ISA model entries.
+ Add the vr4320 model entry and mark the vr4320 insn as necessary.
+
+end-sanitize-vr4320
+Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (GETFCC): Return an unsigned value.
+
+start-sanitize-r5900
+ * r5900.igen: Use an unsigned array index variable `i'.
+ (QFSRV): Ditto for variable bytes.
+
+end-sanitize-r5900
+Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (DIV): Fix check for -1 / MIN_INT.
+ (DADD): Result destination is RD not RT.
+
+start-sanitize-r5900
+ * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
+ (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
+ divide.
+
+end-sanitize-r5900
+Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (HIACCESS, LOACCESS): Always define.
+
+ * mdmx.igen (Maxi, Mini): Rename Max, Min.
+
+ * interp.c (sim_info): Delete.
+
+Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * interp.c (DECLARE_OPTION_HANDLER): Use it.
+ (mips_option_handler): New argument `cpu'.
+ (sim_open): Update call to sim_add_option_table.
+
+Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (CxC1): Add tracing.
+
+start-sanitize-r5900
+Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * r5900.igen (StoreFP): Delete.
+ (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
+ New functions.
+ (rsqrt.s, sqrt.s): Implement.
+ (r59cond): New function.
+ (C.COND.S): Call r59cond in assembler line.
+ (cvt.w.s, cvt.s.w): Implement.
+
+ * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
+ instruction set.
+
+ * sim-main.h: Define an enum of r5900 FCSR bit fields.
+
+end-sanitize-r5900
+start-sanitize-r5900
+Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * r5900.igen: Add tracing to all p* instructions.
+
+Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_store_register, sim_fetch_register): Pull swifty
+ to get gdb talking to re-aranged sim_cpu register structure.
+
+end-sanitize-r5900
+Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (Max, Min): Declare.
+
+ * interp.c (Max, Min): New functions.
+
+ * mips.igen (BC1): Add tracing.
+
+start-sanitize-vr5400
+Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mdmx.igen: Tag all functions as requiring either with mdmx or
+ vr5400 processor.
+
+end-sanitize-vr5400
+start-sanitize-r5900
+Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
+ to 32.
+ (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
+
+ * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
+
+ * r5900.igen: Rewrite.
+
+ * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
+ struct.
+ (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
+ Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
+
+end-sanitize-r5900
+Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
+
+ * interp.c Added memory map for stack in vr4100
+
+Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
+
+ * interp.c (load_memory): Add missing "break"'s.
+
+Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_store_register, sim_fetch_register): Pass in
+ length parameter. Return -1.
+
+Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * interp.c: Added hardware init hook, fixed warnings.
+
+Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
+
+Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (ifetch16): New function.
+
+ * sim-main.h (IMEM32): Rename IMEM.
+ (IMEM16_IMMED): Define.
+ (IMEM16): Define.
+ (DELAY_SLOT): Update.
+
+ * m16run.c (sim_engine_run): New file.
+
+ * m16.igen: All instructions except LB.
+ (LB): Call do_load_byte.
+ * mips.igen (do_load_byte): New function.
+ (LB): Call do_load_byte.
+
+ * mips.igen: Move spec for insn bit size and high bit from here.
+ * Makefile.in (tmp-igen, tmp-m16): To here.
+
+ * m16.dc: New file, decode mips16 instructions.
+
+ * Makefile.in (SIM_NO_ALL): Define.
+ (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
+
+start-sanitize-tx19
+ * m16.igen: Mark all mips16 insns as being part of the tx19 insn
+ set.
+
+end-sanitize-tx19
+Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (mips_fpu_bitsize): For tx39, restrict floating
+ point unit to 32 bit registers.
+ * configure: Re-generate.
+
+Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (sim_use_gen): Make IGEN the default simulator
+ generator for generic 32 and 64 bit mips targets.
+ * configure: Re-generate.
+
+Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (SizeFGR): Determine from floating-point and not gpr
+ bitsize.
+
+ * interp.c (sim_fetch_register, sim_store_register): Read/write
+ FGR from correct location.
+ (sim_open): Set size of FGR's according to
+ WITH_TARGET_FLOATING_POINT_BITSIZE.
+
+ * sim-main.h (FGR): Store floating point registers in a separate
+ array.
+
+Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+start-sanitize-vr5400
+ * mdmx.igen: Mark all instructions as 64bit/fp specific.
+
+end-sanitize-vr5400
+Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (ColdReset): Call PENDING_INVALIDATE.
+
+ * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
+
+ * interp.c (pending_tick): New function. Deliver pending writes.
+
+ * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
+ PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
+ it can handle mixed sized quantites and single bits.
+
+Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (oengine.h): Do not include when building with IGEN.
+ (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
+ (sim_info): Ditto for PROCESSOR_64BIT.
+ (sim_monitor): Replace ut_reg with unsigned_word.
+ (*): Ditto for t_reg.
+ (LOADDRMASK): Define.
+ (sim_open): Remove defunct check that host FP is IEEE compliant,
+ using software to emulate floating point.
+ (value_fpr, ...): Always compile, was conditional on HASFPU.
+
+Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
+ size.
+
+ * interp.c (SD, CPU): Define.
+ (mips_option_handler): Set flags in each CPU.
+ (interrupt_event): Assume CPU 0 is the one being iterrupted.
+ (sim_close): Do not clear STATE, deleted anyway.
+ (sim_write, sim_read): Assume CPU zero's vm should be used for
+ data transfers.
+ (sim_create_inferior): Set the PC for all processors.
+ (sim_monitor, store_word, load_word, mips16_entry): Add cpu
+ argument.
+ (mips16_entry): Pass correct nr of args to store_word, load_word.
+ (ColdReset): Cold reset all cpu's.
+ (signal_exception): Pass cpu to sim_monitor & mips16_entry.
+ (sim_monitor, load_memory, store_memory, signal_exception): Use
+ `CPU' instead of STATE_CPU.
+
+
+ * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
+ SD or CPU_.
+
+ * sim-main.h (signal_exception): Add sim_cpu arg.
+ (SignalException*): Pass both SD and CPU to signal_exception.
+ * interp.c (signal_exception): Update.
+
+ * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
+ Ditto
+ (sync_operation, prefetch, cache_op, store_memory, load_memory,
+ address_translation): Ditto
+ (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
+
+start-sanitize-vr5400
+ * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
+ `sd'.
+ (ByteAlign): Use StoreFPR, pass args in correct order.
+
+end-sanitize-vr5400
+start-sanitize-r5900
+Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (sim_igen_filter): For r5900, configure as SMP.
+
+end-sanitize-r5900
+Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+start-sanitize-r5900
+ * configure.in (sim_igen_filter): For r5900, use igen.
+ * configure: Re-generate.
+
+end-sanitize-r5900
+ * interp.c (sim_engine_run): Add `nr_cpus' argument.
+
+ * mips.igen (model): Map processor names onto BFD name.
+
+ * sim-main.h (CPU_CIA): Delete.
+ (SET_CIA, GET_CIA): Define
+
+Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (GPR_SET): Define, used by igen when zeroing a
+ regiser.
+
+ * configure.in (default_endian): Configure a big-endian simulator
+ by default.
+ * configure: Re-generate.
+
+Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
+
+ * interp.c (sim_monitor): Handle Densan monitor outbyte
+ and inbyte functions.
+
+1997-12-29 Felix Lee <flee@cygnus.com>
+
+ * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
+
+Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
+
+ * Makefile.in (tmp-igen): Arrange for $zero to always be
+ reset to zero after every instruction.
+
+Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+start-sanitize-vr5400
+Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
+ bit values.
+
+end-sanitize-vr5400
+start-sanitize-vr5400
+Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
+
+ * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
+ vr5400 with the vr5000 as the default.
+
+end-sanitize-vr5400
+Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mips.igen (MSUB): Fix to work like MADD.
+ * gencode.c (MSUB): Similarly.
+
+start-sanitize-vr5400
+Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
+ vr5400.
+
+end-sanitize-vr5400
+Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
+
+start-sanitize-vr5400
+ * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
+ (value_cc, store_cc): Implement.
+
+ * sim-main.h: Add 8*3*8 bit accumulator.
+
+ * vr5400.igen: Move mdmx instructins from here
+ * mdmx.igen: To here - new file. Add/fix missing instructions.
+ * mips.igen: Include mdmx.igen.
+ * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
+
+end-sanitize-vr5400
+Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (sim-fpu.h): Include.
+
+ * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
+ Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
+ using host independant sim_fpu module.
+
+Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (signal_exception): Report internal errors with SIGABRT
+ not SIGQUIT.
+
+ * sim-main.h (C0_CONFIG): New register.
+ (signal.h): No longer include.
+
+ * interp.c (decode_coproc): Allow access C0_CONFIG to register.
+
+Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
+
+Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen: Tag vr5000 instructions.
+ (ANDI): Was missing mipsIV model, fix assembler syntax.
+ (do_c_cond_fmt): New function.
+ (C.cond.fmt): Handle mips I-III which do not support CC field
+ separatly.
+ (bc1): Handle mips IV which do not have a delaed FCC separatly.
+ (SDR): Mask paddr when BigEndianMem, not the converse as specified
+ in IV3.2 spec.
+ (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
+ vr5000 which saves LO in a GPR separatly.
+
+ * configure.in (enable-sim-igen): For vr5000, select vr5000
+ specific instructions.
+ * configure: Re-generate.
+
+Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add sim-fpu module.
+
+ * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
+ fmt_uninterpreted_64 bit cases to switch. Convert to
+ fmt_formatted,
+
+ * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
+
+ * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
+ as specified in IV3.2 spec.
+ (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
+
+Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
+ (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
+ (start-sanitize-r5900):
+ (LWXC1, SWXC1): Delete from r5900 instruction set.
+ (end-sanitize-r5900):
+ (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
+ PENDING_FILL versions of instructions. Simplify.
+ (X): New function.
+ (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
+ instructions.
+ (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
+ a signed value.
+ (MTHI, MFHI): Disable code checking HI-LO.
+
+ * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
+ global.
+ (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
+
+Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_mips16_operands): Replace IPC with cia.
+
+ * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
+ value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
+ IPC to `cia'.
+ (UndefinedResult): Replace function with macro/function
+ combination.
+ (sim_engine_run): Don't save PC in IPC.
+
+ * sim-main.h (IPC): Delete.
+
+ start-sanitize-vr5400
+ * vr5400.igen (vr): Add missing cia argument to value_fpr.
+ (do_select): Rename function select.
+ end-sanitize-vr5400
+
+ * interp.c (signal_exception, store_word, load_word,
+ address_translation, load_memory, store_memory, cache_op,
+ prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
+ cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
+ current instruction address - cia - argument.
+ (sim_read, sim_write): Call address_translation directly.
+ (sim_engine_run): Rename variable vaddr to cia.
+ (signal_exception): Pass cia to sim_monitor
+
+ * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
+ Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
+ COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
+
+ * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
+ * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
+ SIM_ASSERT.
+
+ * interp.c (signal_exception): Pass restart address to
+ sim_engine_restart.
+
+ * Makefile.in (semantics.o, engine.o, support.o, itable.o,
+ idecode.o): Add dependency.
+
+ * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
+ Delete definitions
+ (DELAY_SLOT): Update NIA not PC with branch address.
+ (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
+
+ * mips.igen: Use CIA not PC in branch calculations.
+ (illegal): Call SignalException.
+ (BEQ, ADDIU): Fix assembler.
+
+Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * m16.igen (JALX): Was missing.
+
+ * configure.in (enable-sim-igen): New configuration option.
+ * configure: Re-generate.
+
+ * sim-main.h (MAX_INSNS, INSN_NAME): Define.
+
+ * interp.c (load_memory, store_memory): Delete parameter RAW.
+ (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
+ bypassing {load,store}_memory.
+
+ * sim-main.h (ByteSwapMem): Delete definition.
+
+ * Makefile.in (SIM_OBJS): Add sim-memopt module.
+
+ * interp.c (sim_do_command, sim_commands): Delete mips specific
+ commands. Handled by module sim-options.
+
+ * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
+ (WITH_MODULO_MEMORY): Define.
+
+ * interp.c (sim_info): Delete code printing memory size.
+
+ * interp.c (mips_size): Nee sim_size, delete function.
+ (power2): Delete.
+ (monitor, monitor_base, monitor_size): Delete global variables.
+ (sim_open, sim_close): Delete code creating monitor and other
+ memory regions. Use sim-memopts module, via sim_do_commandf, to
+ manage memory regions.
+ (load_memory, store_memory): Use sim-core for memory model.
+
+ * interp.c (address_translation): Delete all memory map code
+ except line forcing 32 bit addresses.
+
+Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (WITH_TRACE): Delete definition. Enables common
+ trace options.
+
+ * interp.c (logfh, logfile): Delete globals.
+ (sim_open, sim_close): Delete code opening & closing log file.
+ (mips_option_handler): Delete -l and -n options.
+ (OPTION mips_options): Ditto.
+
+ * interp.c (OPTION mips_options): Rename option trace to dinero.
+ (mips_option_handler): Update.
+
+Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (fetch_str): New function.
+ (sim_monitor): Rewrite using sim_read & sim_write.
+ (sim_open): Check magic number.
+ (sim_open): Write monitor vectors into memory using sim_write.
+ (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
+ (sim_read, sim_write): Simplify - transfer data one byte at a
+ time.
+ (load_memory, store_memory): Clarify meaning of parameter RAW.
+
+ * sim-main.h (isHOST): Defete definition.
+ (isTARGET): Mark as depreciated.
+ (address_translation): Delete parameter HOST.
+
+ * interp.c (address_translation): Delete parameter HOST.
+
+start-sanitize-tx49
+Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c: Add tx49 configury and insns.
+ * configure.in: Add tx49 configury.
+ * configure: Update.
+
+end-sanitize-tx49
+Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen:
+
+ * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
+ (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
+
+Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen: Add model filter field to records.
+
+Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
+
+ interp.c (sim_engine_run): Do not compile function sim_engine_run
+ when WITH_IGEN == 1.
+
+ * configure.in (sim_igen_flags, sim_m16_flags): Set according to
+ target architecture.
+
+ Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
+ igen. Replace with configuration variables sim_igen_flags /
+ sim_m16_flags.
+
+ start-sanitize-r5900
+ * r5900.igen: New file. Copy r5900 insns here.
+ end-sanitize-r5900
+ start-sanitize-vr5400
+ * vr5400.igen: New file.
+ end-sanitize-vr5400
+ * m16.igen: New file. Copy mips16 insns here.
+ * mips.igen: From here.
+
+Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ start-sanitize-vr5400
+ * mips.igen: Tag all mipsIV instructions with vr5400 model.
+
+ * configure.in: Add mips64vr5400 target.
+ * configure: Re-generate.
+
+ end-sanitize-vr5400
+ * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
+ to top.
+ (tmp-igen, tmp-m16): Pass -I srcdir to igen.
+
+Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (build_instruction): Follow sim_write's lead in using
+ BigEndianMem instead of !ByteSwapMem.
+
+Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (sim_gen): Dependent on target, select type of
+ generator. Always select old style generator.
+
+ configure: Re-generate.
+
+ Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
+ targets.
+ (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
+ SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
+ IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
+ (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
+ SIM_@sim_gen@_*, set by autoconf.
+
+Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
+
+ * interp.c (ColdReset): Remove #ifdef HASFPU, check
+ CURRENT_FLOATING_POINT instead.
+
+ * interp.c (ifetch32): New function. Fetch 32 bit instruction.
+ (address_translation): Raise exception InstructionFetch when
+ translation fails and isINSTRUCTION.
+
+ * interp.c (sim_open, sim_write, sim_monitor, store_word,
+ sim_engine_run): Change type of of vaddr and paddr to
+ address_word.
+ (address_translation, prefetch, load_memory, store_memory,
+ cache_op): Change type of vAddr and pAddr to address_word.
+
+ * gencode.c (build_instruction): Change type of vaddr and paddr to
+ address_word.
+
+Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
+ macro to obtain result of ALU op.
+
+Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_info): Call profile_print.
+
+Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add sim-profile.o module.
+
+ * sim-main.h (WITH_PROFILE): Do not define, defined in
+ common/sim-config.h. Use sim-profile module.
+ (simPROFILE): Delete defintion.
+
+ * interp.c (PROFILE): Delete definition.
+ (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
+ (sim_close): Delete code writing profile histogram.
+ (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
+ Delete.
+ (sim_engine_run): Delete code profiling the PC.
+
+Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
+
+ * interp.c (sim_monitor): Make register pointers of type
+ unsigned_word*.
+
+ * sim-main.h: Make registers of type unsigned_word not
+ signed_word.
+
+Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+start-sanitize-r5900
+ * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
+ ...): Move to sim-main.h
+
+end-sanitize-r5900
+ * interp.c (sync_operation): Rename from SyncOperation, make
+ global, add SD argument.
+ (prefetch): Rename from Prefetch, make global, add SD argument.
+ (decode_coproc): Make global.
+
+ * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
+
+ * gencode.c (build_instruction): Generate DecodeCoproc not
+ decode_coproc calls.
+
+ * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
+ (SizeFGR): Move to sim-main.h
+ (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
+ simSIGINT, simJALDELAYSLOT): Move to sim-main.h
+ (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
+ sim-main.h.
+ (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
+ FP_RM_TOMINF, GETRM): Move to sim-main.h.
+ (Uncached, CachedNoncoherent, CachedCoherent, Cached,
+ isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
+ (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
+ BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
+
+ * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
+ exception.
+ (sim-alu.h): Include.
+ (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
+ (sim_cia): Typedef to instruction_address.
+
+Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (interp.o): Rename generated file engine.c to
+ oengine.c.
+
+ * interp.c: Update.
+
+Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
+
+Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): For "FPSQRT", output correct
+ number of arguments to Recip.
+
+Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (interp.o): Depends on sim-main.h
+
+ * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
+
+ * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
+ ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
+ (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
+ STATE, DSSTATE): Define
+ (GPR, FGRIDX, ..): Define.
+
+ * interp.c (registers, register_widths, fpr_state, ipc, dspc,
+ pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
+ (GPR, FGRIDX, ...): Delete macros.
+
+ * interp.c: Update names to match defines from sim-main.h
+
Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_monitor): Add SD argument.
projects / deliverable / binutils-gdb.git / blobdiff