+Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * interp.c (store_word, load_word): New static functions.
+ (mips16_entry): New static function.
+ (SignalException): Look for mips16 entry and exit instructions.
+ (simulate): Use the correct index when setting fpr_state after
+ doing a pending move.
+
+Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
+
+ * interp.c: Fix byte-swapping code throughout to work on
+ both little- and big-endian hosts.
+
+Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
+
+ * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
+ with gdb/config/i386/xm-windows.h.
+
+Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
+
+ * gencode.c (build_instruction): Work around MSVC++ code gen bug
+ that messes up arithmetic shifts.
+
+Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
+
+ * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
+ SIGTRAP and SIGQUIT for _WIN32.
+
+Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
+ force a 64 bit multiplication.
+ (build_instruction) [OR]: In mips16 mode, don't do anything if the
+ destination register is 0, since that is the default mips16 nop
+ instruction.
+
+Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
+ (build_endian_shift): Don't check proc64.
+ (build_instruction): Always set memval to uword64. Cast op2 to
+ uword64 when shifting it left in memory instructions. Always use
+ the same code for stores--don't special case proc64.
+
+ * gencode.c (build_mips16_operands): Fix base PC value for PC
+ relative operands.
+ (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
+ jal instruction.
+ * interp.c (simJALDELAYSLOT): Define.
+ (JALDELAYSLOT): Define.
+ (INDELAYSLOT, INJALDELAYSLOT): Define.
+ (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
+
+Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
+
+ * interp.c (sim_open): add flush_cache as a PMON routine
+ (sim_monitor): handle flush_cache by ignoring it
+
+Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
+
+ * gencode.c (build_instruction): Use !ByteSwapMem instead of
+ BigEndianMem.
+ * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
+ (BigEndianMem): Rename to ByteSwapMem and change sense.
+ (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
+ BigEndianMem references to !ByteSwapMem.
+ (set_endianness): New function, with prototype.
+ (sim_open): Call set_endianness.
+ (sim_info): Use simBE instead of BigEndianMem.
+ (xfer_direct_word, xfer_direct_long, swap_direct_word,
+ swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
+ xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
+ ifdefs, keeping the prototype declaration.
+ (swap_word): Rewrite correctly.
+ (ColdReset): Delete references to CONFIG. Delete endianness related
+ code; moved to set_endianness.
+
+Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
+
+ * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
+ * interp.c (CHECKHILO): Define away.
+ (simSIGINT): New macro.
+ (membank_size): Increase from 1MB to 2MB.
+ (control_c): New function.
+ (sim_resume): Rename parameter signal to signal_number. Add local
+ variable prev. Call signal before and after simulate.
+ (sim_stop_reason): Add simSIGINT support.
+ (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
+ functions always.
+ (sim_warning): Delete call to SignalException. Do call printf_filtered
+ if logfh is NULL.
+ (AddressTranslation): Add #ifdef DEBUG around debugging message and
+ a call to sim_warning.
+
+Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
+ 16 bit instructions.
+
Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
Add support for mips16 (16 bit MIPS implementation):
projects / deliverable / binutils-gdb.git / blobdiff