+start-sanitize-r5900
+Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
+
+ * gencode.c (build_instruction): For "ppac5" use unsigned
+ arrithmetic so that the sign bit doesn't smear when right shifted.
+ (build_instruction): For "pdiv" perform sign extension when
+ storing results in HI and LO.
+ (build_instructions): For "pdiv" and "pdivbw" check for
+ divide-by-zero.
+ (build_instruction): For "pmfhl.slw" update hi part of dest
+ register as well as low part.
+ (build_instruction): For "pmfhl" portably handle long long values.
+ (build_instruction): For "pmfhl.sh" correctly negative values.
+ Store half words 2 and three in the correct place.
+ (build_instruction): For "psllvw", sign extend value after shift.
+
+end-sanitize-r5900
+Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
+
+ * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
+ * sim/mips/configure.in: Regenerate.
+
+Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
+
+ * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
+ signed8, unsigned8 et.al. types.
+
+start-sanitize-r5900
+ * gencode.c (build_instruction): For PMULTU* do not sign extend
+ registers. Make generated code easier to debug.
+
+end-sanitize-r5900
+ * interp.c (SUB_REG_FETCH): Handle both little and big endian
+ hosts when selecting subreg.
+
+start-sanitize-r5900
+Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
+
+ * gencode.c (type_for_data_len): For 32bit operations concerned
+ with overflow, perform op using 64bits.
+ (build_instruction): For PADD, always compute operation using type
+ returned by type_for_data_len.
+ (build_instruction): For PSUBU, when overflow, saturate to zero as
+ actually underflow.
+
+end-sanitize-r5900
+Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
+
+start-sanitize-r5900
+ * gencode.c (build_instruction): Handle "pext5" according to
+ version 1.95 of the r5900 ISA.
+
+ * gencode.c (build_instruction): Handle "ppac5" according to
+ version 1.95 of the r5900 ISA.
+
+end-sanitize-r5900
+ * interp.c (sim_engine_run): Reset the ZERO register to zero
+ regardless of FEATURE_WARN_ZERO.
+ * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
+
+Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
+ (SignalException): For BreakPoints ignore any mode bits and just
+ save the PC.
+ (SignalException): Always set the CAUSE register.
+
+Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (SignalException): Clear the simDELAYSLOT flag when an
+ exception has been taken.
+
+ * interp.c: Implement the ERET and mt/f sr instructions.
+
+start-sanitize-r5900
+Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): For paddu, extract unsigned
+ sub-fields.
+
+ * gencode.c (build_instruction): Saturate padds instead of padd
+ instructions.
+
+end-sanitize-r5900
+Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (SignalException): Don't bother restarting an
+ interrupt.
+
+Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (SignalException): Really take an interrupt.
+ (interrupt_event): Only deliver interrupts when enabled.
+
+Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_info): Only print info when verbose.
+ (sim_info) Use sim_io_printf for output.
+
+Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
+ mips architectures.
+
+Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_do_command): Check for common commands if a
+ simulator specific command fails.
+
+Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
+
+ * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
+ and simBE when DEBUG is defined.
+
+Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (interrupt_event): New function. Pass exception event
+ onto exception handler.
+
+ * configure.in: Check for stdlib.h.
+ * configure: Regenerate.
+
+ * gencode.c (build_instruction): Add UNUSED attribute to tempS
+ variable declaration.
+ (build_instruction): Initialize memval1.
+ (build_instruction): Add UNUSED attribute to byte, bigend,
+ reverse.
+ (build_operands): Ditto.
+
+ * interp.c: Fix GCC warnings.
+ (sim_get_quit_code): Delete.
+
+ * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
+ * Makefile.in: Ditto.
+ * configure: Re-generate.
+
+ * Makefile.in (SIM_OBJS): Add sim-watch.o module.
+
+Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (mips_option_handler): New function parse argumes using
+ sim-options.
+ (myname): Replace with STATE_MY_NAME.
+ (sim_open): Delete check for host endianness - performed by
+ sim_config.
+ (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
+ (sim_open): Move much of the initialization from here.
+ (sim_load): To here. After the image has been loaded and
+ endianness set.
+ (sim_open): Move ColdReset from here.
+ (sim_create_inferior): To here.
+ (sim_open): Make FP check less dependant on host endianness.
+
+ * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
+ run.
+ * interp.c (sim_set_callbacks): Delete.
+
+ * interp.c (membank, membank_base, membank_size): Replace with
+ STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
+ (sim_open): Remove call to callback->init. gdb/run do this.
+
+ * interp.c: Update
+
+ * sim-main.h (SIM_HAVE_FLATMEM): Define.
+
+ * interp.c (big_endian_p): Delete, replaced by
+ current_target_byte_order.
+
+Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (host_read_long, host_read_word, host_swap_word,
+ host_swap_long): Delete. Using common sim-endian.
+ (sim_fetch_register, sim_store_register): Use H2T.
+ (pipeline_ticks): Delete. Handled by sim-events.
+ (sim_info): Update.
+ (sim_engine_run): Update.
+
+Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_stop_reason): Move code determining simEXCEPTION
+ reason from here.
+ (SignalException): To here. Signal using sim_engine_halt.
+ (sim_stop_reason): Delete, moved to common.
+
+Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
+
+ * interp.c (sim_open): Add callback argument.
+ (sim_set_callbacks): Delete SIM_DESC argument.
+ (sim_size): Ditto.
+
+Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add common modules.
+
+ * interp.c (sim_set_callbacks): Also set SD callback.
+ (set_endianness, xfer_*, swap_*): Delete.
+ (host_read_word, host_read_long, host_swap_word, host_swap_long):
+ Change to functions using sim-endian macros.
+ (control_c, sim_stop): Delete, use common version.
+ (simulate): Convert into.
+ (sim_engine_run): This function.
+ (sim_resume): Delete.
+
+ * interp.c (simulation): New variable - the simulator object.
+ (sim_kind): Delete global - merged into simulation.
+ (sim_load): Cleanup. Move PC assignment from here.
+ (sim_create_inferior): To here.
+
+ * sim-main.h: New file.
+ * interp.c (sim-main.h): Include.
+
+Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * tconfig.in (SIM_HAVE_BIENDIAN): Define.
+
+Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (build_instruction): DIV instructions: check
+ for division by zero and integer overflow before using
+ host's division operation.
+
+Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add sim-load.o.
+ * interp.c: #include bfd.h.
+ (target_byte_order): Delete.
+ (sim_kind, myname, big_endian_p): New static locals.
+ (sim_open): Set sim_kind, myname. Move call to set_endianness to
+ after argument parsing. Recognize -E arg, set endianness accordingly.
+ (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
+ load file into simulator. Set PC from bfd.
+ (sim_create_inferior): Return SIM_RC. Delete arg start_address.
+ (set_endianness): Use big_endian_p instead of target_byte_order.
+
+Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_size): Delete prototype - conflicts with
+ definition in remote-sim.h. Correct definition.
+
+Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * interp.c (sim_open): New arg `kind'.
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * interp.c (sim_open): Set optind to 0 before calling getopt.
+
+Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
+
+ * interp.c : Replace uses of pr_addr with pr_uword64
+ where the bit length is always 64 independent of SIM_ADDR.
+ (pr_uword64) : added.
+
+Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
+
+ * configure: Re-generate.
+
+Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
+
+ * configure: Regenerate to track ../common/aclocal.m4 changes.
+
+Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * interp.c (sim_open): New SIM_DESC result. Argument is now
+ in argv form.
+ (other sim_*): New SIM_DESC argument.
+
+start-sanitize-r5900
+Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
+ Change values to avoid overloading DOUBLEWORD which is tested
+ for all insns.
+ * gencode.c: reinstate "offending code".
+
+end-sanitize-r5900
+Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
+
+ * interp.c: Fix printing of addresses for non-64-bit targets.
+ (pr_addr): Add function to print address based on size.
+start-sanitize-r5900
+ * gencode.c: #ifdef out offending code until a permanent fix
+ can be added. Code is causing build errors for non-5900 mips targets.
+end-sanitize-r5900
+
+start-sanitize-r5900
+Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
+
+ * gencode.c (process_instructions): Correct test for ISA dependent
+ architecture bits in isa field of MIPS_DECODE.
+
+end-sanitize-r5900
+Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
+
+ * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
+
+start-sanitize-r5900
+Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (MIPS_DECODE): Correct instruction feature flags for
+ PMADDUW.
+
+end-sanitize-r5900
+Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * gencode.c (build_mips16_operands): Correct computation of base
+ address for extended PC relative instruction.
+
+start-sanitize-r5900
+Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
+
+ * Makefile.in, configure, configure.in, gencode.c,
+ interp.c, support.h: add r5900.
+
+end-sanitize-r5900
+Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * interp.c (mips16_entry): Add support for floating point cases.
+ (SignalException): Pass floating point cases to mips16_entry.
+ (ValueFPR): Don't restrict fmt_single and fmt_word to even
+ registers.
+ (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
+ or fmt_word.
+ (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
+ and then set the state to fmt_uninterpreted.
+ (COP_SW): Temporarily set the state to fmt_word while calling
+ ValueFPR.
+
+Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * gencode.c (build_instruction): The high order may be set in the
+ comparison flags at any ISA level, not just ISA 4.
+
+Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
+ COMMON_{PRE,POST}_CONFIG_FRAG instead.
+ * configure.in: sinclude ../common/aclocal.m4.
+ * configure: Regenerated.
+
+Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure: Rebuild after change to aclocal.m4.
+
+Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
+
+ * configure configure.in Makefile.in: Update to new configure
+ scheme which is more compatible with WinGDB builds.
+ * configure.in: Improve comment on how to run autoconf.
+ * configure: Re-run autoconf to get new ../common/aclocal.m4.
+ * Makefile.in: Use autoconf substitution to install common
+ makefile fragment.
+
+Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
+
+ * gencode.c (build_instruction): Use BigEndianCPU instead of
+ ByteSwapMem.
+
+Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
+
+ * interp.c (sim_monitor): Make output to stdout visible in
+ wingdb's I/O log window.
+
+Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
+
+ * support.h: Undo previous change to SIGTRAP
+ and SIGQUIT values.
+
+Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * interp.c (store_word, load_word): New static functions.
+ (mips16_entry): New static function.
+ (SignalException): Look for mips16 entry and exit instructions.
+ (simulate): Use the correct index when setting fpr_state after
+ doing a pending move.
+
+Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
+
+ * interp.c: Fix byte-swapping code throughout to work on
+ both little- and big-endian hosts.
+
+Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
+
+ * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
+ with gdb/config/i386/xm-windows.h.
+
+Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
+
+ * gencode.c (build_instruction): Work around MSVC++ code gen bug
+ that messes up arithmetic shifts.
+
+Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
+
+ * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
+ SIGTRAP and SIGQUIT for _WIN32.
+
+Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
+ force a 64 bit multiplication.
+ (build_instruction) [OR]: In mips16 mode, don't do anything if the
+ destination register is 0, since that is the default mips16 nop
+ instruction.
+
Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
+ * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
+ (build_endian_shift): Don't check proc64.
+ (build_instruction): Always set memval to uword64. Cast op2 to
+ uword64 when shifting it left in memory instructions. Always use
+ the same code for stores--don't special case proc64.
+
* gencode.c (build_mips16_operands): Fix base PC value for PC
relative operands.
(build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
(INDELAYSLOT, INJALDELAYSLOT): Define.
(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
+Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
+
+ * interp.c (sim_open): add flush_cache as a PMON routine
+ (sim_monitor): handle flush_cache by ignoring it
+
Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
* gencode.c (build_instruction): Use !ByteSwapMem instead of