2002-02-11 Chris Demetriou <cgd@broadcom.com>

[deliverable/binutils-gdb.git] / sim / mips / ChangeLog

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index f03884a4f7bf1ead2a8c2498c2538340ab34b355..e7d21dce91d19313aec499acac5ff23aea4c6629 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,34 @@
+2002-02-11  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
+       indicating that ALU32_END or ALU64_END are there to check
+       for overflow.
+       (DADD): Likewise, but also remove previous comment about
+       overflow checking.
+
+2002-02-10  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
+       DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
+       JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
+       SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
+       ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
+       fields (i.e., add and move commas) so that they more closely
+       match the MIPS ISA documentation opcode partitioning.
+
+2002-02-10  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.igen (ADDI): Print immediate value.
+        (BREAK): Print code.
+        (DADDIU, DSRAV, DSRLV): Print correct instruction name.
+        (SLL): Print "nop" specially, and don't run the code
+        that does the shift for the "nop" case.
+
+2001-11-17  Fred Fish  <fnf@redhat.com>
+
+       * sim-main.h (float_operation): Move enum declaration outside
+       of _sim_cpu struct declaration.
+
 2001-04-12  Jim Blandy  <jimb@redhat.com>
 
        * mips.igen (CFC1, CTC1): Pass the correct register numbers to