For mips get_mem_size call. Force the return of a 32 bit value

[deliverable/binutils-gdb.git] / sim / mips / ChangeLog

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index d202aa0d5980f7d120fb0f494fc860e7fe28fbca..fd917287855e38c7ca684766c14cda6833c1aceb 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,79 @@
+Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
+       not an address sized quantity.  Return zero for cache sizes.
+
+Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * mips.igen (r3900): r3900 does not support 64 bit integer
+       operations.
+
+start-sanitize-sky
+Wed Apr 1 08:20:31 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+       * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
+       
+end-sanitize-sky
+start-sanitize-sky
+Mon Mar 30 18:41:43 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+       * interp.c (decode_coproc): Continuing COP2 work.
+       (cop_[ls]q): Make sky-target-only.
+
+       * sim-main.h (COP_[LS]Q): Make sky-target-only.
+end-sanitize-sky
+       
+Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
+
+       * configure.in (mipstx39*-*-*): Use gencode simulator rather
+       than igen one.
+       * configure : Rebuild.
+       
+start-sanitize-sky
+Sun Mar 29 17:50:11       Frank Ch. Eigler  <fche@cygnus.com>
+
+       * interp.c (decode_coproc): Added a missing TARGET_SKY check
+       around COP2 implementation skeleton.
+
+end-sanitize-sky
+
+Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+start-sanitize-sky
+       * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
+
+       * interp.c (sim_{load,store}_register): Use new vu[01]_device
+       static to access VU registers.
+       (decode_coproc): Added skeleton of sky COP2 (VU) instruction
+       decoding.  Work in progress.
+
+       * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
+       overlapping/redundant bit pattern.
+       (LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
+       progress.
+
+       * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
+       status register.
+       
+       * interp.c (cop_lq, cop_sq): New functions for future 128-bit
+       access to coprocessor registers.
+
+       * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
+end-sanitize-sky
+
+Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
+
+Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
+
+       * configure: Regenerated to track ../common/aclocal.m4 changes.
+       * config.in: Regenerated to track ../common/aclocal.m4 changes.
+
 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * configure: Regenerated to track ../common/aclocal.m4 changes.