* Makefile.in (SIM_OBJS): Add dsp.o.

[deliverable/binutils-gdb.git] / sim / mips / dv-tx3904tmr.c

diff --git a/sim/mips/dv-tx3904tmr.c b/sim/mips/dv-tx3904tmr.c
index 0d33678dbee662bdd0fcb41b4f3befeb8ee72d3d..c1c7b8ce601f8d77ac4330f378ec5ea9c9c1c378 100644 (file)
--- a/sim/mips/dv-tx3904tmr.c
+++ b/sim/mips/dv-tx3904tmr.c
@@ -372,11 +372,9 @@ tx3904tmr_io_write_buffer (struct hw *me,
   for (byte = 0; byte < nr_bytes; byte++)
     {
       address_word address = base + byte;
-      unsigned_1 write_byte = ((char*) source)[byte];
+      unsigned_1 write_byte = ((const char*) source)[byte];
       int reg_number = (address - controller->base_address) / 4;
       int reg_offset = 3 - (address - controller->base_address) % 4;
-      unsigned_4* register_ptr;
-      unsigned_4 register_value;
 
       /* fill in entire register_value word */
       switch (reg_number)
@@ -518,7 +516,7 @@ deliver_tx3904tmr_tick (struct hw *me,
   /* Check whether the timer ticking is enabled at this moment.  This
      largely a function of the TCE bit, but is also slightly
      mode-dependent. */
-  switch(GET_TCR_TMODE(controller))
+  switch((int) GET_TCR_TMODE(controller))
     {
     case 0: /* interval */
       /* do not advance counter if TCE = 0 or if holding at count = CPRA */
@@ -584,7 +582,7 @@ deliver_tx3904tmr_tick (struct hw *me,
       unsigned_4 next_trr = (controller->trr + 1) % (1 << 24);
       quotient --;
       
-      switch(GET_TCR_TMODE(controller))
+      switch((int) GET_TCR_TMODE(controller))
        {
        case 0: /* interval timer mode */
          {
@@ -681,7 +679,8 @@ deliver_tx3904tmr_tick (struct hw *me,
 
       /* update counter and report */
       controller->trr = next_trr;
-      HW_TRACE ((me, "counter trr %d tisr %x", controller->trr, controller->tisr));
+      /* HW_TRACE ((me, "counter trr %ld tisr %lx",
+        (long) controller->trr, (long) controller->tisr)); */
     } /* end quotient loop */
 
   /* Reschedule a timer event in near future, so we can increment the