/* This file is part of the program GDB, the GNU debugger.
- Copyright (C) 1998 Free Software Foundation, Inc.
+ Copyright (C) 1998-2020 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
-
+
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
-
+
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
signed_8 last_ticks; /* time at last deliver_*_tick call */
signed_8 roundoff_ticks; /* sim ticks unprocessed during last tick call */
int ff; /* pulse generator flip-flop value: 1/0 */
+ struct hw_event* event; /* last scheduled event */
unsigned_4 tcr;
#define GET_TCR_TCE(c) (((c)->tcr & 0x80) >> 7)
controller->trr = 0;
controller->cpra = controller->cprb = 0x00FFFFFF;
controller->ff = 0;
+ controller->last_ticks = controller->roundoff_ticks = 0;
+ controller->event = NULL;
}
controller->tisr =
controller->trr = 0;
controller->cpra = controller->cprb = 0x00FFFFFF;
+ controller->last_ticks = controller->roundoff_ticks = 0;
+ if(controller->event != NULL)
+ hw_event_queue_deschedule(me, controller->event);
+ controller->event = NULL;
break;
}
{
address_word address = base + byte;
int reg_number = (address - controller->base_address) / 4;
- int reg_offset = (address - controller->base_address) % 4;
+ int reg_offset = 3 - (address - controller->base_address) % 4;
unsigned_4 register_value; /* in target byte order */
/* fill in entire register_value word */
for (byte = 0; byte < nr_bytes; byte++)
{
address_word address = base + byte;
- unsigned_1 write_byte = ((char*) source)[byte];
+ unsigned_1 write_byte = ((const char*) source)[byte];
int reg_number = (address - controller->base_address) / 4;
- int reg_offset = (address - controller->base_address) % 4;
- unsigned_4* register_ptr;
- unsigned_4 register_value;
+ int reg_offset = 3 - (address - controller->base_address) % 4;
/* fill in entire register_value word */
switch (reg_number)
if(GET_TCR_TCE(controller) == 0 &&
GET_TCR_CRE(controller) == 1)
controller->trr = 0;
-
}
- HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr));
+ /* HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr)); */
break;
case ITMR_REG:
{
SET_ITMR_TZCE(controller, write_byte & 0x01);
}
- HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr));
+ /* HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr)); */
break;
case CCDR_REG:
{
controller->ccdr = write_byte & 0x07;
}
- HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr));
+ /* HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr)); */
break;
case PMGR_REG:
{
SET_PMGR_FFI(controller, write_byte & 0x01);
}
- HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr));
+ /* HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr)); */
break;
case WTMR_REG:
SET_WTMR_WDIS(controller, write_byte & 0x80);
SET_WTMR_TWC(controller, write_byte & 0x01);
}
- HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr));
+ /* HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr)); */
break;
case TISR_REG:
/* clear interrupt status register */
controller->tisr = 0;
}
- HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr));
+ /* HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr)); */
break;
case CPRA_REG:
if(reg_offset < 3) /* first, second, or third byte */
{
- MBLIT32(controller->cpra, (reg_offset*8), (reg_offset*8+7), write_byte);
+ MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte);
}
- HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra));
+ /* HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra)); */
break;
case CPRB_REG:
if(reg_offset < 3) /* first, second, or third byte */
{
- MBLIT32(controller->cprb, (reg_offset*8), (reg_offset*8+7), write_byte);
+ MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
}
- HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb));
+ /* HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb)); */
break;
default:
SIM_DESC sd = hw_system (me);
signed_8 this_ticks = sim_events_time(sd);
- /* compute simulation ticks between last tick and this tick */
- signed_8 warp = this_ticks - controller->last_ticks + controller->roundoff_ticks;
+ signed_8 warp;
signed_8 divisor;
- signed_8 quotient, reminder;
+ signed_8 quotient, remainder;
+
+ /* compute simulation ticks between last tick and this tick */
+ if(controller->last_ticks != 0)
+ warp = this_ticks - controller->last_ticks + controller->roundoff_ticks;
+ else
+ {
+ controller->last_ticks = this_ticks; /* initialize */
+ warp = controller->roundoff_ticks;
+ }
+
+ if(controller->event != NULL)
+ hw_event_queue_deschedule(me, controller->event);
+ controller->event = NULL;
/* Check whether the timer ticking is enabled at this moment. This
largely a function of the TCE bit, but is also slightly
mode-dependent. */
- switch(GET_TCR_TMODE(controller))
+ switch((int) GET_TCR_TMODE(controller))
{
case 0: /* interval */
/* do not advance counter if TCE = 0 or if holding at count = CPRA */
{
/* apply internal clock divider */
if(GET_TCR_CCDE(controller)) /* divisor circuit enabled? */
- divisor = controller->ext_ticks * (1 << (1 + GET_CCDR_CDR(controller)));
+ divisor = controller->clock_ticks * (1 << (1 + GET_CCDR_CDR(controller)));
else
- divisor = controller->ext_ticks;
+ divisor = controller->clock_ticks;
}
else
{
- divisor = controller->clock_ticks;
+ divisor = controller->ext_ticks;
}
/* how many times to increase counter? */
quotient = warp / divisor;
- reminder = warp % divisor;
+ remainder = warp % divisor;
/* NOTE: If the event rescheduling code works properly, the quotient
should never be larger than 1. That is, we should receive events
here at least as frequently as the simulated counter is supposed
- to decrement. So the reminder (-> roundoff_ticks) will slowly
+ to decrement. So the remainder (-> roundoff_ticks) will slowly
accumulate, with the quotient == 0. Once in a while, quotient
will equal 1. */
- controller->roundoff_ticks = reminder;
+ controller->roundoff_ticks = remainder;
controller->last_ticks = this_ticks;
while(quotient > 0) /* Is it time to increment counter? */
{
unsigned_4 next_trr = (controller->trr + 1) % (1 << 24);
quotient --;
- switch(GET_TCR_TMODE(controller))
+ switch((int) GET_TCR_TMODE(controller))
{
case 0: /* interval timer mode */
{
case 3: /* disabled */
default:
+ break;
}
/* update counter and report */
controller->trr = next_trr;
- HW_TRACE ((me, "counter trr %d tisr %x", controller->trr, controller->tisr));
+ /* HW_TRACE ((me, "counter trr %ld tisr %lx",
+ (long) controller->trr, (long) controller->tisr)); */
} /* end quotient loop */
/* Reschedule a timer event in near future, so we can increment the
- counter again. Set the event about 50% of divisor time away, so
- we will experience roughly two events per counter increment. */
- hw_event_queue_schedule(me, divisor/2, deliver_tx3904tmr_tick, NULL);
+ counter again. Set the event about 75% of divisor time away, so
+ we will experience roughly 1.3 events per counter increment. */
+ controller->event = hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL);
}
projects / deliverable / binutils-gdb.git / blobdiff