$Revision$
$Author$
- $Date$
+ $Date$
NOTEs:
#define PROFILE (1)
#endif
+#include "bfd.h"
+#include "sim-main.h"
+#include "sim-utils.h"
+#include "sim-options.h"
+#include "sim-assert.h"
+
+#include "config.h"
+
#include <stdio.h>
#include <stdarg.h>
#include <ansidecl.h>
-#include <signal.h>
#include <ctype.h>
#include <limits.h>
#include <math.h>
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#ifdef HAVE_STRING_H
+#include <string.h>
+#else
+#ifdef HAVE_STRINGS_H
+#include <strings.h>
+#endif
+#endif
#include "getopt.h"
#include "libiberty.h"
-
-#include "remote-sim.h" /* GDB simulator interface */
+#include "bfd.h"
#include "callback.h" /* GDB simulator callback interface */
+#include "remote-sim.h" /* GDB simulator interface */
+
+#include "sysdep.h"
+
+#ifndef PARAMS
+#define PARAMS(x)
+#endif
+
+char* pr_addr PARAMS ((SIM_ADDR addr));
+char* pr_uword64 PARAMS ((uword64 addr));
-#include "support.h" /* internal support manifests */
/* Get the simulator engine description, without including the code: */
#define SIM_MANIFESTS
#include "engine.c"
#undef SIM_MANIFESTS
+
/* The following reserved instruction value is used when a simulator
trap is required. NOTE: Care must be taken, since this value may be
used in later revisions of the MIPS ISA. */
-#define RSVD_INSTRUCTION (0x7C000000)
-#define RSVD_INSTRUCTION_AMASK (0x03FFFFFF)
-
-/* NOTE: These numbers depend on the processor architecture being
- simulated: */
-#define Interrupt (0)
-#define TLBModification (1)
-#define TLBLoad (2)
-#define TLBStore (3)
-#define AddressLoad (4)
-#define AddressStore (5)
-#define InstructionFetch (6)
-#define DataReference (7)
-#define SystemCall (8)
-#define BreakPoint (9)
-#define ReservedInstruction (10)
-#define CoProcessorUnusable (11)
-#define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
-#define Trap (13)
-#define FPE (15)
-#define Watch (23)
-
-/* The following exception code is actually private to the simulator
- world. It is *NOT* a processor feature, and is used to signal
- run-time errors in the simulator. */
-#define SimulatorFault (0xFFFFFFFF)
+#define RSVD_INSTRUCTION (0x00000005)
+#define RSVD_INSTRUCTION_MASK (0xFC00003F)
+
+#define RSVD_INSTRUCTION_ARG_SHIFT 6
+#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
+
/* The following are generic to all versions of the MIPS architecture
to date: */
#define AccessLength_SEXTIBYTE (5)
#define AccessLength_SEPTIBYTE (6)
#define AccessLength_DOUBLEWORD (7)
+#define AccessLength_QUADWORD (15)
-#if defined(HASFPU)
-/* FPU registers must be one of the following types. All other values
- are reserved (and undefined). */
-typedef enum {
- fmt_single = 0,
- fmt_double = 1,
- fmt_word = 4,
- fmt_long = 5,
- /* The following are well outside the normal acceptable format
- range, and are used in the register status vector. */
- fmt_unknown = 0x10000000,
- fmt_uninterpreted = 0x20000000,
-} FP_formats;
-#endif /* HASFPU */
-/* NOTE: We cannot avoid globals, since the GDB "sim_" interface does
- not allow a private variable to be passed around. This means that
- simulators under GDB can only be single-threaded. However, it would
- be possible for the simulators to be multi-threaded if GDB allowed
- for a private pointer to be maintained. i.e. a general "void **ptr"
- variable that GDB passed around in the argument list to all of
- sim_xxx() routines. It could be initialised to NULL by GDB, and
- then updated by sim_open() and used by the other sim_xxx() support
- functions. This would allow new features in the simulator world,
- like storing a context - continuing execution to gather a result,
- and then going back to the point where the context was saved and
- changing some state before continuing. i.e. the ability to perform
- UNDOs on simulations. It would also allow the simulation of
- shared-memory multi-processor systems. */
-
-static host_callback *callback = NULL; /* handle onto the current callback structure */
-
-/* The warning system should be improved, to allow more information to
- be passed about the cause: */
-#define WARNING(m) { callback->printf_filtered(callback,"SIM Warning: %s\n",(m)); }
-
-/* This is nasty, since we have to rely on matching the register
- numbers used by GDB. Unfortunately, depending on the MIPS target
- GDB uses different register numbers. We cannot just include the
- relevant "gdb/tm.h" link, since GDB may not be configured before
- the sim world, and also the GDB header file requires too much other
- state. */
-/* TODO: Sort out a scheme for *KNOWING* the mapping between real
- registers, and the numbers that GDB uses. At the moment due to the
- order that the tools are built, we cannot rely on a configured GDB
- world whilst constructing the simulator. This means we have to
- assume the GDB register number mapping. */
-#define LAST_EMBED_REGNUM (89)
-
-/* To keep this default simulator simple, and fast, we use a direct
- vector of registers. The internal simulator engine then uses
- manifests to access the correct slot. */
-ut_reg registers[LAST_EMBED_REGNUM + 1];
-int register_widths[LAST_EMBED_REGNUM + 1];
-
-#define GPR (®isters[0])
-#if defined(HASFPU)
-#define FGRIDX (38)
-#define FGR (®isters[FGRIDX])
-#endif /* HASFPU */
-#define LO (registers[33])
-#define HI (registers[34])
-#define PC (registers[37])
-#define CAUSE (registers[36])
-#define SRIDX (32)
-#define SR (registers[SRIDX]) /* CPU status register */
-#define FCR0IDX (71)
-#define FCR0 (registers[FCR0IDX]) /* really a 32bit register */
-#define FCR31IDX (70)
-#define FCR31 (registers[FCR31IDX]) /* really a 32bit register */
-#define FCSR (FCR31)
-#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
-
-/* The following are pseudonyms for standard registers */
-#define ZERO (registers[0])
-#define V0 (registers[2])
-#define A0 (registers[4])
-#define A1 (registers[5])
-#define A2 (registers[6])
-#define A3 (registers[7])
-#define SP (registers[29])
-#define RA (registers[31])
-
-ut_reg EPC = 0; /* Exception PC */
+/* Bits in the Debug register */
+#define Debug_DBD 0x80000000 /* Debug Branch Delay */
+#define Debug_DM 0x40000000 /* Debug Mode */
+#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
+
-#if defined(HASFPU)
-/* Keep the current format state for each register: */
-FP_formats fpr_state[32];
-#endif /* HASFPU */
-/* VR4300 CP0 configuration register: */
-unsigned int CONFIG = 0;
+/* start-sanitize-r5900 */
-/* The following are internal simulator state variables: */
-ut_reg IPC = 0; /* internal Instruction PC */
-ut_reg DSPC = 0; /* delay-slot PC */
+#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
+#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
+#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
+#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
+
+#define BYTES_IN_MIPS_REGS (sizeof(signed_word))
+#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
+#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
+#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
+
+
+
+
+/*
+SUB_REG_FETCH - return as lvalue some sub-part of a "register"
+ T - type of the sub part
+ TC - # of T's in the mips part of the "register"
+ I - index (from 0) of desired sub part
+ A - low part of "register"
+ A1 - high part of register
+*/
+#define SUB_REG_FETCH(T,TC,A,A1,I) \
+(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
+ + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
+ ? ((TC) - 1 - (I) % (TC)) \
+ : ((I) % (TC)) \
+ ) \
+ ) \
+ )
+
+/*
+GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
+ where <type> has two letters:
+ 1 is S=signed or U=unsigned
+ 2 is B=byte H=halfword W=word D=doubleword
+*/
+
+#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
+
+#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
+
+#define GPR_SB(R,I) SUB_REG_SB(®ISTERS[R], ®ISTERS1[R], I)
+#define GPR_SH(R,I) SUB_REG_SH(®ISTERS[R], ®ISTERS1[R], I)
+#define GPR_SW(R,I) SUB_REG_SW(®ISTERS[R], ®ISTERS1[R], I)
+#define GPR_SD(R,I) SUB_REG_SD(®ISTERS[R], ®ISTERS1[R], I)
+
+#define GPR_UB(R,I) SUB_REG_UB(®ISTERS[R], ®ISTERS1[R], I)
+#define GPR_UH(R,I) SUB_REG_UH(®ISTERS[R], ®ISTERS1[R], I)
+#define GPR_UW(R,I) SUB_REG_UW(®ISTERS[R], ®ISTERS1[R], I)
+#define GPR_UD(R,I) SUB_REG_UD(®ISTERS[R], ®ISTERS1[R], I)
+
+
+#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
+#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
+#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
+#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
+
+#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
+#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
+#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
+#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
+
+#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
+#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
+#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
+#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
+
+#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
+#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
+#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
+#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
+
+
+
+#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
+#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
+#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
+#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
+
+#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
+#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
+#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
+#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
+
+#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
+#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
+#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
+#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
+
+#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
+#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
+#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
+#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
+/* end-sanitize-r5900 */
/* TODO : these should be the bitmasks for these bits within the
#define ksu_user (0x2)
#define ksu_unknown (0x3)
+#define status_IE (1 << 0) /* Interrupt enable */
+#define status_EXL (1 << 1) /* Exception level */
#define status_RE (1 << 25) /* Reverse Endian in user mode */
#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
#define status_SR (1 << 20) /* soft reset or NMI */
#define status_ERL (1 << 2) /* Error level */
#define status_RP (1 << 27) /* Reduced Power mode */
-#define config_EP_mask (0xF)
-#define config_EP_shift (27)
-#define config_EP_D (0x0)
-#define config_EP_DxxDxx (0x6)
-
-#define config_BE (1 << 15)
-
#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
#if defined(HASFPU)
/* This should be the COC1 value at the start of the preceding
instruction: */
-#define PREVCOC1() ((state & simPCOC1) ? 1 : 0)
+#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
#endif /* HASFPU */
/* Standard FCRS bits: */
#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
-/* Slots for delayed register updates. For the moment we just have a
- fixed number of slots (rather than a more generic, dynamic
- system). This keeps the simulator fast. However, we only allow for
- the register update to be delayed for a single instruction
- cycle. */
-#define PSLOTS (5) /* Maximum number of instruction cycles */
-int pending_in;
-int pending_out;
-int pending_total;
-int pending_slot_count[PSLOTS];
-int pending_slot_reg[PSLOTS];
-ut_reg pending_slot_value[PSLOTS];
+/*---------------------------------------------------------------------------*/
+/*-- GDB simulator interface ------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+
+static void dotrace PARAMS((SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...));
+static void ColdReset PARAMS((SIM_DESC sd));
+static long getnum PARAMS((SIM_DESC sd, char *value));
+static unsigned int power2 PARAMS((unsigned int value));
+static void mips_set_profile PARAMS((SIM_DESC sd, int n));
+static void mips_set_profile_size PARAMS((SIM_DESC sd, int n));
+static void mips_size PARAMS((SIM_DESC sd, int n));
+
+/*---------------------------------------------------------------------------*/
/* The following are not used for MIPS IV onwards: */
#define PENDING_FILL(r,v) {\
-printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\
- if (pending_slot_reg[pending_in] != (LAST_EMBED_REGNUM + 1))\
- callback->printf_filtered(callback,"SIM Warning: Attempt to over-write pending value\n");\
- pending_slot_count[pending_in] = 2;\
- pending_slot_reg[pending_in] = (r);\
- pending_slot_value[pending_in] = (uword64)(v);\
-printf("DBG: FILL reg %d value = 0x%08X%08X\n",(r),WORD64HI(v),WORD64LO(v));\
- pending_total++;\
- pending_in++;\
- if (pending_in == PSLOTS)\
- pending_in = 0;\
-printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\
+/* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
+ if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
+ sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
+ PENDING_SLOT_COUNT[PENDING_IN] = 2;\
+ PENDING_SLOT_REG[PENDING_IN] = (r);\
+ PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
+/*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\
+ PENDING_TOTAL++;\
+ PENDING_IN++;\
+ if (PENDING_IN == PSLOTS)\
+ PENDING_IN = 0;\
+/*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
}
-int LLBIT = 0;
-/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
- read-write instructions. It is set when a linked load occurs. It is
- tested and cleared by the conditional store. It is cleared (during
- other CPU operations) when a store to the location would no longer
- be atomic. In particular, it is cleared by exception return
- instructions. */
-
-int HIACCESS = 0;
-int LOACCESS = 0;
-/* The HIACCESS and LOACCESS counts are used to ensure that
- corruptions caused by using the HI or LO register to close to a
- following operation are spotted. */
-
-/* If either of the preceding two instructions have accessed the HI or
- LO registers, then the values they see should be
- undefined. However, to keep the simulator world simple, we just let
- them use the value read and raise a warning to notify the user: */
-#define CHECKHILO(s) {\
- if ((HIACCESS != 0) || (LOACCESS != 0))\
- callback->printf_filtered(callback,"SIM Warning: %s over-writing HI and LO registers values\n",(s));\
- /* Set the access counts, since we are about\
- to update the HI and LO registers: */\
- HIACCESS = LOACCESS = 3; /* 3rd instruction will be safe */\
- }
/* NOTE: We keep the following status flags as bit values (1 for true,
0 for false). This allows them to be used in binary boolean
/* Hardware configuration. Affects endianness of LoadMemory and
StoreMemory and the endianness of Kernel and Supervisor mode
execution. The value is 0 for little-endian; 1 for big-endian. */
-#define BigEndianMem ((CONFIG & config_BE) ? 1 : 0)
-/* NOTE: Problems will occur if the simulator memory model does not
- match the host program expectation. i.e. if the host is writing
- big-endian values to a little-endian memory model. */
+#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
+/*(state & simBE) ? 1 : 0)*/
+
+/* ByteSwapMem */
+/* This is true if the host and target have different endianness. */
+#define ByteSwapMem (CURRENT_TARGET_BYTE_ORDER != CURRENT_HOST_BYTE_ORDER)
/* ReverseEndian */
/* This mode is selected if in User mode with the RE bit being set in
/* The endianness for load and store instructions (0=little;1=big). In
User mode this endianness may be switched by setting the state_RE
bit in the SR register. Thus, BigEndianCPU may be computed as
- (BigEndienMem EOR ReverseEndian). */
+ (BigEndianMem EOR ReverseEndian). */
#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
#if !defined(FASTSIM) || defined(PROFILE)
/* At the moment these values will be the same, since we do not have
access to the pipeline cycle count information from the simulator
engine. */
-unsigned int instruction_fetches = 0;
-unsigned int pipeline_ticks = 0;
+/* FIXME: These will be replaced by ../common/sim-profile.h */
+static unsigned int instruction_fetches = 0;
+static unsigned int instruction_fetch_overflow = 0;
#endif
/* Flags in the "state" variable: */
-#define simSTOP (1 << 0) /* 0 = execute; 1 = stop simulation */
-#define simSTEP (1 << 1) /* 0 = run; 1 = single-step */
#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
#define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */
-#define simHOSTBE (1 << 10) /* 0 = little-endian; 1 = big-endian (host endianness) */
-/* Whilst simSTOP is not set, the simulator control loop should just
- keep simulating instructions. The simSTEP flag is used to force
- single-step execution. */
-#define simBE (1 << 16) /* 0 = little-endian; 1 = big-endian (target endianness) */
#define simPCOC0 (1 << 17) /* COC[1] from current */
#define simPCOC1 (1 << 18) /* COC[1] from previous */
#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
-#define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
-#define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
-
-unsigned int state = (0 | simBE); /* big-endian simulator by default */
-unsigned int rcexit = 0; /* _exit() reason code holder */
+#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
+#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
#define DELAYSLOT() {\
- if (state & simDELAYSLOT) callback->printf_filtered(callback,"SIM Warning: Delay slot already activated (branch in delay slot?)\n");\
- state |= simDELAYSLOT;\
+ if (STATE & simDELAYSLOT)\
+ sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
+ STATE |= simDELAYSLOT;\
}
+#define JALDELAYSLOT() {\
+ DELAYSLOT ();\
+ STATE |= simJALDELAYSLOT;\
+ }
+
#define NULLIFY() {\
- state &= ~simDELAYSLOT;\
- state |= simSKIPNEXT;\
+ STATE &= ~simDELAYSLOT;\
+ STATE |= simSKIPNEXT;\
}
-/* Very simple memory model to start with: */
-unsigned char *membank = NULL;
-ut_reg membank_base = 0xA0000000;
-unsigned membank_size = (1 << 20); /* (16 << 20); */ /* power-of-2 */
+#define CANCELDELAYSLOT() {\
+ DSSTATE = 0;\
+ STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
+ }
+
+#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
+#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
+
+#define K0BASE (0x80000000)
+#define K0SIZE (0x20000000)
+#define K1BASE (0xA0000000)
+#define K1SIZE (0x20000000)
/* Simple run-time monitor support */
-unsigned char *monitor = NULL;
-ut_reg monitor_base = 0xBFC00000;
-unsigned monitor_size = (1 << 11); /* power-of-2 */
+static unsigned char *monitor = NULL;
+static ut_reg monitor_base = 0xBFC00000;
+static unsigned monitor_size = (1 << 11); /* power-of-2 */
+
+static char *logfile = NULL; /* logging disabled by default */
+static FILE *logfh = NULL;
#if defined(TRACE)
-char *tracefile = "trace.din"; /* default filename for trace log */
-FILE *tracefh = NULL;
+static char *tracefile = "trace.din"; /* default filename for trace log */
+static FILE *tracefh = NULL;
+static void open_trace PARAMS((SIM_DESC sd));
#endif /* TRACE */
#if defined(PROFILE)
-unsigned profile_frequency = 256;
-unsigned profile_nsamples = (128 << 10);
-unsigned short *profile_hist = NULL;
-ut_reg profile_minpc;
-ut_reg profile_maxpc;
-int profile_shift = 0; /* address shift amount */
+static unsigned profile_frequency = 256;
+static unsigned profile_nsamples = (128 << 10);
+static unsigned short *profile_hist = NULL;
+static ut_reg profile_minpc;
+static ut_reg profile_maxpc;
+static int profile_shift = 0; /* address shift amount */
#endif /* PROFILE */
+
+static SIM_RC
+mips_option_handler (sd, opt, arg)
+ SIM_DESC sd;
+ int opt;
+ char *arg;
+{
+ switch (opt)
+ {
+ case 'l':
+ if (arg != NULL) {
+ char *tmp;
+ tmp = (char *)malloc(strlen(arg) + 1);
+ if (tmp == NULL)
+ sim_io_printf(sd,"Failed to allocate buffer for logfile name \"%s\"\n",optarg);
+ else {
+ strcpy(tmp,optarg);
+ logfile = tmp;
+ }
+ }
+ return SIM_RC_OK;
+
+ case 'n': /* OK */
+ sim_io_printf(sd,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg);
+ return SIM_RC_FAIL;
+
+ case 't': /* ??? */
+#if defined(TRACE)
+ /* Eventually the simTRACE flag could be treated as a toggle, to
+ allow external control of the program points being traced
+ (i.e. only from main onwards, excluding the run-time setup,
+ etc.). */
+ if (arg == NULL)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "yes") == 0)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "no") == 0)
+ STATE &= ~simTRACE;
+ else
+ {
+ fprintf (stderr, "Unreconized trace option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+ return SIM_RC_OK;
+#else /* !TRACE */
+ fprintf(stderr,"\
+Simulator constructed without tracing support (for performance).\n\
+Re-compile simulator with \"-DTRACE\" to enable this option.\n");
+ return SIM_RC_FAIL;
+#endif /* !TRACE */
+
+ case 'z':
+#if defined(TRACE)
+ if (optarg != NULL) {
+ char *tmp;
+ tmp = (char *)malloc(strlen(optarg) + 1);
+ if (tmp == NULL)
+ {
+ sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
+ return SIM_RC_FAIL;
+ }
+ else {
+ strcpy(tmp,optarg);
+ tracefile = tmp;
+ sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
+ }
+ }
+#endif /* TRACE */
+ return SIM_RC_OK;
+
+ case 'p':
+#if defined(PROFILE)
+ STATE |= simPROFILE;
+ return SIM_RC_OK;
+#else /* !PROFILE */
+ fprintf(stderr,"\
+Simulator constructed without profiling support (for performance).\n\
+Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
+ return SIM_RC_FAIL;
+#endif /* !PROFILE */
+
+ case 'x':
+#if defined(PROFILE)
+ profile_nsamples = (unsigned)getnum(sd, optarg);
+#endif /* PROFILE */
+ return SIM_RC_OK;
+
+ case 'y':
+#if defined(PROFILE)
+ mips_set_profile(sd, (int)getnum(sd, optarg));
+#endif /* PROFILE */
+ return SIM_RC_OK;
+
+ }
+
+ return SIM_RC_OK;
+}
+
+static const OPTION mips_options[] =
+{
+ { {"log", required_argument, NULL,'l'},
+ 'l', "FILE", "Log file",
+ mips_option_handler },
+ { {"name", required_argument, NULL,'n'},
+ 'n', "MODEL", "Select arch model",
+ mips_option_handler },
+ { {"profile", optional_argument, NULL,'p'},
+ 'p', "on|off", "Enable profiling",
+ mips_option_handler },
+ { {"trace", optional_argument, NULL,'t'},
+ 't', "on|off", "Enable tracing",
+ mips_option_handler },
+ { {"tracefile",required_argument, NULL,'z'},
+ 'z', "FILE", "Write trace to file",
+ mips_option_handler },
+ { {"frequency",required_argument, NULL,'y'},
+ 'y', "FREQ", "Profile frequency",
+ mips_option_handler },
+ { {"samples", required_argument, NULL,'x'},
+ 'x', "SIZE", "Profile sample size",
+ mips_option_handler },
+ { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
+};
+
+
+int interrupt_pending;
+
+static void
+interrupt_event (SIM_DESC sd, void *data)
+{
+ if (SR & status_IE)
+ {
+ interrupt_pending = 0;
+ SignalExceptionInterrupt ();
+ }
+ else if (!interrupt_pending)
+ sim_events_schedule (sd, 1, interrupt_event, data);
+}
+
+
+
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
-static void dotrace PARAMS((FILE *tracefh,int type,unsigned int address,int width,char *comment,...));
-extern void sim_error PARAMS((char *fmt,...));
-static void ColdReset PARAMS((void));
-static int AddressTranslation PARAMS((uword64 vAddr,int IorD,int LorS,uword64 *pAddr,int *CCA,int host,int raw));
-static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64 pAddr,uword64 vAddr,int raw));
-static uword64 LoadMemory PARAMS((int CCA,int AccessLength,uword64 pAddr,uword64 vAddr,int IorD,int raw));
-static void SignalException PARAMS((int exception,...));
-static void simulate PARAMS((void));
-static long getnum(char *value);
-extern void sim_size(unsigned int newsize);
-extern void sim_set_profile(int frequency);
-static unsigned int power2(unsigned int value);
-
-void
-sim_open (args)
- char *args;
+SIM_DESC
+sim_open (kind, cb, abfd, argv)
+ SIM_OPEN_KIND kind;
+ host_callback *cb;
+ struct _bfd *abfd;
+ char **argv;
{
- if (callback == NULL) {
- fprintf(stderr,"SIM Error: sim_open() called without callbacks attached\n");
- return;
- }
+ SIM_DESC sd = sim_state_alloc (kind, cb);
+ sim_cpu *cpu = STATE_CPU (sd, 0);
+
+ /* FIXME: watchpoints code shouldn't need this */
+ STATE_WATCHPOINTS (sd)->pc = &(PC);
+ STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+ STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
+
+ /* memory defaults (unless sim_size was here first) */
+ if (STATE_MEM_SIZE (sd) == 0)
+ STATE_MEM_SIZE (sd) = (2 << 20);
+ STATE_MEM_BASE (sd) = K1BASE;
+
+ STATE = 0;
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ return 0;
+ sim_add_option_table (sd, mips_options);
+
+ /* getopt will print the error message so we just have to exit if this fails.
+ FIXME: Hmmm... in the case of gdb we need getopt to call
+ print_filtered. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
- /* The following ensures that the standard file handles for stdin,
- stdout and stderr are initialised: */
- callback->init(callback);
+ /* check for/establish the a reference program image */
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL),
+ abfd) != SIM_RC_OK)
+ {
+ sim_module_uninstall (sd);
+ return 0;
+ }
- state = 0;
- CHECKSIM();
- if (state & simEXCEPTION) {
- fprintf(stderr,"This simulator is not suitable for this host configuration\n");
- exit(1);
- }
+ /* Configure/verify the target byte order and other runtime
+ configuration options */
+ if (sim_config (sd) != SIM_RC_OK)
+ {
+ sim_module_uninstall (sd);
+ return 0;
+ }
- {
- int data = 0x12;
- if (*((char *)&data) != 0x12)
- state |= simHOSTBE; /* big-endian host */
- }
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ /* verify assumptions the simulator made about the host type system.
+ This macro does not return if there is a problem */
+ if (sizeof(int) != (4 * sizeof(char)))
+ SignalExceptionSimulatorFault ("sizeof(int) != 4");
+ if (sizeof(word64) != (8 * sizeof(char)))
+ SignalExceptionSimulatorFault ("sizeof(word64) != 8");
#if defined(HASFPU)
/* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
and DOUBLE binary formats. This is a bit nasty, requiring that we
trust the explicit manifests held in the source: */
+ /* TODO: We need to cope with the simulated target and the host not
+ having the same endianness. This will require the high and low
+ words of a (double) to be swapped when converting between the
+ host and the simulated target. */
{
- unsigned int s[2];
- s[0] = 0x40805A5A;
- s[1] = 0x00000000;
- if (((float)4.01102924346923828125 != *(float *)s) || ((double)523.2939453125 != *(double *)s)) {
- fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
- fprintf(stderr,"*(float *)s = %f (4.01102924346923828125)\n",*(float *)s);
- fprintf(stderr,"*(double *)s = %f (523.2939453125)\n",*(double *)s);
- exit(1);
- }
+ union {
+ unsigned int i[2];
+ double d;
+ float f[2];
+ } s;
+
+ s.d = (double)523.2939453125;
+
+ if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125
+ || s.i[1] != 0x40805A5A))
+ || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125
+ || s.i[0] != 0x40805A5A)))
+ {
+ fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
+ return 0;
+ }
}
#endif /* HASFPU */
int rn;
for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
if (rn < 32)
- register_widths[rn] = GPRLEN;
+ cpu->register_widths[rn] = GPRLEN;
else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
- register_widths[rn] = GPRLEN;
+ cpu->register_widths[rn] = GPRLEN;
else if ((rn >= 33) && (rn <= 37))
- register_widths[rn] = GPRLEN;
+ cpu->register_widths[rn] = GPRLEN;
else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
- register_widths[rn] = 32;
+ cpu->register_widths[rn] = 32;
else
- register_widths[rn] = 0;
+ cpu->register_widths[rn] = 0;
}
- }
-
- /* It would be good if we could select particular named MIPS
- architecture simulators. However, having a pre-built, fixed
- engine would mean including multiple engines. If the simulator is
- changed to a run-time conditional version, then the ability to
- select a particular architecture would be straightforward. */
- if (args != NULL) {
- int c;
- char *cline;
- char **argv;
- int argc;
- static struct option cmdline[] = {
- {"help", 0,0,'h'},
- {"name", 1,0,'n'},
- {"profile", 0,0,'p'},
- {"size", 1,0,'s'},
- {"trace", 0,0,'t'},
- {"tracefile",1,0,'z'},
- {"frequency",1,0,'y'},
- {"samples", 1,0,'x'},
- {0, 0,0,0}
- };
-
- /* Unfortunately, getopt_long() is designed to be used with
- vectors, where the first option is normally program name (and
- ignored). We cheat by creating a dummy first argument, so that
- we can use the standard argument processing. */
-#define DUMMYARG "simulator "
- cline = (char *)malloc(strlen(args) + strlen(DUMMYARG) + 1);
- if (cline == NULL) {
- fprintf(stderr,"Failed to allocate memory for command line buffer\n");
- exit(1);
- }
- sprintf(cline,"%s%s",DUMMYARG,args);
- argv = buildargv(cline);
- for (argc = 0; argv[argc]; argc++);
-
- /* Unfortunately, getopt_long() assumes that it is ignoring the
- first argument (normally the program name). This means it
- ignores the first option on our "args" line. */
- optind = 0; /* Force reset of argument processing */
- while (1) {
- int option_index = 0;
-
- c = getopt_long(argc,argv,"hn:s:tp",cmdline,&option_index);
- if (c == -1)
- break;
+ /* start-sanitize-r5900 */
- switch (c) {
- case 'h':
- callback->printf_filtered(callback,"Usage:\n\t\
-target sim [-h] [--name=<model>] [--size=<amount>]");
-#if defined(TRACE)
- callback->printf_filtered(callback," [-t [--tracefile=<name>]]");
-#endif /* TRACE */
-#if defined(PROFILE)
- callback->printf_filtered(callback," [-p [--frequency=<count>] [--samples=<count>]]");
-#endif /* PROFILE */
- callback->printf_filtered(callback,"\n");
- break;
-
- case 'n':
- callback->printf_filtered(callback,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg);
- break;
-
- case 's':
- membank_size = (unsigned)getnum(optarg);
- break;
-
- case 't':
-#if defined(TRACE)
- /* Eventually the simTRACE flag could be treated as a toggle, to
- allow external control of the program points being traced
- (i.e. only from main onwards, excluding the run-time setup,
- etc.). */
- state |= simTRACE;
-#else /* !TRACE */
- fprintf(stderr,"\
-Simulator constructed without tracing support (for performance).\n\
-Re-compile simulator with \"-DTRACE\" to enable this option.\n");
-#endif /* !TRACE */
- break;
-
- case 'z':
-#if defined(TRACE)
- if (optarg != NULL) {
- char *tmp;
- tmp = (char *)malloc(strlen(optarg) + 1);
- if (tmp == NULL)
- callback->printf_filtered(callback,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
- else {
- strcpy(tmp,optarg);
- tracefile = tmp;
- callback->printf_filtered(callback,"Placing trace information into file \"%s\"\n",tracefile);
- }
- }
-#endif /* TRACE */
- break;
-
- case 'p':
-#if defined(PROFILE)
- state |= simPROFILE;
-#else /* !PROFILE */
- fprintf(stderr,"\
-Simulator constructed without profiling support (for performance).\n\
-Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
-#endif /* !PROFILE */
- break;
-
- case 'x':
-#if defined(PROFILE)
- profile_nsamples = (unsigned)getnum(optarg);
-#endif /* PROFILE */
- break;
+ /* set the 5900 "upper" registers to 64 bits */
+ for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
+ cpu->register_widths[rn] = 64;
+ /* end-sanitize-r5900 */
+ }
- case 'y':
-#if defined(PROFILE)
- sim_set_profile((int)getnum(optarg));
-#endif /* PROFILE */
- break;
- default:
- callback->printf_filtered(callback,"Warning: Simulator getopt returned unrecognised code 0x%08X\n",c);
- case '?':
- break;
+ if (logfile != NULL) {
+ if (strcmp(logfile,"-") == 0)
+ logfh = stdout;
+ else {
+ logfh = fopen(logfile,"wb+");
+ if (logfh == NULL) {
+ sim_io_printf(sd,"Failed to create file \"%s\", writing log information to stderr.\n",tracefile);
+ logfh = stderr;
}
}
-
- if (optind < argc) {
- callback->printf_filtered(callback,"Warning: Ignoring spurious non-option arguments ");
- while (optind < argc)
- callback->printf_filtered(callback,"\"%s\" ",argv[optind++]);
- callback->printf_filtered(callback,"\n");
- }
-
- freeargv(argv);
}
+ /* FIXME: In the future both of these malloc's can be replaced by
+ calls to sim-core. */
+
/* If the host has "mmap" available we could use it to provide a
very large virtual address space for the simulator, since memory
would only be allocated within the "mmap" space as it is
accessed. This can also be linked to the architecture specific
support, required to simulate the MMU. */
- sim_size(membank_size);
- /* NOTE: The above will also have enabled any profiling state */
+ mips_size(sd, STATE_MEM_SIZE (sd));
+ /* NOTE: The above will also have enabled any profiling state! */
+
+ /* Create the monitor address space as well */
+ monitor = (unsigned char *)calloc(1,monitor_size);
+ if (!monitor)
+ fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n",
+ monitor_size);
- ColdReset();
- /* If we were providing a more complete I/O, co-processor or memory
- simulation, we should perform any "device" initialisation at this
- point. This can include pre-loading memory areas with particular
- patterns (e.g. simulating ROM monitors). */
+#if defined(TRACE)
+ if (STATE & simTRACE)
+ open_trace(sd);
+#endif /* TRACE */
- /* We can start writing to the memory, now that the processor has
- been reset: */
- monitor = (unsigned char *)calloc(1,monitor_size);
- if (!monitor) {
- fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size);
- } else {
- int loop;
- /* TODO: Provide support for PMON monitor */
+ /* Write the monitor trap address handlers into the monitor (eeprom)
+ address space. This can only be done once the target endianness
+ has been determined. */
+ {
+ unsigned loop;
/* Entry into the IDT monitor is via fixed address vectors, and
not using machine instructions. To avoid clashing with use of
the MIPS TRAP system, we place our own (simulator specific)
uword64 vaddr = (monitor_base + loop);
uword64 paddr;
int cca;
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
- StoreMemory(cca,AccessLength_WORD,(RSVD_INSTRUCTION | ((loop >> 2) & RSVD_INSTRUCTION_AMASK)),paddr,vaddr,isRAW);
+ if (AddressTranslation(vaddr, isDATA, isSTORE, &paddr, &cca, isTARGET, isRAW))
+ StoreMemory(cca, AccessLength_WORD,
+ (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)),
+ 0, paddr, vaddr, isRAW);
}
+ /* The PMON monitor uses the same address space, but rather than
+ branching into it the address of a routine is loaded. We can
+ cheat for the moment, and direct the PMON routine to IDT style
+ instructions within the monitor space. This relies on the IDT
+ monitor not using the locations from 0xBFC00500 onwards as its
+ entry points.*/
+ for (loop = 0; (loop < 24); loop++)
+ {
+ uword64 vaddr = (monitor_base + 0x500 + (loop * 4));
+ uword64 paddr;
+ int cca;
+ unsigned int value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
+ switch (loop)
+ {
+ case 0: /* read */
+ value = 7;
+ break;
+
+ case 1: /* write */
+ value = 8;
+ break;
+
+ case 2: /* open */
+ value = 6;
+ break;
+
+ case 3: /* close */
+ value = 10;
+ break;
+
+ case 5: /* printf */
+ value = ((0x500 - 16) / 8); /* not an IDT reason code */
+ break;
+
+ case 8: /* cliexit */
+ value = 17;
+ break;
+
+ case 11: /* flush_cache */
+ value = 28;
+ break;
+ }
+ /* FIXME - should monitor_base be SIM_ADDR?? */
+ value = ((unsigned int)monitor_base + (value * 8));
+ if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
+ else
+ sim_io_error(sd,"Failed to write to monitor space 0x%s",pr_addr(vaddr));
+
+ /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
+ vaddr -= 0x300;
+ if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
+ else
+ sim_io_error(sd,"Failed to write to monitor space 0x%s",pr_addr(vaddr));
+ }
}
-#if defined(TRACE)
- if (state & simTRACE) {
- tracefh = fopen(tracefile,"wb+");
- if (tracefh == NULL) {
- callback->printf_filtered(callback,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
- tracefh = stderr;
- }
- }
-#endif /* TRACE */
+ return sd;
+}
- return;
+#if defined(TRACE)
+static void
+open_trace(sd)
+ SIM_DESC sd;
+{
+ tracefh = fopen(tracefile,"wb+");
+ if (tracefh == NULL)
+ {
+ sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
+ tracefh = stderr;
+ }
}
+#endif /* TRACE */
/* For the profile writing, we write the data in the host
endianness. This unfortunately means we are assuming that the
endianness, or a method of encoding the endianness in the file
header. */
static int
-writeout32(fh,val)
+writeout32(sd,fh,val)
+ SIM_DESC sd;
FILE *fh;
unsigned int val;
{
char buff[4];
int res = 1;
- if (state & simHOSTBE) {
+ if (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN) {
buff[3] = ((val >> 0) & 0xFF);
buff[2] = ((val >> 8) & 0xFF);
buff[1] = ((val >> 16) & 0xFF);
buff[3] = ((val >> 24) & 0xFF);
}
if (fwrite(buff,4,1,fh) != 1) {
- callback->printf_filtered(callback,"Failed to write 4bytes to the profile file\n");
+ sim_io_eprintf(sd,"Failed to write 4bytes to the profile file\n");
res = 0;
}
return(res);
}
static int
-writeout16(fh,val)
+writeout16(sd,fh,val)
+ SIM_DESC sd;
FILE *fh;
unsigned short val;
{
char buff[2];
int res = 1;
- if (state & simHOSTBE) {
+ if (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN) {
buff[1] = ((val >> 0) & 0xFF);
buff[0] = ((val >> 8) & 0xFF);
} else {
buff[1] = ((val >> 8) & 0xFF);
}
if (fwrite(buff,2,1,fh) != 1) {
- callback->printf_filtered(callback,"Failed to write 2bytes to the profile file\n");
+ sim_io_eprintf(sd,"Failed to write 2bytes to the profile file\n");
res = 0;
}
return(res);
}
void
-sim_close (quitting)
+sim_close (sd, quitting)
+ SIM_DESC sd;
int quitting;
{
#ifdef DEBUG
printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
#endif
- /* Cannot assume sim_kill() has been called */
/* "quitting" is non-zero if we cannot hang on errors */
/* Ensure that any resources allocated through the callback
mechanism are released: */
- callback->shutdown(callback);
+ sim_io_shutdown (sd);
#if defined(PROFILE)
- if ((state & simPROFILE) && (profile_hist != NULL)) {
- unsigned short *p = profile_hist;
+ if ((STATE & simPROFILE) && (profile_hist != NULL)) {
FILE *pf = fopen("gmon.out","wb");
- int loop;
+ unsigned loop;
if (pf == NULL)
- callback->printf_filtered(callback,"Failed to open \"gmon.out\" profile file\n");
+ sim_io_eprintf(sd,"Failed to open \"gmon.out\" profile file\n");
else {
int ok;
#ifdef DEBUG
- printf("DBG: minpc = 0x%08X\n",(unsigned int)profile_minpc);
- printf("DBG: maxpc = 0x%08X\n",(unsigned int)profile_maxpc);
+ printf("DBG: minpc = 0x%s\n",pr_addr(profile_minpc));
+ printf("DBG: maxpc = 0x%s\n",pr_addr(profile_maxpc));
#endif /* DEBUG */
ok = writeout32(pf,(unsigned int)profile_minpc);
if (ok)
free(profile_hist);
profile_hist = NULL;
- state &= ~simPROFILE;
+ STATE &= ~simPROFILE;
}
#endif /* PROFILE */
#if defined(TRACE)
- if (tracefh != stderr)
+ if (tracefh != NULL && tracefh != stderr)
fclose(tracefh);
- state &= ~simTRACE;
+ tracefh = NULL;
+ STATE &= ~simTRACE;
#endif /* TRACE */
- if (membank)
- free(membank); /* cfree not available on all hosts */
- membank = NULL;
-
- return;
-}
-
-void
-sim_resume (step,signal)
- int step, signal;
-{
-#ifdef DEBUG
- printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step,signal,membank);
-#endif /* DEBUG */
-
- if (step)
- state |= simSTEP; /* execute only a single instruction */
- else
- state &= ~(simSTOP | simSTEP); /* execute until event */
-
- state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */
+ if (logfh != NULL && logfh != stdout && logfh != stderr)
+ fclose(logfh);
+ logfh = NULL;
- /* Start executing instructions from the current state (set
- explicitly by register updates, or by sim_create_inferior): */
+ if (STATE_MEMORY (sd) != NULL)
+ free(STATE_MEMORY (sd)); /* cfree not available on all hosts */
+ STATE_MEMORY (sd) = NULL;
- simulate();
return;
}
+
int
-sim_write (addr,buffer,size)
+sim_write (sd,addr,buffer,size)
+ SIM_DESC sd;
SIM_ADDR addr;
unsigned char *buffer;
int size;
/* Return the number of bytes written, or zero if error. */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_write(0x%08X%08X,buffer,%d);\n",WORD64HI(addr),WORD64LO(addr),size);
+ sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif
/* We provide raw read and write routines, since we do not want to
int cca;
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
uword64 value = ((uword64)(*buffer++));
- StoreMemory(cca,AccessLength_BYTE,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_BYTE,value,0,paddr,vaddr,isRAW);
}
vaddr++;
index &= ~1; /* logical operations usually quicker than arithmetic on RISC systems */
value = ((uword64)(*buffer++) << 0);
value |= ((uword64)(*buffer++) << 8);
}
- StoreMemory(cca,AccessLength_HALFWORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_HALFWORD,value,0,paddr,vaddr,isRAW);
}
vaddr += 2;
index &= ~2;
value |= ((uword64)(*buffer++) << 16);
value |= ((uword64)(*buffer++) << 24);
}
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
}
vaddr += 4;
index &= ~4;
value |= ((uword64)(*buffer++) << 48);
value |= ((uword64)(*buffer++) << 56);
}
- StoreMemory(cca,AccessLength_DOUBLEWORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_DOUBLEWORD,value,0,paddr,vaddr,isRAW);
}
vaddr += 8;
}
}
int
-sim_read (addr,buffer,size)
+sim_read (sd,addr,buffer,size)
+ SIM_DESC sd;
SIM_ADDR addr;
unsigned char *buffer;
int size;
/* Return the number of bytes read, or zero if error. */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_read(0x%08X%08X,buffer,%d);\n",WORD64HI(addr),WORD64LO(addr),size);
+ sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif /* DEBUG */
/* TODO: Perform same optimisation as the sim_write() code
int cca;
vaddr = (uword64)addr + index;
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&cca,isTARGET,isRAW)) {
- value = LoadMemory(cca,AccessLength_BYTE,paddr,vaddr,isDATA,isRAW);
+ LoadMemory(&value,NULL,cca,AccessLength_BYTE,paddr,vaddr,isDATA,isRAW);
buffer[index] = (unsigned char)(value&0xFF);
} else
break;
}
void
-sim_store_register (rn,memory)
+sim_store_register (sd,rn,memory)
+ SIM_DESC sd;
int rn;
unsigned char *memory;
{
+ sim_cpu *cpu = STATE_CPU (sd, 0);
+ /* NOTE: gdb (the client) stores registers in target byte order
+ while the simulator uses host byte order */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_store_register(%d,*memory=0x%08X%08X);\n",rn,*((unsigned int *)memory),*((unsigned int *)(memory + 4)));
+ sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
#endif /* DEBUG */
/* Unfortunately this suffers from the same problem as the register
numbering one. We need to know what the width of each logical
register number is for the architecture being simulated. */
- if (register_widths[rn] == 0)
- callback->printf_filtered(callback,"Warning: Invalid register width for %d (register store ignored)\n",rn);
- else {
- if (register_widths[rn] == 32)
- registers[rn] = *((unsigned int *)memory);
- else
- registers[rn] = *((uword64 *)memory);
- }
+
+ if (cpu->register_widths[rn] == 0)
+ sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
+ /* start-sanitize-r5900 */
+ else if (rn == REGISTER_SA)
+ SA = T2H_8(*(uword64*)memory);
+ else if (rn > LAST_EMBED_REGNUM)
+ cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory);
+ /* end-sanitize-r5900 */
+ else if (cpu->register_widths[rn] == 32)
+ cpu->registers[rn] = T2H_4 (*(unsigned int*)memory);
+ else
+ cpu->registers[rn] = T2H_8 (*(uword64*)memory);
return;
}
void
-sim_fetch_register (rn,memory)
+sim_fetch_register (sd,rn,memory)
+ SIM_DESC sd;
int rn;
unsigned char *memory;
{
+ sim_cpu *cpu = STATE_CPU (sd, 0);
+ /* NOTE: gdb (the client) stores registers in target byte order
+ while the simulator uses host byte order */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_fetch_register(%d=0x%08X%08X,mem) : place simulator registers into memory\n",rn,WORD64HI(registers[rn]),WORD64LO(registers[rn]));
+ sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
#endif /* DEBUG */
- if (register_widths[rn] == 0)
- callback->printf_filtered(callback,"Warning: Invalid register width for %d (register fetch ignored)\n",rn);
- else {
- if (register_widths[rn] == 32)
- *((unsigned int *)memory) = (registers[rn] & 0xFFFFFFFF);
- else /* 64bit register */
- *((uword64 *)memory) = registers[rn];
- }
- return;
-}
+ if (cpu->register_widths[rn] == 0)
+ sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
+ /* start-sanitize-r5900 */
+ else if (rn == REGISTER_SA)
+ *((uword64 *)memory) = H2T_8(SA);
+ else if (rn > LAST_EMBED_REGNUM)
+ *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
+ /* end-sanitize-r5900 */
+ else if (cpu->register_widths[rn] == 32)
+ *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF));
+ else /* 64bit register */
+ *((uword64 *)memory) = H2T_8 (cpu->registers[rn]);
-void
-sim_stop_reason (reason,sigrc)
- enum sim_stop *reason;
- int *sigrc;
-{
-/* We can have "*reason = {sim_exited, sim_stopped, sim_signalled}", so
- sim_exited *sigrc = argument to exit()
- sim_stopped *sigrc = exception number
- sim_signalled *sigrc = signal number
-*/
- if (state & simEXCEPTION) {
- /* If "sim_signalled" is used, GDB expects normal SIGNAL numbers,
- and not the MIPS specific exception codes. */
-#if 1
- /* For some reason, sending GDB a sim_signalled reason cause it to
- terminate out. */
- *reason = sim_stopped;
-#else
- *reason = sim_signalled;
-#endif
- switch ((CAUSE >> 2) & 0x1F) {
- case Interrupt:
- *sigrc = SIGINT; /* wrong type of interrupt, but it will do for the moment */
- break;
-
- case TLBModification:
- case TLBLoad:
- case TLBStore:
- case AddressLoad:
- case AddressStore:
- case InstructionFetch:
- case DataReference:
- *sigrc = SIGBUS;
- break;
-
- case ReservedInstruction:
- case CoProcessorUnusable:
- *sigrc = SIGILL;
- break;
-
- case IntegerOverflow:
- case FPE:
- *sigrc = SIGFPE;
- break;
-
- case Trap:
- case Watch:
- case SystemCall:
- case BreakPoint:
- *sigrc = SIGTRAP;
- break;
-
- default : /* Unknown internal exception */
- *sigrc = SIGQUIT;
- break;
- }
- } else if (state & simEXIT) {
- printf("DBG: simEXIT (%d)\n",rcexit);
- *reason = sim_exited;
- *sigrc = rcexit;
- } else { /* assume single-stepping */
- *reason = sim_stopped;
- *sigrc = SIGTRAP;
- }
- state &= ~(simEXCEPTION | simEXIT);
return;
}
+
void
-sim_info (verbose)
+sim_info (sd,verbose)
+ SIM_DESC sd;
int verbose;
{
/* Accessed from the GDB "info files" command: */
-
- callback->printf_filtered(callback,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT ? 64 : 32));
-
- callback->printf_filtered(callback,"%s endian memory model\n",(BigEndianMem ? "Big" : "Little"));
-
- callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%08X%08X\n",(unsigned int)membank_size,WORD64HI(membank_base),WORD64LO(membank_base));
-
+ if (STATE_VERBOSE_P (sd) || verbose)
+ {
+
+ sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
+ (PROCESSOR_64BIT ? 64 : 32),
+ (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
+
+ sim_io_printf (sd, "0x%08X bytes of memory at 0x%s\n",
+ STATE_MEM_SIZE (sd),
+ pr_addr (STATE_MEM_BASE (sd)));
+
#if !defined(FASTSIM)
- callback->printf_filtered(callback,"Instruction fetches = %d\n",instruction_fetches);
- callback->printf_filtered(callback,"Pipeline ticks = %d\n",pipeline_ticks);
- /* It would be a useful feature, if when performing multi-cycle
- simulations (rather than single-stepping) we keep the start and
- end times of the execution, so that we can give a performance
- figure for the simulator. */
+#if 0
+ /* at present this simulator executes one instruction per
+ simulator cycle. Consequently this data never changes */
+ if (instruction_fetch_overflow != 0)
+ sim_io_printf (sd, "Instruction fetches = 0x%08X%08X\n",
+ instruction_fetch_overflow, instruction_fetches);
+ else
+ sim_io_printf (sd, "Instruction fetches = %d\n", instruction_fetches);
+#endif
+ /* It would be a useful feature, if when performing multi-cycle
+ simulations (rather than single-stepping) we keep the start and
+ end times of the execution, so that we can give a performance
+ figure for the simulator. */
#endif /* !FASTSIM */
-
- /* print information pertaining to MIPS ISA and architecture being simulated */
- /* things that may be interesting */
- /* instructions executed - if available */
- /* cycles executed - if available */
- /* pipeline stalls - if available */
- /* virtual time taken */
- /* profiling size */
- /* profiling frequency */
- /* profile minpc */
- /* profile maxpc */
-
- return;
+ sim_io_printf (sd, "Number of execution cycles = %ld\n",
+ (long) sim_events_time (sd));
+
+ /* print information pertaining to MIPS ISA and architecture being simulated */
+ /* things that may be interesting */
+ /* instructions executed - if available */
+ /* cycles executed - if available */
+ /* pipeline stalls - if available */
+ /* virtual time taken */
+ /* profiling size */
+ /* profiling frequency */
+ /* profile minpc */
+ /* profile maxpc */
+ }
}
-int
-sim_load (prog,from_tty)
- char *prog;
- int from_tty;
-{
- /* Return non-zero if the caller should handle the load. Zero if
- we have loaded the image. */
- return(-1);
-}
-void
-sim_create_inferior (start_address,argv,env)
- SIM_ADDR start_address;
+SIM_RC
+sim_create_inferior (sd, abfd, argv,env)
+ SIM_DESC sd;
+ struct _bfd *abfd;
char **argv;
char **env;
{
+
#ifdef DEBUG
- printf("DBG: sim_create_inferior entered: start_address = 0x%08X\n",start_address);
+ printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
+ pr_addr(PC));
#endif /* DEBUG */
- /* Prepare to execute the program to be simulated */
- /* argv and env are NULL terminated lists of pointers */
+ ColdReset(sd);
+ /* If we were providing a more complete I/O, co-processor or memory
+ simulation, we should perform any "device" initialisation at this
+ point. This can include pre-loading memory areas with particular
+ patterns (e.g. simulating ROM monitors). */
#if 1
- PC = (uword64)start_address;
+ if (abfd != NULL)
+ PC = (unsigned64) bfd_get_start_address(abfd);
+ else
+ PC = 0; /* ???? */
#else
/* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */
- PC = SIGNEXTEND(start_address,32);
+ PC = SIGNEXTEND(bfd_get_start_address(abfd),32);
#endif
- /* NOTE: GDB normally sets the PC explicitly. However, this call is
- used by other clients of the simulator. */
+
+ /* Prepare to execute the program to be simulated */
+ /* argv and env are NULL terminated lists of pointers */
if (argv || env) {
- callback->printf_filtered(callback,"sim_create_inferior() : passed arguments ignored\n");
-#if 1 /* def DEBUG */
+#if 0 /* def DEBUG */
+ sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
{
char **cptr;
for (cptr = argv; (cptr && *cptr); cptr++)
true at the moment. */
}
- return;
-}
-
-void
-sim_kill ()
-{
-#if 1
- /* This routine should be for terminating any existing simulation
- thread. Since we are single-threaded only at the moment, this is
- not an issue. It should *NOT* be used to terminate the
- simulator. */
-#else /* do *NOT* call sim_close */
- sim_close(1); /* Do not hang on errors */
- /* This would also be the point where any memory mapped areas used
- by the simulator should be released. */
-#endif
- return;
-}
-
-int
-sim_get_quit_code ()
-{
- /* The standard MIPS PCS (Procedure Calling Standard) uses V0(r2) as
- the function return value. However, it may be more correct for
- this to return the argument to the exit() function (if
- called). */
- return(V0);
-}
-
-void
-sim_set_callbacks (p)
- host_callback *p;
-{
- callback = p;
- return;
+ return SIM_RC_OK;
}
typedef enum {e_terminate,e_help,e_setmemsize,e_reset} e_cmds;
};
void
-sim_do_command (cmd)
+sim_do_command (sd,cmd)
+ SIM_DESC sd;
char *cmd;
{
struct t_sim_command *cptr;
/* NOTE: Accessed from the GDB "sim" commmand: */
for (cptr = sim_commands; cptr && cptr->name; cptr++)
- if (strncmp(cmd,cptr->name,strlen(cptr->name)) == 0) {
- cmd += strlen(cptr->name);
- switch (cptr->id) {
- case e_help: /* no arguments */
- { /* no arguments */
- struct t_sim_command *lptr;
- callback->printf_filtered(callback,"List of MIPS simulator commands:\n");
- for (lptr = sim_commands; lptr->name; lptr++)
- callback->printf_filtered(callback,"%s %s\n",lptr->name,lptr->help);
- }
- break;
-
- case e_setmemsize: /* memory size argument */
- {
- unsigned int newsize = (unsigned int)getnum(cmd);
- sim_size(newsize);
- }
+ if (strncmp (cmd, cptr->name, strlen(cptr->name)) == 0)
+ {
+ cmd += strlen(cptr->name);
+ switch (cptr->id) {
+ case e_help: /* no arguments */
+ { /* no arguments */
+ struct t_sim_command *lptr;
+ sim_io_printf(sd,"List of MIPS simulator commands:\n");
+ for (lptr = sim_commands; lptr->name; lptr++)
+ sim_io_printf(sd,"%s %s\n",lptr->name,lptr->help);
+ sim_args_command (sd, "help");
+ }
break;
- case e_reset: /* no arguments */
- ColdReset();
- /* NOTE: See the comments in sim_open() relating to device
- initialisation. */
+ case e_setmemsize: /* memory size argument */
+ {
+ unsigned int newsize = (unsigned int)getnum(sd, cmd);
+ mips_size(sd, newsize);
+ }
break;
- default:
- callback->printf_filtered(callback,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd,cptr->id);
- break;
- }
- break;
- }
+ case e_reset: /* no arguments */
+ ColdReset(sd);
+ /* NOTE: See the comments in sim_open() relating to device
+ initialisation. */
+ break;
+
+ default:
+ sim_io_printf(sd,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd,cptr->id);
+ break;
+ }
+ break;
+ }
if (!(cptr->name))
- callback->printf_filtered(callback,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd);
+ {
+ /* try for a common command when the sim specific lookup fails */
+ if (sim_args_command (sd, cmd) != SIM_RC_OK)
+ sim_io_printf(sd,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd);
+ }
return;
}
/* The profiling format is described in the "gmon_out.h" header file */
-void
-sim_set_profile (n)
+static void
+mips_set_profile (sd,n)
+ SIM_DESC sd;
int n;
{
#if defined(PROFILE)
profile_frequency = n;
- state |= simPROFILE;
+ STATE |= simPROFILE;
#endif /* PROFILE */
return;
}
-void
-sim_set_profile_size (n)
+static void
+mips_set_profile_size (sd,n)
+ SIM_DESC sd;
int n;
{
#if defined(PROFILE)
- if (state & simPROFILE) {
+ if (STATE & simPROFILE) {
int bsize;
/* Since we KNOW that the memory banks are a power-of-2 in size: */
profile_nsamples = power2(n);
- profile_minpc = membank_base;
- profile_maxpc = (membank_base + membank_size);
+ profile_minpc = STATE_MEM_BASE (sd);
+ profile_maxpc = (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd));
/* Just in-case we are sampling every address: NOTE: The shift
right of 2 is because we only have word-aligned PC addresses. */
- if (profile_nsamples > (membank_size >> 2))
- profile_nsamples = (membank_size >> 2);
+ if (profile_nsamples > (STATE_MEM_SIZE (sd) >> 2))
+ profile_nsamples = (STATE_MEM_SIZE (sd) >> 2);
/* Since we are dealing with power-of-2 values: */
- profile_shift = (((membank_size >> 2) / profile_nsamples) - 1);
+ profile_shift = (((STATE_MEM_SIZE (sd) >> 2) / profile_nsamples) - 1);
bsize = (profile_nsamples * sizeof(unsigned short));
if (profile_hist == NULL)
else
profile_hist = (unsigned short *)realloc(profile_hist,bsize);
if (profile_hist == NULL) {
- callback->printf_filtered(callback,"Failed to allocate VM for profiling buffer (0x%08X bytes)\n",bsize);
- state &= ~simPROFILE;
+ sim_io_eprintf(sd,"Failed to allocate VM for profiling buffer (0x%08X bytes)\n",bsize);
+ STATE &= ~simPROFILE;
}
}
#endif /* PROFILE */
return;
}
-void
-sim_size(newsize)
- unsigned int newsize;
+static void
+mips_size(sd, newsize)
+ SIM_DESC sd;
+ int newsize;
{
char *new;
/* Used by "run", and internally, to set the simulated memory size */
+ if (newsize == 0) {
+ sim_io_printf(sd,"Zero not valid: Memory size still 0x%08X bytes\n",STATE_MEM_SIZE (sd));
+ return;
+ }
newsize = power2(newsize);
- if (membank == NULL)
- new = (char *)calloc(64,(membank_size / 64));
+ if (STATE_MEMORY (sd) == NULL)
+ new = (char *)calloc(64,(STATE_MEM_SIZE (sd) / 64));
else
- new = (char *)realloc(membank,newsize);
+ new = (char *)realloc(STATE_MEMORY (sd),newsize);
if (new == NULL) {
- if (membank == NULL)
- callback->printf_filtered(callback,"Not enough VM for simulation memory of 0x%08X bytes\n",membank_size);
+ if (STATE_MEMORY (sd) == NULL)
+ sim_io_error(sd,"Not enough VM for simulation memory of 0x%08X bytes",STATE_MEM_SIZE (sd));
else
- callback->printf_filtered(callback,"Failed to resize memory (still 0x%08X bytes)\n",membank_size);
+ sim_io_eprintf(sd,"Failed to resize memory (still 0x%08X bytes)\n",STATE_MEM_SIZE (sd));
} else {
- membank_size = (unsigned)newsize;
- membank = new;
- callback->printf_filtered(callback,"Memory size now 0x%08X bytes\n",membank_size);
+ STATE_MEM_SIZE (sd) = (unsigned)newsize;
+ STATE_MEMORY (sd) = new;
#if defined(PROFILE)
/* Ensure that we sample across the new memory range */
- sim_set_profile_size(profile_nsamples);
+ mips_set_profile_size(sd, profile_nsamples);
#endif /* PROFILE */
}
return;
}
-int
-sim_trace()
-{
- /* This routine is called by the "run" program, when detailed
- execution information is required. Rather than executing a single
- instruction, and looping around externally... we just start
- simulating, returning TRUE when the simulator stops (for whatever
- reason). */
-
-#if defined(TRACE)
- /* Ensure tracing is enabled, if available */
- if (tracefh != NULL)
- state |= simTRACE;
-#endif /* TRACE */
-
- state &= ~(simSTOP | simSTEP); /* execute until event */
- state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */
- /* Start executing instructions from the current state (set
- explicitly by register updates, or by sim_create_inferior): */
- simulate();
-
- return(1);
-}
/*---------------------------------------------------------------------------*/
/*-- Private simulator support interface ------------------------------------*/
/*---------------------------------------------------------------------------*/
-/* Simple monitor interface (currently setup for the IDT monitor) */
+/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
static void
-sim_monitor(reason)
+sim_monitor(sd,reason)
+ SIM_DESC sd;
unsigned int reason;
{
+#ifdef DEBUG
+ printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
+#endif /* DEBUG */
+
/* The IDT monitor actually allows two instructions per vector
slot. However, the simulator currently causes a trap on each
individual instruction. We cheat, and lose the bottom bit. */
switch (reason) {
case 6: /* int open(char *path,int flags) */
{
- const char *ptr;
uword64 paddr;
int cca;
if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
- V0 = callback->open(callback,(char *)((int)paddr),(int)A1);
+ V0 = sim_io_open(sd,(char *)((int)paddr),(int)A1);
else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory");
}
break;
case 7: /* int read(int file,char *ptr,int len) */
{
- const char *ptr;
uword64 paddr;
int cca;
if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
- V0 = callback->read(callback,(int)A0,(char *)((int)paddr),(int)A2);
+ V0 = sim_io_read(sd,(int)A0,(char *)((int)paddr),(int)A2);
else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory");
}
break;
case 8: /* int write(int file,char *ptr,int len) */
{
- const char *ptr;
uword64 paddr;
int cca;
if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
- V0 = callback->write(callback,(int)A0,(const char *)((int)paddr),(int)A2);
+ V0 = sim_io_write(sd,(int)A0,(const char *)((int)paddr),(int)A2);
else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory");
}
break;
case 10: /* int close(int file) */
- V0 = callback->close(callback,(int)A0);
+ V0 = sim_io_close(sd,(int)A0);
break;
case 11: /* char inbyte(void) */
{
char tmp;
- if (callback->read_stdin(callback,&tmp,sizeof(char)) != sizeof(char)) {
- callback->printf_filtered(callback,"WARNING: Invalid return from character read\n");
- V0 = -1;
+ if (sim_io_read_stdin(sd,&tmp,sizeof(char)) != sizeof(char)) {
+ sim_io_error(sd,"Invalid return from character read");
+ V0 = (ut_reg)-1;
}
else
- V0 = tmp;
+ V0 = (ut_reg)tmp;
}
break;
case 12: /* void outbyte(char chr) : write a byte to "stdout" */
{
char tmp = (char)(A0 & 0xFF);
- callback->write_stdout(callback,&tmp,sizeof(char));
+ sim_io_write_stdout(sd,&tmp,sizeof(char));
}
break;
case 17: /* void _exit() */
- callback->printf_filtered(callback,"sim_monitor(17): _exit(int reason) to be coded\n");
- state |= (simSTOP | simEXIT); /* stop executing code */
- rcexit = (unsigned int)(A0 & 0xFFFFFFFF);
+ sim_io_eprintf(sd,"sim_monitor(17): _exit(int reason) to be coded\n");
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited,
+ (unsigned int)(A0 & 0xFFFFFFFF));
+ break;
+
+ case 28 : /* PMON flush_cache */
break;
case 55: /* void get_mem_info(unsigned int *ptr) */
/* Memory size */
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) {
- value = (uword64)membank_size;
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
+ value = (uword64)STATE_MEM_SIZE (sd);
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
/* We re-do the address translations, in-case the block
overlaps a memory boundary: */
value = 0;
vaddr += (AccessLength_WORD + 1);
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) {
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_WORD,0,value,paddr,vaddr,isRAW);
vaddr += (AccessLength_WORD + 1);
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL))
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
else
failed = -1;
} else
failed = -1;
} else
- failed = -1;
-
- if (failed)
- callback->printf_filtered(callback,"WARNING: Invalid pointer passed into monitor call\n");
+ failed = -1;
+
+ if (failed)
+ sim_io_error(sd,"Invalid pointer passed into monitor call");
+ }
+ break;
+
+ case 158 : /* PMON printf */
+ /* in: A0 = pointer to format string */
+ /* A1 = optional argument 1 */
+ /* A2 = optional argument 2 */
+ /* A3 = optional argument 3 */
+ /* out: void */
+ /* The following is based on the PMON printf source */
+ {
+ uword64 paddr;
+ int cca;
+ /* This isn't the quickest way, since we call the host print
+ routine for every character almost. But it does avoid
+ having to allocate and manage a temporary string buffer. */
+ if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) {
+ char *s = (char *)((int)paddr);
+ ut_reg *ap = &A1; /* 1st argument */
+ /* TODO: Include check that we only use three arguments (A1, A2 and A3) */
+ for (; *s;) {
+ if (*s == '%') {
+ char tmp[40];
+ enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
+ int width = 0, trunc = 0, haddot = 0, longlong = 0;
+ s++;
+ for (; *s; s++) {
+ if (strchr ("dobxXulscefg%", *s))
+ break;
+ else if (*s == '-')
+ fmt = FMT_LJUST;
+ else if (*s == '0')
+ fmt = FMT_RJUST0;
+ else if (*s == '~')
+ fmt = FMT_CENTER;
+ else if (*s == '*') {
+ if (haddot)
+ trunc = (int)*ap++;
+ else
+ width = (int)*ap++;
+ } else if (*s >= '1' && *s <= '9') {
+ char *t;
+ unsigned int n;
+ for (t = s; isdigit (*s); s++);
+ strncpy (tmp, t, s - t);
+ tmp[s - t] = '\0';
+ n = (unsigned int)strtol(tmp,NULL,10);
+ if (haddot)
+ trunc = n;
+ else
+ width = n;
+ s--;
+ } else if (*s == '.')
+ haddot = 1;
+ }
+ if (*s == '%') {
+ sim_io_printf(sd,"%%");
+ } else if (*s == 's') {
+ if ((int)*ap != 0) {
+ if (AddressTranslation(*ap++,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) {
+ char *p = (char *)((int)paddr);;
+ sim_io_printf(sd,p);
+ } else {
+ ap++;
+ sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory");
+ }
+ }
+ else
+ sim_io_printf(sd,"(null)");
+ } else if (*s == 'c') {
+ int n = (int)*ap++;
+ sim_io_printf(sd,"%c",n);
+ } else {
+ if (*s == 'l') {
+ if (*++s == 'l') {
+ longlong = 1;
+ ++s;
+ }
+ }
+ if (strchr ("dobxXu", *s)) {
+ word64 lv = (word64) *ap++;
+ if (*s == 'b')
+ sim_io_printf(sd,"<binary not supported>");
+ else {
+ sprintf(tmp,"%%%s%c",longlong ? "ll" : "",*s);
+ if (longlong)
+ sim_io_printf(sd,tmp,lv);
+ else
+ sim_io_printf(sd,tmp,(int)lv);
+ }
+ } else if (strchr ("eEfgG", *s)) {
+#ifdef _MSC_VER /* MSVC version 2.x can't convert from uword64 directly */
+ double dbl = (double)((word64)*ap++);
+#else
+ double dbl = (double)*ap++;
+#endif
+ sprintf(tmp,"%%%d.%d%c",width,trunc,*s);
+ sim_io_printf(sd,tmp,dbl);
+ trunc = 0;
+ }
+ }
+ s++;
+ } else
+ sim_io_printf(sd,"%c",*s++);
+ }
+ } else
+ sim_io_error(sd,"Attempt to pass pointer that does not reference simulated memory");
}
break;
default:
- callback->printf_filtered(callback,"TODO: sim_monitor(%d) : PC = 0x%08X%08X\n",reason,WORD64HI(IPC),WORD64LO(IPC));
- callback->printf_filtered(callback,"(Arguments : A0 = 0x%08X%08X : A1 = 0x%08X%08X : A2 = 0x%08X%08X : A3 = 0x%08X%08X)\n",WORD64HI(A0),WORD64LO(A0),WORD64HI(A1),WORD64LO(A1),WORD64HI(A2),WORD64LO(A2),WORD64HI(A3),WORD64LO(A3));
+ sim_io_eprintf(sd,"TODO: sim_monitor(%d) : PC = 0x%s\n",reason,pr_addr(IPC));
+ sim_io_eprintf(sd,"(Arguments : A0 = 0x%s : A1 = 0x%s : A2 = 0x%s : A3 = 0x%s)\n",pr_addr(A0),pr_addr(A1),pr_addr(A2),pr_addr(A3));
break;
}
return;
}
-void
-sim_error(fmt)
- char *fmt;
+/* Store a word into memory. */
+
+static void
+store_word (sd, vaddr, val)
+ SIM_DESC sd;
+ uword64 vaddr;
+ t_reg val;
{
- va_list ap;
- va_start(ap,fmt);
- callback->printf_filtered(callback,"SIM Error: ");
- callback->printf_filtered(callback,fmt,ap);
- va_end(ap);
- SignalException(SimulatorFault,"");
- return;
+ uword64 paddr;
+ int uncached;
+
+ if ((vaddr & 3) != 0)
+ SignalExceptionAddressStore ();
+ else
+ {
+ if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
+ isTARGET, isREAL))
+ {
+ const uword64 mask = 7;
+ uword64 memval;
+ unsigned int byte;
+
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
+ byte = (vaddr & mask) ^ (BigEndianCPU << 2);
+ memval = ((uword64) val) << (8 * byte);
+ StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
+ isREAL);
+ }
+ }
+}
+
+/* Load a word from memory. */
+
+static t_reg
+load_word (sd, vaddr)
+ SIM_DESC sd;
+ uword64 vaddr;
+{
+ if ((vaddr & 3) != 0)
+ SignalExceptionAddressLoad ();
+ else
+ {
+ uword64 paddr;
+ int uncached;
+
+ if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
+ isTARGET, isREAL))
+ {
+ const uword64 mask = 0x7;
+ const unsigned int reverse = ReverseEndian ? 1 : 0;
+ const unsigned int bigend = BigEndianCPU ? 1 : 0;
+ uword64 memval;
+ unsigned int byte;
+
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
+ LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
+ isDATA, isREAL);
+ byte = (vaddr & mask) ^ (bigend << 2);
+ return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
+ }
+ }
+
+ return 0;
+}
+
+/* Simulate the mips16 entry and exit pseudo-instructions. These
+ would normally be handled by the reserved instruction exception
+ code, but for ease of simulation we just handle them directly. */
+
+static void
+mips16_entry (sd,insn)
+ SIM_DESC sd;
+ unsigned int insn;
+{
+ int aregs, sregs, rreg;
+
+#ifdef DEBUG
+ printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
+#endif /* DEBUG */
+
+ aregs = (insn & 0x700) >> 8;
+ sregs = (insn & 0x0c0) >> 6;
+ rreg = (insn & 0x020) >> 5;
+
+ /* This should be checked by the caller. */
+ if (sregs == 3)
+ abort ();
+
+ if (aregs < 5)
+ {
+ int i;
+ t_reg tsp;
+
+ /* This is the entry pseudo-instruction. */
+
+ for (i = 0; i < aregs; i++)
+ store_word ((uword64) (SP + 4 * i), GPR[i + 4]);
+
+ tsp = SP;
+ SP -= 32;
+
+ if (rreg)
+ {
+ tsp -= 4;
+ store_word ((uword64) tsp, RA);
+ }
+
+ for (i = 0; i < sregs; i++)
+ {
+ tsp -= 4;
+ store_word ((uword64) tsp, GPR[16 + i]);
+ }
+ }
+ else
+ {
+ int i;
+ t_reg tsp;
+
+ /* This is the exit pseudo-instruction. */
+
+ tsp = SP + 32;
+
+ if (rreg)
+ {
+ tsp -= 4;
+ RA = load_word ((uword64) tsp);
+ }
+
+ for (i = 0; i < sregs; i++)
+ {
+ tsp -= 4;
+ GPR[i + 16] = load_word ((uword64) tsp);
+ }
+
+ SP += 32;
+
+#if defined(HASFPU)
+ if (aregs == 5)
+ {
+ FGR[0] = WORD64LO (GPR[4]);
+ FPR_STATE[0] = fmt_uninterpreted;
+ }
+ else if (aregs == 6)
+ {
+ FGR[0] = WORD64LO (GPR[5]);
+ FGR[1] = WORD64LO (GPR[4]);
+ FPR_STATE[0] = fmt_uninterpreted;
+ FPR_STATE[1] = fmt_uninterpreted;
+ }
+#endif /* defined(HASFPU) */
+
+ PC = RA;
+ }
}
static unsigned int
}
static long
-getnum(value)
+getnum(sd,value)
+ SIM_DESC sd;
char *value;
{
long num;
num = strtol(value,&end,10);
if (end == value)
- callback->printf_filtered(callback,"Warning: Invalid number \"%s\" ignored, using zero\n",value);
+ sim_io_printf(sd,"Warning: Invalid number \"%s\" ignored, using zero\n",value);
else {
if (*end && ((tolower(*end) == 'k') || (tolower(*end) == 'm'))) {
if (tolower(*end) == 'k')
end++;
}
if (*end)
- callback->printf_filtered(callback,"Warning: Spurious characters \"%s\" at end of number ignored\n",end);
+ sim_io_printf(sd,"Warning: Spurious characters \"%s\" at end of number ignored\n",end);
}
return(num);
to construct an end product, rather than a processor). They
currently have an ARM version of their tool called ChARM. */
+
static
-void dotrace(tracefh,type,address,width,comment)
- FILE *tracefh;
- int type;
- unsigned int address;
- int width;
- char *comment;
+void dotrace(SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
{
- if (state & simTRACE) {
+ if (STATE & simTRACE) {
va_list ap;
- fprintf(tracefh,"%d %08x ; width %d ; ",type,address,width);
+ fprintf(tracefh,"%d %s ; width %d ; ",
+ type,
+ pr_addr(address),
+ width);
va_start(ap,comment);
- fprintf(tracefh,comment,ap);
+ vfprintf(tracefh,comment,ap);
va_end(ap);
fprintf(tracefh,"\n");
}
/*---------------------------------------------------------------------------*/
static void
-ColdReset()
+ColdReset(sd)
+ SIM_DESC sd;
{
/* RESET: Fixed PC address: */
PC = (((uword64)0xFFFFFFFF<<32) | 0xBFC00000);
SR &= ~(status_SR | status_TS | status_RP);
SR |= (status_ERL | status_BEV);
- /* VR4300 starts in Big-Endian mode */
- CONFIG &= ~(config_EP_mask << config_EP_shift);
- CONFIG |= ((config_EP_D << config_EP_shift) | config_BE);
- /* TODO: The VR4300 CONFIG register is not modelled fully at the moment */
#if defined(HASFPU) && (GPRLEN == (64))
/* Cheat and allow access to the complete register set immediately: */
{
int loop;
for (loop = 0; (loop < PSLOTS); loop++)
- pending_slot_reg[loop] = (LAST_EMBED_REGNUM + 1);
- pending_in = pending_out = pending_total = 0;
+ PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1);
+ PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0;
}
#if defined(HASFPU)
{
int rn;
for (rn = 0; (rn < 32); rn++)
- fpr_state[rn] = fmt_uninterpreted;
+ FPR_STATE[rn] = fmt_uninterpreted;
}
#endif /* HASFPU */
along with the exception generation is used to notify whether a
valid address translation occured */
-static int
-AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw)
+int
+address_translation(sd,vAddr,IorD,LorS,pAddr,CCA,host,raw)
+ SIM_DESC sd;
uword64 vAddr;
int IorD;
int LorS;
int res = -1; /* TRUE : Assume good return */
#ifdef DEBUG
- callback->printf_filtered(callback,"AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
+ sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
#endif
/* Check that the address is valid for this memory model */
/* For a simple (flat) memory model, we simply pass virtual
addressess through (mostly) unchanged. */
vAddr &= 0xFFFFFFFF;
+
+ /* Treat the kernel memory spaces identically for the moment: */
+ if ((STATE_MEM_BASE (sd) == K1BASE) && (vAddr >= K0BASE) && (vAddr < (K0BASE + K0SIZE)))
+ vAddr += (K1BASE - K0BASE);
+
+ /* Also assume that the K1BASE memory wraps. This is required to
+ allow the PMON run-time __sizemem() routine to function (without
+ having to provide exception simulation). NOTE: A kludge to work
+ around the fact that the monitor memory is currently held in the
+ K1BASE space. */
+ if (((vAddr < monitor_base) || (vAddr >= (monitor_base + monitor_size))) && (vAddr >= K1BASE && vAddr < (K1BASE + K1SIZE)))
+ vAddr = (K1BASE | (vAddr & (STATE_MEM_SIZE (sd) - 1)));
+
*pAddr = vAddr; /* default for isTARGET */
*CCA = Uncached; /* not used for isHOST */
/* NOTE: This is a duplicate of the code that appears in the
LoadMemory and StoreMemory functions. They should be merged into
a single function (that can be in-lined if required). */
- if ((vAddr >= membank_base) && (vAddr < (membank_base + membank_size))) {
+ if ((vAddr >= STATE_MEM_BASE (sd)) && (vAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) {
if (host)
- *pAddr = (int)&membank[((unsigned int)(vAddr - membank_base) & (membank_size - 1))];
+ *pAddr = (int)&STATE_MEMORY (sd)[((unsigned int)(vAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1))];
} else if ((vAddr >= monitor_base) && (vAddr < (monitor_base + monitor_size))) {
if (host)
*pAddr = (int)&monitor[((unsigned int)(vAddr - monitor_base) & (monitor_size - 1))];
} else {
-#if 1 /* def DEBUG */
- callback->printf_filtered(callback,"Failed: AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"));
+#ifdef DEBUG
+ sim_io_eprintf(sd,"Failed: AddressTranslation(0x%s,%s,%s,...) IPC = 0x%s\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),pr_addr(IPC));
#endif /* DEBUG */
res = 0; /* AddressTranslation has failed */
- *pAddr = -1;
+ *pAddr = (SIM_ADDR)-1;
if (!raw) /* only generate exceptions on real memory transfers */
- SignalException((LorS == isSTORE) ? AddressStore : AddressLoad);
+ if (LorS == isSTORE)
+ SignalExceptionAddressStore ();
+ else
+ SignalExceptionAddressLoad ();
+#ifdef DEBUG
else
- callback->printf_filtered(callback,"AddressTranslation for %s %s from 0x%08X%08X failed\n",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),WORD64HI(vAddr),WORD64LO(vAddr));
+ /* This is a normal occurance during gdb operation, for instance trying
+ to print parameters at function start before they have been setup,
+ and hence we should not print a warning except when debugging the
+ simulator. */
+ sim_io_eprintf(sd,"AddressTranslation for %s %s from 0x%s failed\n",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),pr_addr(vAddr));
+#endif
}
return(res);
which an implementation specific action is taken. The action taken
may increase performance, but must not change the meaning of the
program, or alter architecturally-visible state. */
-static void
+
+static void UNUSED
Prefetch(CCA,pAddr,vAddr,DATA,hint)
int CCA;
uword64 pAddr;
int hint;
{
#ifdef DEBUG
- callback->printf_filtered(callback,"Prefetch(%d,0x%08X%08X,0x%08X%08X,%d,%d);\n",CCA,WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),DATA,hint);
+ sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
#endif /* DEBUG */
/* For our simple memory model we do nothing */
alignment block of memory is read and loaded into the cache to
satisfy a load reference. At a minimum, the block is the entire
memory element. */
-static uword64
-LoadMemory(CCA,AccessLength,pAddr,vAddr,IorD,raw)
+void
+load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw)
+ SIM_DESC sd;
+ uword64* memvalp;
+ uword64* memval1p;
int CCA;
int AccessLength;
uword64 pAddr;
int IorD;
int raw;
{
- uword64 value;
+ uword64 value = 0;
+ uword64 value1 = 0;
#ifdef DEBUG
- if (membank == NULL)
- callback->printf_filtered(callback,"DBG: LoadMemory(%d,%d,0x%08X%08X,0x%08X%08X,%s,%s)\n",CCA,AccessLength,WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(raw ? "isRAW" : "isREAL"));
+ if (STATE_MEMORY (sd) == NULL)
+ sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(raw ? "isRAW" : "isREAL"));
#endif /* DEBUG */
#if defined(WARN_MEM)
if (CCA != uncached)
- callback->printf_filtered(callback,"SIM Warning: LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
+ sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) {
/* In reality this should be a Bus Error */
- sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength,WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
}
#endif /* WARN_MEM */
/* If instruction fetch then we need to check that the two lo-order
bits are zero, otherwise raise a InstructionFetch exception: */
- if ((IorD == isINSTRUCTION) && ((pAddr & 0x3) != 0))
- SignalException(InstructionFetch);
+ if ((IorD == isINSTRUCTION)
+ && ((pAddr & 0x3) != 0)
+ && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
+ SignalExceptionInstructionFetch ();
else {
- unsigned int index;
+ unsigned int index = 0;
unsigned char *mem = NULL;
#if defined(TRACE)
if (!raw)
- dotrace(tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
+ dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
#endif /* TRACE */
/* NOTE: Quicker methods of decoding the address space can be used
when a real memory map is being simulated (i.e. using hi-order
address bits to select device). */
- if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) {
- index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1));
- mem = membank;
+ if ((pAddr >= STATE_MEM_BASE (sd)) && (pAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) {
+ index = ((unsigned int)(pAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1));
+ mem = STATE_MEMORY (sd);
} else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) {
index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1));
mem = monitor;
}
if (mem == NULL)
- sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_io_error(sd,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr));
else {
/* If we obtained the endianness of the host, and it is the same
as the target memory system we can optimise the memory
accesses. However, without that information we must perform
slow transfer, and hope that the compiler optimisation will
merge successive loads. */
- value = 0; /* no data loaded yet */
/* In reality we should always be loading a doubleword value (or
word value in 32bit memory worlds). The external code then
slots. */
if (BigEndianMem)
switch (AccessLength) { /* big-endian memory */
+ case AccessLength_QUADWORD :
+ value1 |= ((uword64)mem[index++] << 56);
+ case 14: /* AccessLength is one less than datalen */
+ value1 |= ((uword64)mem[index++] << 48);
+ case 13:
+ value1 |= ((uword64)mem[index++] << 40);
+ case 12:
+ value1 |= ((uword64)mem[index++] << 32);
+ case 11:
+ value1 |= ((unsigned int)mem[index++] << 24);
+ case 10:
+ value1 |= ((unsigned int)mem[index++] << 16);
+ case 9:
+ value1 |= ((unsigned int)mem[index++] << 8);
+ case 8:
+ value1 |= mem[index];
+
case AccessLength_DOUBLEWORD :
value |= ((uword64)mem[index++] << 56);
case AccessLength_SEPTIBYTE :
else {
index += (AccessLength + 1);
switch (AccessLength) { /* little-endian memory */
+ case AccessLength_QUADWORD :
+ value1 |= ((uword64)mem[--index] << 56);
+ case 14: /* AccessLength is one less than datalen */
+ value1 |= ((uword64)mem[--index] << 48);
+ case 13:
+ value1 |= ((uword64)mem[--index] << 40);
+ case 12:
+ value1 |= ((uword64)mem[--index] << 32);
+ case 11:
+ value1 |= ((uword64)mem[--index] << 24);
+ case 10:
+ value1 |= ((uword64)mem[--index] << 16);
+ case 9:
+ value1 |= ((uword64)mem[--index] << 8);
+ case 8:
+ value1 |= ((uword64)mem[--index] << 0);
+
case AccessLength_DOUBLEWORD :
value |= ((uword64)mem[--index] << 56);
case AccessLength_SEPTIBYTE :
}
#ifdef DEBUG
- printf("DBG: LoadMemory() : (offset %d) : value = 0x%08X%08X\n",(int)(pAddr & LOADDRMASK),WORD64HI(value),WORD64LO(value));
+ printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
+ (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
#endif /* DEBUG */
/* TODO: We could try and avoid the shifts when dealing with raw
memory accesses. This would mean updating the LoadMemory and
StoreMemory routines to avoid shifting the data before
returning or using it. */
- if (!raw) { /* do nothing for raw accessess */
- if (BigEndianMem)
- value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
- else /* little-endian only needs to be shifted up to the correct byte offset */
- value <<= ((pAddr & LOADDRMASK) * 8);
+ if (AccessLength <= AccessLength_DOUBLEWORD) {
+ if (!raw) { /* do nothing for raw accessess */
+ if (BigEndianMem)
+ value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
+ else /* little-endian only needs to be shifted up to the correct byte offset */
+ value <<= ((pAddr & LOADDRMASK) * 8);
+ }
}
#ifdef DEBUG
- printf("DBG: LoadMemory() : shifted value = 0x%08X%08X\n",WORD64HI(value),WORD64LO(value));
+ printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
+ pr_uword64(value1),pr_uword64(value));
#endif /* DEBUG */
}
}
- return(value);
+*memvalp = value;
+if (memval1p) *memval1p = value1;
}
-/* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
+
+/* Description from page A-23 of the "MIPS IV Instruction Set" manual
+ (revision 3.1) */
/* Store a value to memory. The specified data is stored into the
physical location pAddr using the memory hierarchy (data caches and
main memory) as specified by the Cache Coherence Algorithm
and the AccessLength field indicates which of the bytes within the
MemElem data should actually be stored; only these bytes in memory
will be changed. */
-static void
-StoreMemory(CCA,AccessLength,MemElem,pAddr,vAddr,raw)
+
+void
+store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
+ SIM_DESC sd;
int CCA;
int AccessLength;
uword64 MemElem;
+ uword64 MemElem1; /* High order 64 bits */
uword64 pAddr;
uword64 vAddr;
int raw;
{
#ifdef DEBUG
- callback->printf_filtered(callback,"DBG: StoreMemory(%d,%d,0x%08X%08X,0x%08X%08X,0x%08X%08X,%s)\n",CCA,AccessLength,WORD64HI(MemElem),WORD64LO(MemElem),WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),(raw ? "isRAW" : "isREAL"));
+ sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s,%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr),(raw ? "isRAW" : "isREAL"));
#endif /* DEBUG */
#if defined(WARN_MEM)
if (CCA != uncached)
- callback->printf_filtered(callback,"SIM Warning: StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
+ sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
- sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength,WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
#endif /* WARN_MEM */
#if defined(TRACE)
if (!raw)
- dotrace(tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
+ dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
#endif /* TRACE */
/* See the comments in the LoadMemory routine about optimising
routine. However, this would slow the simulator down with
run-time conditionals. */
{
- unsigned int index;
+ unsigned int index = 0;
unsigned char *mem = NULL;
- if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) {
- index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1));
- mem = membank;
+ if ((pAddr >= STATE_MEM_BASE (sd)) && (pAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) {
+ index = ((unsigned int)(pAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1));
+ mem = STATE_MEMORY (sd);
} else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) {
index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1));
mem = monitor;
}
if (mem == NULL)
- sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_io_error(sd,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr));
else {
int shift = 0;
#ifdef DEBUG
- printf("DBG: StoreMemory: offset = %d MemElem = 0x%08X%08X\n",(unsigned int)(pAddr & LOADDRMASK),WORD64HI(MemElem),WORD64LO(MemElem));
+ printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
#endif /* DEBUG */
- if (BigEndianMem) {
- if (raw)
- shift = ((7 - AccessLength) * 8);
- else /* real memory access */
- shift = ((pAddr & LOADDRMASK) * 8);
- MemElem <<= shift;
- } else {
- /* no need to shift raw little-endian data */
- if (!raw)
- MemElem >>= ((pAddr & LOADDRMASK) * 8);
+ if (AccessLength <= AccessLength_DOUBLEWORD) {
+ if (BigEndianMem) {
+ if (raw)
+ shift = ((7 - AccessLength) * 8);
+ else /* real memory access */
+ shift = ((pAddr & LOADDRMASK) * 8);
+ MemElem <<= shift;
+ } else {
+ /* no need to shift raw little-endian data */
+ if (!raw)
+ MemElem >>= ((pAddr & LOADDRMASK) * 8);
+ }
}
#ifdef DEBUG
- printf("DBG: StoreMemory: shift = %d MemElem = 0x%08X%08X\n",shift,WORD64HI(MemElem),WORD64LO(MemElem));
+ printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
#endif /* DEBUG */
if (BigEndianMem) {
switch (AccessLength) { /* big-endian memory */
+ case AccessLength_QUADWORD :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 14 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 13 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 12 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 11 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 10 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 9 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 8 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+
case AccessLength_DOUBLEWORD :
mem[index++] = (unsigned char)(MemElem >> 56);
MemElem <<= 8;
} else {
index += (AccessLength + 1);
switch (AccessLength) { /* little-endian memory */
+ case AccessLength_QUADWORD :
+ mem[--index] = (unsigned char)(MemElem1 >> 56);
+ case 14 :
+ mem[--index] = (unsigned char)(MemElem1 >> 48);
+ case 13 :
+ mem[--index] = (unsigned char)(MemElem1 >> 40);
+ case 12 :
+ mem[--index] = (unsigned char)(MemElem1 >> 32);
+ case 11 :
+ mem[--index] = (unsigned char)(MemElem1 >> 24);
+ case 10 :
+ mem[--index] = (unsigned char)(MemElem1 >> 16);
+ case 9 :
+ mem[--index] = (unsigned char)(MemElem1 >> 8);
+ case 8 :
+ mem[--index] = (unsigned char)(MemElem1 >> 0);
+
case AccessLength_DOUBLEWORD :
mem[--index] = (unsigned char)(MemElem >> 56);
case AccessLength_SEPTIBYTE :
return;
}
+
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* Order loads and stores to synchronise shared memory. Perform the
action necessary to make the effects of groups of synchronizable
int stype;
{
#ifdef DEBUG
- callback->printf_filtered(callback,"SyncOperation(%d) : TODO\n",stype);
+ sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
#endif /* DEBUG */
return;
}
/* Signal an exception condition. This will result in an exception
that aborts the instruction. The instruction operation pseudocode
will never see a return from this function call. */
-static void
-SignalException(exception)
- int exception;
+
+void
+signal_exception (SIM_DESC sd, int exception,...)
{
+ int vector;
+
+#ifdef DEBUG
+ sim_io_printf(sd,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC));
+#endif /* DEBUG */
+
/* Ensure that any active atomic read/modify/write operation will fail: */
LLBIT = 0;
switch (exception) {
/* TODO: For testing purposes I have been ignoring TRAPs. In
reality we should either simulate them, or allow the user to
- ignore them at run-time. */
+ ignore them at run-time.
+ Same for SYSCALL */
case Trap :
- callback->printf_filtered(callback,"Ignoring instruction TRAP (PC 0x%08X%08X)\n",WORD64HI(IPC),WORD64LO(IPC));
+ sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(IPC));
+ break;
+
+ case SystemCall :
+ {
+ va_list ap;
+ unsigned int instruction;
+ unsigned int code;
+
+ va_start(ap,exception);
+ instruction = va_arg(ap,unsigned int);
+ va_end(ap);
+
+ code = (instruction >> 6) & 0xFFFFF;
+
+ sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
+ code, pr_addr(IPC));
+ }
break;
+ case DebugBreakPoint :
+ if (! (Debug & Debug_DM))
+ {
+ if (INDELAYSLOT())
+ {
+ CANCELDELAYSLOT();
+
+ Debug |= Debug_DBD; /* signaled from within in delay slot */
+ DEPC = IPC - 4; /* reference the branch instruction */
+ }
+ else
+ {
+ Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
+ DEPC = IPC;
+ }
+
+ Debug |= Debug_DM; /* in debugging mode */
+ Debug |= Debug_DBp; /* raising a DBp exception */
+ PC = 0xBFC00200;
+ sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
+ }
+ break;
+
case ReservedInstruction :
{
va_list ap;
space with suitable instruction values. For systems were
actual trap instructions are used, we would not need to
perform this magic. */
- if ((instruction & ~RSVD_INSTRUCTION_AMASK) == RSVD_INSTRUCTION) {
- sim_monitor(instruction & RSVD_INSTRUCTION_AMASK);
+ if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) {
+ sim_monitor(sd, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
PC = RA; /* simulate the return from the vector entry */
/* NOTE: This assumes that a branch-and-link style
instruction was used to enter the vector (which is the
case with the current IDT monitor). */
- break; /* out of the switch statement */
+ sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
+ }
+ /* Look for the mips16 entry and exit instructions, and
+ simulate a handler for them. */
+ else if ((IPC & 1) != 0
+ && (instruction & 0xf81f) == 0xe809
+ && (instruction & 0x0c0) != 0x0c0) {
+ mips16_entry (instruction);
+ sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
} /* else fall through to normal exception processing */
- callback->printf_filtered(callback,"DBG: ReservedInstruction 0x%08X at IPC = 0x%08X%08X\n",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ sim_io_eprintf(sd,"ReservedInstruction 0x%08X at IPC = 0x%s\n",instruction,pr_addr(IPC));
}
- default:
-#if 1 /* def DEBUG */
- callback->printf_filtered(callback,"DBG: SignalException(%d) IPC = 0x%08X%08X\n",exception,WORD64HI(IPC),WORD64LO(IPC));
+ case BreakPoint:
+#ifdef DEBUG
+ sim_io_printf(sd,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC));
#endif /* DEBUG */
+ /* Keep a copy of the current A0 in-case this is the program exit
+ breakpoint: */
+ {
+ va_list ap;
+ unsigned int instruction;
+ va_start(ap,exception);
+ instruction = va_arg(ap,unsigned int);
+ va_end(ap);
+ /* Check for our special terminating BREAK: */
+ if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
+ }
+ }
+ if (STATE & simDELAYSLOT)
+ PC = IPC - 4; /* reference the branch instruction */
+ else
+ PC = IPC;
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGTRAP);
+
+ default:
/* Store exception code into current exception id variable (used
by exit code): */
/* TODO: If not simulating exceptions then stop the simulator
execution. At the moment we always stop the simulation. */
- state |= (simSTOP | simEXCEPTION);
- CAUSE = (exception << 2);
- if (state & simDELAYSLOT) {
- CAUSE |= cause_BD;
- EPC = (IPC - 4); /* reference the branch instruction */
- } else
- EPC = IPC;
- /* The following is so that the simulator will continue from the
- exception address on breakpoint operations. */
- PC = EPC;
- break;
+
+ /* See figure 5-17 for an outline of the code below */
+ if (! (SR & status_EXL))
+ {
+ CAUSE = (exception << 2);
+ if (STATE & simDELAYSLOT)
+ {
+ STATE &= ~simDELAYSLOT;
+ CAUSE |= cause_BD;
+ EPC = (IPC - 4); /* reference the branch instruction */
+ }
+ else
+ EPC = IPC;
+ /* FIXME: TLB et.al. */
+ vector = 0x180;
+ }
+ else
+ {
+ CAUSE = (exception << 2);
+ vector = 0x180;
+ }
+ SR |= status_EXL;
+ /* Store exception code into current exception id variable (used
+ by exit code): */
+ if (SR & status_BEV)
+ PC = (signed)0xBFC00200 + 0x180;
+ else
+ PC = (signed)0x80000000 + 0x180;
+
+ switch ((CAUSE >> 2) & 0x1F)
+ {
+ case Interrupt:
+ /* Interrupts arrive during event processing, no need to
+ restart */
+ return;
+
+ case TLBModification:
+ case TLBLoad:
+ case TLBStore:
+ case AddressLoad:
+ case AddressStore:
+ case InstructionFetch:
+ case DataReference:
+ /* The following is so that the simulator will continue from the
+ exception address on breakpoint operations. */
+ PC = EPC;
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGBUS);
+
+ case ReservedInstruction:
+ case CoProcessorUnusable:
+ PC = EPC;
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGILL);
+
+ case IntegerOverflow:
+ case FPE:
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGFPE);
+
+ case Trap:
+ case Watch:
+ case SystemCall:
+ PC = EPC;
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGTRAP);
+
+ case BreakPoint:
+ PC = EPC;
+ sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
+ "FATAL: Should not encounter a breakpoint\n");
+
+ default : /* Unknown internal exception */
+ PC = EPC;
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGQUIT);
+
+ }
case SimulatorFault:
{
char *msg;
va_start(ap,exception);
msg = va_arg(ap,char *);
- fprintf(stderr,"FATAL: Simulator error \"%s\"\n",msg);
va_end(ap);
+ sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
+ "FATAL: Simulator error \"%s\"\n",msg);
}
- exit(1);
}
return;
static void
UndefinedResult()
{
- callback->printf_filtered(callback,"UndefinedResult: IPC = 0x%08X%08X\n",WORD64HI(IPC),WORD64LO(IPC));
+ sim_io_eprintf(sd,"UndefinedResult: IPC = 0x%s\n",pr_addr(IPC));
#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
state |= simSTOP;
#endif
}
#endif /* WARN_RESULT */
-static void
-CacheOp(op,pAddr,vAddr,instruction)
+void
+cache_op(sd,op,pAddr,vAddr,instruction)
+ SIM_DESC sd;
int op;
uword64 pAddr;
uword64 vAddr;
unsigned int instruction;
{
+#if 1 /* stop warning message being displayed (we should really just remove the code) */
+ static int icache_warning = 1;
+ static int dcache_warning = 1;
+#else
+ static int icache_warning = 0;
+ static int dcache_warning = 0;
+#endif
+
/* If CP0 is not useable (User or Supervisor mode) and the CP0
enable bit in the Status Register is clear - a coprocessor
unusable exception is taken. */
- callback->printf_filtered(callback,"TODO: Cache availability checking (PC = 0x%08X%08X)\n",WORD64HI(IPC),WORD64LO(IPC));
+#if 0
+ sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC));
+#endif
switch (op & 0x3) {
case 0: /* instruction cache */
case 4: /* Hit Invalidate */
case 5: /* Fill */
case 6: /* Hit Writeback */
- callback->printf_filtered(callback,"SIM Warning: Instruction CACHE operation %d to be coded\n",(op >> 2));
+ if (!icache_warning)
+ {
+ sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
+ icache_warning = 1;
+ }
break;
default:
case 4: /* Hit Invalidate */
case 5: /* Hit Writeback Invalidate */
case 6: /* Hit Writeback */
- callback->printf_filtered(callback,"SIM Warning: Data CACHE operation %d to be coded\n",(op >> 2));
+ if (!dcache_warning)
+ {
+ sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
+ dcache_warning = 1;
+ }
break;
default:
#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
#endif /* DEBUG */
-static uword64
-ValueFPR(fpr,fmt)
- int fpr;
- FP_formats fmt;
+uword64
+value_fpr(sd,fpr,fmt)
+ SIM_DESC sd;
+ int fpr;
+ FP_formats fmt;
{
- uword64 value;
+ uword64 value = 0;
int err = 0;
/* Treat unused register values, as fixed-point 64bit values: */
#if 1
/* If request to read data as "uninterpreted", then use the current
encoding: */
- fmt = fpr_state[fpr];
+ fmt = FPR_STATE[fpr];
#else
fmt = fmt_long;
#endif
/* For values not yet accessed, set to the desired format: */
- if (fpr_state[fpr] == fmt_uninterpreted) {
- fpr_state[fpr] = fmt;
+ if (FPR_STATE[fpr] == fmt_uninterpreted) {
+ FPR_STATE[fpr] = fmt;
#ifdef DEBUG
printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
#endif /* DEBUG */
}
- if (fmt != fpr_state[fpr]) {
- callback->printf_filtered(callback,"Warning: FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%08X%08X)\n",fpr,DOFMT(fpr_state[fpr]),DOFMT(fmt),WORD64HI(IPC),WORD64LO(IPC));
- fpr_state[fpr] = fmt_unknown;
+ if (fmt != FPR_STATE[fpr]) {
+ sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(IPC));
+ FPR_STATE[fpr] = fmt_unknown;
}
- if (fpr_state[fpr] == fmt_unknown) {
+ if (FPR_STATE[fpr] == fmt_unknown) {
/* Set QNaN value: */
switch (fmt) {
case fmt_single:
err = -1;
break;
}
- } else if ((fpr & 1) == 0) { /* even registers only */
+ } else {
switch (fmt) {
case fmt_single:
case fmt_word:
case fmt_uninterpreted:
case fmt_double:
case fmt_long:
- value = ((FGR[fpr+1] << 32) | (FGR[fpr] & 0xFFFFFFFF));
+ if ((fpr & 1) == 0) { /* even registers only */
+ value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
+ } else {
+ SignalException(ReservedInstruction,0);
+ }
break;
default :
}
if (err)
- SignalException(SimulatorFault,"Unrecognised FP format in ValueFPR()");
+ SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
#ifdef DEBUG
- printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr,DOFMT(fmt),WORD64HI(value),WORD64LO(value),WORD64HI(IPC),WORD64LO(IPC),SizeFGR());
+ printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR());
#endif /* DEBUG */
return(value);
}
-static void
-StoreFPR(fpr,fmt,value)
+void
+store_fpr(sd,fpr,fmt,value)
+ SIM_DESC sd;
int fpr;
FP_formats fmt;
uword64 value;
int err = 0;
#ifdef DEBUG
- printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr,DOFMT(fmt),WORD64HI(value),WORD64LO(value),WORD64HI(IPC),WORD64LO(IPC),SizeFGR());
+ printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR());
#endif /* DEBUG */
if (SizeFGR() == 64) {
case fmt_single :
case fmt_word :
FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
- fpr_state[fpr] = fmt;
+ FPR_STATE[fpr] = fmt;
break;
case fmt_uninterpreted:
case fmt_double :
case fmt_long :
FGR[fpr] = value;
- fpr_state[fpr] = fmt;
+ FPR_STATE[fpr] = fmt;
break;
default :
- fpr_state[fpr] = fmt_unknown;
+ FPR_STATE[fpr] = fmt_unknown;
err = -1;
break;
}
- } else if ((fpr & 1) == 0) { /* even register number only */
+ } else {
switch (fmt) {
case fmt_single :
case fmt_word :
- FGR[fpr+1] = 0xDEADC0DE;
FGR[fpr] = (value & 0xFFFFFFFF);
- fpr_state[fpr + 1] = fmt;
- fpr_state[fpr] = fmt;
+ FPR_STATE[fpr] = fmt;
break;
case fmt_uninterpreted:
case fmt_double :
case fmt_long :
- FGR[fpr+1] = (value >> 32);
- FGR[fpr] = (value & 0xFFFFFFFF);
- fpr_state[fpr + 1] = fmt;
- fpr_state[fpr] = fmt;
+ if ((fpr & 1) == 0) { /* even register number only */
+ FGR[fpr+1] = (value >> 32);
+ FGR[fpr] = (value & 0xFFFFFFFF);
+ FPR_STATE[fpr + 1] = fmt;
+ FPR_STATE[fpr] = fmt;
+ } else {
+ FPR_STATE[fpr] = fmt_unknown;
+ FPR_STATE[fpr + 1] = fmt_unknown;
+ SignalException(ReservedInstruction,0);
+ }
break;
default :
- fpr_state[fpr] = fmt_unknown;
+ FPR_STATE[fpr] = fmt_unknown;
err = -1;
break;
}
#endif /* WARN_RESULT */
if (err)
- SignalException(SimulatorFault,"Unrecognised FP format in StoreFPR()");
+ SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
#ifdef DEBUG
- printf("DBG: StoreFPR: fpr[%d] = 0x%08X%08X (format %s)\n",fpr,WORD64HI(FGR[fpr]),WORD64LO(FGR[fpr]),DOFMT(fmt));
+ printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
#endif /* DEBUG */
return;
}
-static int
+int
NaN(op,fmt)
uword64 op;
FP_formats fmt;
case fmt_long:
boolean = (op == FPQNaN_LONG);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
-printf("DBG: NaN: returning %d for 0x%08X%08X (format = %s)\n",boolean,WORD64HI(op),WORD64LO(op),DOFMT(fmt));
+printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
#endif /* DEBUG */
return(boolean);
}
-static int
+int
Infinity(op,fmt)
uword64 op;
FP_formats fmt;
int boolean = 0;
#ifdef DEBUG
- printf("DBG: Infinity: format %s 0x%08X%08X (PC = 0x%08X%08X)\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op),WORD64HI(IPC),WORD64LO(IPC));
+ printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt),pr_addr(op),pr_addr(IPC));
#endif /* DEBUG */
/* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
}
#ifdef DEBUG
- printf("DBG: Infinity: returning %d for 0x%08X%08X (format = %s)\n",boolean,WORD64HI(op),WORD64LO(op),DOFMT(fmt));
+ printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
#endif /* DEBUG */
return(boolean);
}
-static int
+int
Less(op1,op2,fmt)
uword64 op1;
uword64 op2;
/* Argument checking already performed by the FPCOMPARE code */
#ifdef DEBUG
- printf("DBG: Less: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The format type should already have been checked: */
case fmt_double:
boolean = (*(double *)&op1 < *(double *)&op2);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
return(boolean);
}
-static int
+int
Equal(op1,op2,fmt)
uword64 op1;
uword64 op2;
/* Argument checking already performed by the FPCOMPARE code */
#ifdef DEBUG
- printf("DBG: Equal: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The format type should already have been checked: */
case fmt_double:
boolean = (op1 == op2);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
return(boolean);
}
-static uword64
+uword64
+AbsoluteValue(op,fmt)
+ uword64 op;
+ FP_formats fmt;
+{
+ uword64 result = 0;
+
+#ifdef DEBUG
+ printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
+#endif /* DEBUG */
+
+ /* The format type should already have been checked: */
+ switch (fmt) {
+ case fmt_single:
+ {
+ unsigned int wop = (unsigned int)op;
+ float tmp = ((float)fabs((double)*(float *)&wop));
+ result = (uword64)*(unsigned int *)&tmp;
+ }
+ break;
+ case fmt_double:
+ {
+ double tmp = (fabs(*(double *)&op));
+ result = *(uword64 *)&tmp;
+ }
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
+ }
+
+ return(result);
+}
+
+uword64
Negate(op,fmt)
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Negate: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The format type should already have been checked: */
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
return(result);
}
-static uword64
+uword64
Add(op1,op2,fmt)
uword64 op1;
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Add: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Add: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64
Sub(op1,op2,fmt)
uword64 op1;
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Sub: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64H(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Sub: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64
Multiply(op1,op2,fmt)
uword64 op1;
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Multiply: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Multiply: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64
Divide(op1,op2,fmt)
uword64 op1;
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Divide: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Divide: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64 UNUSED
Recip(op,fmt)
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Recip: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Recip: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64
SquareRoot(op,fmt)
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: SquareRoot: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
case fmt_single:
{
unsigned int wop = (unsigned int)op;
+#ifdef HAVE_SQRT
float tmp = ((float)sqrt((double)*(float *)&wop));
result = (uword64)*(unsigned int *)&tmp;
+#else
+ /* TODO: Provide square-root */
+ result = (uword64)0;
+#endif
}
break;
case fmt_double:
{
+#ifdef HAVE_SQRT
double tmp = (sqrt(*(double *)&op));
result = *(uword64 *)&tmp;
+#else
+ /* TODO: Provide square-root */
+ result = (uword64)0;
+#endif
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: SquareRoot: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
-Convert(rm,op,from,to)
+uword64
+convert(sd,rm,op,from,to)
+ SIM_DESC sd;
int rm;
uword64 op;
FP_formats from;
FP_formats to;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Convert: mode %s : op 0x%08X%08X : from %s : to %s : (PC = 0x%08X%08X)\n",RMMODE(rm),WORD64HI(op),WORD64LO(op),DOFMT(from),DOFMT(to),WORD64HI(IPC),WORD64LO(IPC));
+ printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
#endif /* DEBUG */
/* The value "op" is converted to the destination format, rounding
break;
case fmt_long:
- tmp = (float)((int)op);
+ tmp = (float)((word64)op);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
+#if 0
+ /* FIXME: This code is incorrect. The rounding mode does not
+ round to integral values; it rounds to the nearest
+ representable value in the format. */
+
switch (rm) {
case FP_RM_NEAREST:
/* Round result to nearest representable value. When two
representable values are equally near, round to the value
that has a least significant bit of zero (i.e. is even). */
-#if defined(sun)
+#ifdef HAVE_ANINT
tmp = (float)anint((double)tmp);
#else
/* TODO: Provide round-to-nearest */
case FP_RM_TOZERO:
/* Round result to the value closest to, and not greater in
magnitude than, the result. */
-#if defined(sun)
+#ifdef HAVE_AINT
tmp = (float)aint((double)tmp);
#else
/* TODO: Provide round-to-zero */
tmp = (float)floor((double)tmp);
break;
}
+#endif /* 0 */
+
result = (uword64)*(unsigned int *)&tmp;
}
break;
case fmt_double:
{
double tmp;
+ word64 xxx;
switch (from) {
case fmt_single:
break;
case fmt_word:
- tmp = (double)((word64)SIGNEXTEND((op & 0xFFFFFFFF),32));
+ xxx = SIGNEXTEND((op & 0xFFFFFFFF),32);
+ tmp = (double)xxx;
break;
case fmt_long:
tmp = (double)((word64)op);
break;
+
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
+#if 0
+ /* FIXME: This code is incorrect. The rounding mode does not
+ round to integral values; it rounds to the nearest
+ representable value in the format. */
+
switch (rm) {
case FP_RM_NEAREST:
-#if defined(sun)
+#ifdef HAVE_ANINT
tmp = anint(*(double *)&tmp);
#else
/* TODO: Provide round-to-nearest */
break;
case FP_RM_TOZERO:
-#if defined(sun)
+#ifdef HAVE_AINT
tmp = aint(*(double *)&tmp);
#else
/* TODO: Provide round-to-zero */
tmp = floor(*(double *)&tmp);
break;
}
+#endif /* 0 */
+
result = *(uword64 *)&tmp;
}
break;
case fmt_long:
if (Infinity(op,from) || NaN(op,from) || (1 == 0/*TODO: check range */)) {
printf("DBG: TODO: update FCSR\n");
- SignalException(FPE);
+ SignalExceptionFPE ();
} else {
if (to == fmt_word) {
- unsigned int tmp;
+ int tmp = 0;
switch (from) {
case fmt_single:
{
unsigned int wop = (unsigned int)op;
- tmp = (unsigned int)*((float *)&wop);
+ tmp = (int)*((float *)&wop);
}
break;
case fmt_double:
- tmp = (unsigned int)*((double *)&op);
+ tmp = (int)*((double *)&op);
#ifdef DEBUG
- printf("DBG: from double %.30f (0x%08X%08X) to word: 0x%08X\n",*((double *)&op),WORD64HI(op),WORD64LO(op),tmp);
+ printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op),pr_addr(op),tmp);
#endif /* DEBUG */
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
result = (uword64)tmp;
} else { /* fmt_long */
+ word64 tmp = 0;
switch (from) {
case fmt_single:
{
unsigned int wop = (unsigned int)op;
- result = (uword64)*((float *)&wop);
+ tmp = (word64)*((float *)&wop);
}
break;
case fmt_double:
- result = (uword64)*((double *)&op);
+ tmp = (word64)*((double *)&op);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
+ result = (uword64)tmp;
}
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Convert: returning 0x%08X%08X (to format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(to));
+ printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result),DOFMT(to));
#endif /* DEBUG */
return(result);
/*-- co-processor support routines ------------------------------------------*/
-static int
+static int UNUSED
CoProcPresent(coproc_number)
unsigned int coproc_number;
{
return(0);
}
-static void
-COP_LW(coproc_num,coproc_reg,memword)
+void
+cop_lw(sd,coproc_num,coproc_reg,memword)
+ SIM_DESC sd;
int coproc_num, coproc_reg;
unsigned int memword;
{
#if defined(HASFPU)
case 1:
#ifdef DEBUG
- printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%08X%08X\n",memword,WORD64HI(memword),WORD64LO(memword));
+ printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
#endif
- StoreFPR(coproc_reg,fmt_uninterpreted,(uword64)memword);
+ StoreFPR(coproc_reg,fmt_word,(uword64)memword);
+ FPR_STATE[coproc_reg] = fmt_uninterpreted;
break;
#endif /* HASFPU */
default:
- callback->printf_filtered(callback,"COP_LW(%d,%d,0x%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,WORD64HI(IPC),WORD64LO(IPC));
+#if 0 /* this should be controlled by a configuration option */
+ sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(IPC));
+#endif
break;
}
return;
}
-static void
-COP_LD(coproc_num,coproc_reg,memword)
+void
+cop_ld(sd,coproc_num,coproc_reg,memword)
+ SIM_DESC sd;
int coproc_num, coproc_reg;
uword64 memword;
{
#endif /* HASFPU */
default:
- callback->printf_filtered(callback,"COP_LD(%d,%d,0x%08X%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(memword),WORD64LO(memword),WORD64HI(IPC),WORD64LO(IPC));
+#if 0 /* this message should be controlled by a configuration option */
+ sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(IPC));
+#endif
break;
}
return;
}
-static unsigned int
-COP_SW(coproc_num,coproc_reg)
+unsigned int
+cop_sw(sd,coproc_num,coproc_reg)
+ SIM_DESC sd;
int coproc_num, coproc_reg;
{
unsigned int value = 0;
+
switch (coproc_num) {
#if defined(HASFPU)
case 1:
#if 1
- value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
+ {
+ FP_formats hold;
+ hold = FPR_STATE[coproc_reg];
+ FPR_STATE[coproc_reg] = fmt_word;
+ value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
+ FPR_STATE[coproc_reg] = hold;
+ }
#else
#if 1
- value = (unsigned int)ValueFPR(coproc_reg,fpr_state[coproc_reg]);
+ value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
#else
#ifdef DEBUG
- printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(fpr_state[coproc_reg]));
+ printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg]));
#endif /* DEBUG */
value = (unsigned int)ValueFPR(coproc_reg,fmt_single);
#endif
#endif /* HASFPU */
default:
- callback->printf_filtered(callback,"COP_SW(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC));
+#if 0 /* should be controlled by configuration option */
+ sim_io_printf(sd,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC));
+#endif
break;
}
return(value);
}
-static uword64
-COP_SD(coproc_num,coproc_reg)
+uword64
+cop_sd(sd,coproc_num,coproc_reg)
+ SIM_DESC sd;
int coproc_num, coproc_reg;
{
uword64 value = 0;
value = ValueFPR(coproc_reg,fmt_uninterpreted);
#else
#if 1
- value = ValueFPR(coproc_reg,fpr_state[coproc_reg]);
+ value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
#else
#ifdef DEBUG
- printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(fpr_state[coproc_reg]));
+ printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg]));
#endif /* DEBUG */
value = ValueFPR(coproc_reg,fmt_double);
#endif
#endif /* HASFPU */
default:
- callback->printf_filtered(callback,"COP_SD(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC));
+#if 0 /* should be controlled by configuration option */
+ sim_io_printf(sd,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC));
+#endif
break;
}
}
static void
-decode_coproc(instruction)
+decode_coproc(sd,instruction)
+ SIM_DESC sd;
unsigned int instruction;
{
int coprocnum = ((instruction >> 26) & 3);
- switch (coprocnum) {
+ switch (coprocnum)
+ {
case 0: /* standard CPU control and cache registers */
{
- /* NOTEs:
- Standard CP0 registers
- 0 = Index R4000 VR4100 VR4300
- 1 = Random R4000 VR4100 VR4300
- 2 = EntryLo0 R4000 VR4100 VR4300
- 3 = EntryLo1 R4000 VR4100 VR4300
- 4 = Context R4000 VR4100 VR4300
- 5 = PageMask R4000 VR4100 VR4300
- 6 = Wired R4000 VR4100 VR4300
- 8 = BadVAddr R4000 VR4100 VR4300
- 9 = Count R4000 VR4100 VR4300
- 10 = EntryHi R4000 VR4100 VR4300
- 11 = Compare R4000 VR4100 VR4300
- 12 = SR R4000 VR4100 VR4300
- 13 = Cause R4000 VR4100 VR4300
- 14 = EPC R4000 VR4100 VR4300
- 15 = PRId R4000 VR4100 VR4300
- 16 = Config R4000 VR4100 VR4300
- 17 = LLAddr R4000 VR4100 VR4300
- 18 = WatchLo R4000 VR4100 VR4300
- 19 = WatchHi R4000 VR4100 VR4300
- 20 = XContext R4000 VR4100 VR4300
- 26 = PErr or ECC R4000 VR4100 VR4300
- 27 = CacheErr R4000 VR4100
- 28 = TagLo R4000 VR4100 VR4300
- 29 = TagHi R4000 VR4100 VR4300
- 30 = ErrorEPC R4000 VR4100 VR4300
- */
int code = ((instruction >> 21) & 0x1F);
/* R4000 Users Manual (second edition) lists the following CP0
instructions:
- DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
- DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
- MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
- MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
- TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
- TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
- TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
- TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
- CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
- ERET Exception return (VR4100 = 01000010000000000000000000011000)
- */
- if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) {
- int rt = ((instruction >> 16) & 0x1F);
- int rd = ((instruction >> 11) & 0x1F);
- if (code == 0x00) { /* MF : move from */
- callback->printf_filtered(callback,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
- GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
- } else { /* MT : move to */
- /* CPR[0,rd] = GPR[rt]; */
- callback->printf_filtered(callback,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
+ DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
+ DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
+ MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
+ MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
+ TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
+ TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
+ TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
+ TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
+ CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
+ ERET Exception return (VR4100 = 01000010000000000000000000011000)
+ */
+ if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
+ {
+ int rt = ((instruction >> 16) & 0x1F);
+ int rd = ((instruction >> 11) & 0x1F);
+
+ switch (rd) /* NOTEs: Standard CP0 registers */
+ {
+ /* 0 = Index R4000 VR4100 VR4300 */
+ /* 1 = Random R4000 VR4100 VR4300 */
+ /* 2 = EntryLo0 R4000 VR4100 VR4300 */
+ /* 3 = EntryLo1 R4000 VR4100 VR4300 */
+ /* 4 = Context R4000 VR4100 VR4300 */
+ /* 5 = PageMask R4000 VR4100 VR4300 */
+ /* 6 = Wired R4000 VR4100 VR4300 */
+ /* 8 = BadVAddr R4000 VR4100 VR4300 */
+ /* 9 = Count R4000 VR4100 VR4300 */
+ /* 10 = EntryHi R4000 VR4100 VR4300 */
+ /* 11 = Compare R4000 VR4100 VR4300 */
+ /* 12 = SR R4000 VR4100 VR4300 */
+ case 12:
+ if (code == 0x00)
+ GPR[rt] = SR;
+ else
+ SR = GPR[rt];
+ break;
+ /* 13 = Cause R4000 VR4100 VR4300 */
+ case 13:
+ if (code == 0x00)
+ GPR[rt] = CAUSE;
+ else
+ CAUSE = GPR[rt];
+ break;
+ /* 14 = EPC R4000 VR4100 VR4300 */
+ /* 15 = PRId R4000 VR4100 VR4300 */
+#ifdef SUBTARGET_R3900
+ /* 16 = Debug */
+ case 16:
+ if (code == 0x00)
+ GPR[rt] = Debug;
+ else
+ Debug = GPR[rt];
+ break;
+#else
+ /* 16 = Config R4000 VR4100 VR4300 */
+#endif
+#ifdef SUBTARGET_R3900
+ /* 17 = Debug */
+ case 17:
+ if (code == 0x00)
+ GPR[rt] = DEPC;
+ else
+ DEPC = GPR[rt];
+ break;
+#else
+ /* 17 = LLAddr R4000 VR4100 VR4300 */
+#endif
+ /* 18 = WatchLo R4000 VR4100 VR4300 */
+ /* 19 = WatchHi R4000 VR4100 VR4300 */
+ /* 20 = XContext R4000 VR4100 VR4300 */
+ /* 26 = PErr or ECC R4000 VR4100 VR4300 */
+ /* 27 = CacheErr R4000 VR4100 */
+ /* 28 = TagLo R4000 VR4100 VR4300 */
+ /* 29 = TagHi R4000 VR4100 VR4300 */
+ /* 30 = ErrorEPC R4000 VR4100 VR4300 */
+ GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
+ /* CPR[0,rd] = GPR[rt]; */
+ default:
+ if (code == 0x00)
+ sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
+ else
+ sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
+ }
+ }
+ else if (code == 0x10 && (instruction & 0x3f) == 0x18)
+ {
+ /* ERET */
+ if (SR & status_ERL)
+ {
+ /* Oops, not yet available */
+ sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
+ PC = EPC;
+ SR &= ~status_ERL;
+ }
+ else
+ {
+ PC = EPC;
+ SR &= ~status_EXL;
+ }
+ }
+ else if (code == 0x10 && (instruction & 0x3f) == 0x10)
+ {
+ /* RFE */
}
- } else
- callback->printf_filtered(callback,"Warning: Unrecognised COP0 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
+ {
+ /* DERET */
+ Debug &= ~Debug_DM;
+ DELAYSLOT();
+ DSPC = DEPC;
+ }
+ else
+ sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction,pr_addr(IPC));
/* TODO: When executing an ERET or RFE instruction we should
clear LLBIT, to ensure that any out-standing atomic
read/modify/write sequence fails. */
}
- break;
-
+ break;
+
case 2: /* undefined co-processor */
- callback->printf_filtered(callback,"Warning: COP2 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ sim_io_eprintf(sd,"COP2 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction,pr_addr(IPC));
break;
-
+
case 1: /* should not occur (FPU co-processor) */
case 3: /* should not occur (FPU co-processor) */
SignalException(ReservedInstruction,instruction);
break;
- }
-
+ }
+
return;
}
/*-- instruction simulation -------------------------------------------------*/
-static void
-simulate ()
+void
+sim_engine_run (sd, next_cpu_nr, siggnal)
+ SIM_DESC sd;
+ int next_cpu_nr; /* ignore */
+ int siggnal; /* ignore */
{
+#if !defined(FASTSIM)
unsigned int pipeline_count = 1;
+#endif
#ifdef DEBUG
- if (membank == NULL) {
+ if (STATE_MEMORY (sd) == NULL) {
printf("DBG: simulate() entered with no memory\n");
exit(1);
}
#endif
/* main controlling loop */
- do {
+ while (1) {
/* Fetch the next instruction from the simulator memory: */
uword64 vaddr = (uword64)PC;
uword64 paddr;
int cca;
- unsigned int instruction;
- int dsstate = (state & simDELAYSLOT);
+ unsigned int instruction; /* uword64? what's this used for? FIXME! */
#ifdef DEBUG
{
printf("DBG: state = 0x%08X :",state);
+#if 0
if (state & simSTOP) printf(" simSTOP");
if (state & simSTEP) printf(" simSTEP");
+#endif
if (state & simHALTEX) printf(" simHALTEX");
if (state & simHALTIN) printf(" simHALTIN");
+#if 0
if (state & simBE) printf(" simBE");
+#endif
+ printf("\n");
}
#endif /* DEBUG */
+ DSSTATE = (STATE & simDELAYSLOT);
#ifdef DEBUG
if (dsstate)
- callback->printf_filtered(callback,"DBG: DSPC = 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
+ sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
#endif /* DEBUG */
- if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { /* Copy the action of the LW instruction */
- unsigned int reverse = (ReverseEndian ? 1 : 0);
- unsigned int bigend = (BigEndianCPU ? 1 : 0);
- uword64 value;
- unsigned int byte;
- paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 2)));
- value = LoadMemory(cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
- byte = ((vaddr & 0x7) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
+ if ((vaddr & 1) == 0) {
+ /* Copy the action of the LW instruction */
+ unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
+ unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
+ uword64 value;
+ unsigned int byte;
+ paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
+ LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
+ byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
+ instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ } else {
+ /* Copy the action of the LH instruction */
+ unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
+ unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
+ uword64 value;
+ unsigned int byte;
+ paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
+ | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
+ LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
+ paddr & ~ (uword64) 1,
+ vaddr, isINSTRUCTION, isREAL);
+ byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
+ instruction = ((value >> (8 * byte)) & 0xFFFF);
+ }
} else {
- fprintf(stderr,"Cannot translate address for PC = 0x%08X%08X failed\n",WORD64HI(PC),WORD64LO(PC));
+ fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
exit(1);
}
#ifdef DEBUG
- callback->printf_filtered(callback,"DBG: fetched 0x%08X from PC = 0x%08X%08X\n",instruction,WORD64HI(PC),WORD64LO(PC));
+ sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
#endif /* DEBUG */
#if !defined(FASTSIM) || defined(PROFILE)
instruction_fetches++;
+ /* Since we increment above, the value should only ever be zero if
+ we have just overflowed: */
+ if (instruction_fetches == 0)
+ instruction_fetch_overflow++;
#if defined(PROFILE)
- if ((state & simPROFILE) && ((instruction_fetches % profile_frequency) == 0) && profile_hist) {
- int n = ((unsigned int)(PC - profile_minpc) >> (profile_shift + 2));
+ if ((STATE & simPROFILE) && ((instruction_fetches % profile_frequency) == 0) && profile_hist) {
+ unsigned n = ((unsigned int)(PC - profile_minpc) >> (profile_shift + 2));
if (n < profile_nsamples) {
/* NOTE: The counts for the profiling bins are only 16bits wide */
if (profile_hist[n] != USHRT_MAX)
/* This is required by exception processing, to ensure that we can
cope with exceptions in the delay slots of branches that may
already have changed the PC. */
- PC += 4; /* increment ready for the next fetch */
+ if ((vaddr & 1) == 0)
+ PC += 4; /* increment ready for the next fetch */
+ else
+ PC += 2;
/* NOTE: If we perform a delay slot change to the PC, this
increment is not requuired. However, it would make the
simulator more complicated to try and avoid this small hit. */
treated as using a single cycle. NOTE: A standard system is not
provided by the default simulator because different MIPS
architectures have different cycle counts for the same
- instructions. */
+ instructions.
+
+ [NOTE: pipeline_count has been replaced the event queue] */
#if defined(HASFPU)
/* Set previous flag, depending on current: */
- if (state & simPCOC0)
- state |= simPCOC1;
+ if (STATE & simPCOC0)
+ STATE |= simPCOC1;
else
- state &= ~simPCOC1;
+ STATE &= ~simPCOC1;
/* and update the current value: */
if (GETFCC(0))
- state |= simPCOC0;
+ STATE |= simPCOC0;
else
- state &= ~simPCOC0;
+ STATE &= ~simPCOC0;
#endif /* HASFPU */
/* NOTE: For multi-context simulation environments the "instruction"
variables (and a single-threaded simulator engine), then we can
create the actual variables with these names. */
- if (!(state & simSKIPNEXT)) {
+ if (!(STATE & simSKIPNEXT)) {
/* Include the simulator engine */
#include "engine.c"
-#if ((GPRLEN == 64) && !defined(PROCESSOR_64BIT)) || ((GPRLEN == 32) && defined(PROCESSOR_64BIT))
+#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
#error "Mismatch between run-time simulator code and simulation engine"
#endif
+#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
+#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
+#endif
+#if (WITH_FLOATING_POINT == HARD_FLOATING_POINT != defined (HASFPU))
+#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
+#endif
#if defined(WARN_LOHI)
/* Decrement the HI/LO validity ticks */
HIACCESS--;
if (LOACCESS > 0)
LOACCESS--;
+ if (HI1ACCESS > 0)
+ HI1ACCESS--;
+ if (LO1ACCESS > 0)
+ LO1ACCESS--;
#endif /* WARN_LOHI */
-#if defined(WARN_ZERO)
/* For certain MIPS architectures, GPR[0] is hardwired to zero. We
should check for it being changed. It is better doing it here,
than within the simulator, since it will help keep the simulator
small. */
if (ZERO != 0) {
- callback->printf_filtered(callback,"SIM Warning: The ZERO register has been updated with 0x%08X%08X (PC = 0x%08X%08X)\nSIM Warning: Resetting back to zero\n",WORD64HI(ZERO),WORD64LO(ZERO),WORD64HI(IPC),WORD64LO(IPC));
+#if defined(WARN_ZERO)
+ sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(IPC));
+#endif /* WARN_ZERO */
ZERO = 0; /* reset back to zero before next instruction */
}
-#endif /* WARN_ZERO */
} else /* simSKIPNEXT check */
- state &= ~simSKIPNEXT;
+ STATE &= ~simSKIPNEXT;
/* If the delay slot was active before the instruction is
executed, then update the PC to its new value: */
- if (dsstate) {
+ if (DSSTATE) {
#ifdef DEBUG
- printf("DBG: dsstate set before instruction execution - updating PC to 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
+ printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
#endif /* DEBUG */
PC = DSPC;
- state &= ~simDELAYSLOT;
+ CANCELDELAYSLOT();
}
if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
#ifdef DEBUG
printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
#endif /* DEBUG */
- if (pending_out != pending_in) {
+ if (PENDING_OUT != PENDING_IN) {
int loop;
- int index = pending_out;
- int total = pending_total;
- if (pending_total == 0) {
+ int index = PENDING_OUT;
+ int total = PENDING_TOTAL;
+ if (PENDING_TOTAL == 0) {
fprintf(stderr,"FATAL: Mis-match on pending update pointers\n");
exit(1);
}
#ifdef DEBUG
printf("DBG: BEFORE index = %d, loop = %d\n",index,loop);
#endif /* DEBUG */
- if (pending_slot_reg[index] != (LAST_EMBED_REGNUM + 1)) {
+ if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) {
#ifdef DEBUG
- printf("pending_slot_count[%d] = %d\n",index,pending_slot_count[index]);
+ printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]);
#endif /* DEBUG */
- if (--(pending_slot_count[index]) == 0) {
+ if (--(PENDING_SLOT_COUNT[index]) == 0) {
#ifdef DEBUG
- printf("pending_slot_reg[%d] = %d\n",index,pending_slot_reg[index]);
- printf("pending_slot_value[%d] = 0x%08X%08X\n",index,WORD64HI(pending_slot_value[index]),WORD64LO(pending_slot_value[index]));
+ printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]);
+ printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index]));
#endif /* DEBUG */
- if (pending_slot_reg[index] == COCIDX) {
+ if (PENDING_SLOT_REG[index] == COCIDX) {
+#if defined(HASFPU)
SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
+#else
+ ;
+#endif
} else {
- registers[pending_slot_reg[index]] = pending_slot_value[index];
+ REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
#if defined(HASFPU)
/* The only time we have PENDING updates to FPU
registers, is when performing binary transfers. This
means we should update the register type field. */
- if ((pending_slot_reg[index] >= FGRIDX) && (pending_slot_reg[index] < (FGRIDX + 32)))
- fpr_state[pending_slot_reg[index]] = fmt_uninterpreted;
+ if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
+ FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
#endif /* HASFPU */
}
#ifdef DEBUG
- printf("registers[%d] = 0x%08X%08X\n",pending_slot_reg[index],WORD64HI(registers[pending_slot_reg[index]]),WORD64LO(registers[pending_slot_reg[index]]));
+ printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]]));
#endif /* DEBUG */
- pending_slot_reg[index] = (LAST_EMBED_REGNUM + 1);
- pending_out++;
- if (pending_out == PSLOTS)
- pending_out = 0;
- pending_total--;
+ PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1);
+ PENDING_OUT++;
+ if (PENDING_OUT == PSLOTS)
+ PENDING_OUT = 0;
+ PENDING_TOTAL--;
}
}
#ifdef DEBUG
}
}
#ifdef DEBUG
- printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
+ printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);
#endif /* DEBUG */
}
#if !defined(FASTSIM)
- pipeline_ticks += pipeline_count;
+ if (sim_events_tickn (sd, pipeline_count))
+ {
+ /* cpu->cia = cia; */
+ sim_events_process (sd);
+ }
+#else
+ if (sim_events_tick (sd))
+ {
+ /* cpu->cia = cia; */
+ sim_events_process (sd);
+ }
#endif /* FASTSIM */
+ }
+}
- if (state & simSTEP)
- state |= simSTOP;
- } while (!(state & simSTOP));
+/* This code copied from gdb's utils.c. Would like to share this code,
+ but don't know of a common place where both could get to it. */
-#ifdef DEBUG
- if (membank == NULL) {
- printf("DBG: simulate() LEAVING with no memory\n");
- exit(1);
- }
-#endif /* DEBUG */
+/* Temporary storage using circular buffer */
+#define NUMCELLS 16
+#define CELLSIZE 32
+static char*
+get_cell()
+{
+ static char buf[NUMCELLS][CELLSIZE];
+ static int cell=0;
+ if (++cell>=NUMCELLS) cell=0;
+ return buf[cell];
+}
- return;
+/* Print routines to handle variable size regs, etc */
+
+/* Eliminate warning from compiler on 32-bit systems */
+static int thirty_two = 32;
+
+char*
+pr_addr(addr)
+ SIM_ADDR addr;
+{
+ char *paddr_str=get_cell();
+ switch (sizeof(addr))
+ {
+ case 8:
+ sprintf(paddr_str,"%08lx%08lx",
+ (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
+ break;
+ case 4:
+ sprintf(paddr_str,"%08lx",(unsigned long)addr);
+ break;
+ case 2:
+ sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
+ break;
+ default:
+ sprintf(paddr_str,"%x",addr);
+ }
+ return paddr_str;
}
+char*
+pr_uword64(addr)
+ uword64 addr;
+{
+ char *paddr_str=get_cell();
+ sprintf(paddr_str,"%08lx%08lx",
+ (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
+ return paddr_str;
+}
+
+
/*---------------------------------------------------------------------------*/
/*> EOF interp.c <*/
projects / deliverable / binutils-gdb.git / blobdiff