MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
$Revision$
- $Author$
- $Date$
+ $Date$
NOTEs:
#include "sim-options.h"
#include "sim-assert.h"
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+#include "sky-vu.h"
+#include "sky-vpe.h"
+#include "sky-libvpe.h"
+#endif
+/* end-sanitize-sky */
+
#include "config.h"
#include <stdio.h>
/* Get the simulator engine description, without including the code: */
+#if !(WITH_IGEN)
#define SIM_MANIFESTS
#include "oengine.c"
#undef SIM_MANIFESTS
+#endif
+
+/* Within interp.c we refer to the sim_state and sim_cpu directly. */
+#define SD sd
+#define CPU cpu
/* The following reserved instruction value is used when a simulator
#define MONITOR_SIZE (1 << 11)
#define MEM_SIZE (2 << 20)
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+#undef MEM_SIZE
+#define MEM_SIZE (16 << 20) /* 16 MB */
+#endif
+/* end-sanitize-sky */
+
#if defined(TRACE)
static char *tracefile = "trace.din"; /* default filename for trace log */
FILE *tracefh = NULL;
static void open_trace PARAMS((SIM_DESC sd));
#endif /* TRACE */
-#define OPTION_DINERO_TRACE 200
-#define OPTION_DINERO_FILE 201
+static DECLARE_OPTION_HANDLER (mips_option_handler);
+
+enum {
+ OPTION_DINERO_TRACE = OPTION_START,
+ OPTION_DINERO_FILE
+/* start-sanitize-sky */
+ ,OPTION_FLOAT_TYPE
+/* end-sanitize-sky */
+};
static SIM_RC
-mips_option_handler (sd, opt, arg)
+mips_option_handler (sd, cpu, opt, arg, is_command)
SIM_DESC sd;
+ sim_cpu *cpu;
int opt;
char *arg;
+ int is_command;
{
+ int cpu_nr;
switch (opt)
{
case OPTION_DINERO_TRACE: /* ??? */
allow external control of the program points being traced
(i.e. only from main onwards, excluding the run-time setup,
etc.). */
- if (arg == NULL)
- STATE |= simTRACE;
- else if (strcmp (arg, "yes") == 0)
- STATE |= simTRACE;
- else if (strcmp (arg, "no") == 0)
- STATE &= ~simTRACE;
- else if (strcmp (arg, "on") == 0)
- STATE |= simTRACE;
- else if (strcmp (arg, "off") == 0)
- STATE &= ~simTRACE;
- else
+ for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
{
- fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
- return SIM_RC_FAIL;
+ sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+ if (arg == NULL)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "yes") == 0)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "no") == 0)
+ STATE &= ~simTRACE;
+ else if (strcmp (arg, "on") == 0)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "off") == 0)
+ STATE &= ~simTRACE;
+ else
+ {
+ fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
}
return SIM_RC_OK;
#else /* !TRACE */
#endif /* TRACE */
return SIM_RC_OK;
+/* start-sanitize-sky */
+ case OPTION_FLOAT_TYPE:
+ /* Use host (fast) or target (accurate) floating point implementation. */
+ if (arg && strcmp (arg, "host") == 0)
+ STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_TARGET;
+ else if (arg && strcmp (arg, "target") == 0)
+ STATE_FP_TYPE_OPT (sd) |= STATE_FP_TYPE_OPT_TARGET;
+ else
+ {
+ fprintf (stderr, "Unrecognized float-type option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+ return SIM_RC_OK;
+/* end-sanitize-sky */
}
return SIM_RC_OK;
{ {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
'\0', "FILE", "Write dinero trace to FILE",
mips_option_handler },
+/* start-sanitize-sky */
+ { {"float-type", required_argument, NULL, OPTION_FLOAT_TYPE},
+ '\0', "host|target", "Use host (fast) or target (accurate) floating point",
+ mips_option_handler },
+/* end-sanitize-sky */
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
};
static void
interrupt_event (SIM_DESC sd, void *data)
{
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
if (SR & status_IE)
{
interrupt_pending = 0;
}
+/*---------------------------------------------------------------------------*/
+/*-- Device registration hook -----------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+static void device_init(SIM_DESC sd) {
+#ifdef DEVICE_INIT
+ extern void register_devices(SIM_DESC);
+ register_devices(sd);
+#endif
+}
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
char **argv;
{
SIM_DESC sd = sim_state_alloc (kind, cb);
- sim_cpu *cpu = STATE_CPU (sd, 0);
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
- sim_add_option_table (sd, mips_options);
+ sim_add_option_table (sd, NULL, mips_options);
/* Allocate core managed memory */
/* For compatibility with the old code - under this (at level one)
are the kernel spaces K0 & K1. Both of these map to a single
smaller sub region */
+ sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
+/* start-sanitize-sky */
+#ifndef TARGET_SKY
+/* end-sanitize-sky */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
K1BASE, K0SIZE,
MEM_SIZE, /* actual size */
K0BASE);
+/* start-sanitize-sky */
+#else
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
+ K1BASE, K0SIZE,
+ MEM_SIZE, /* actual size */
+ K0BASE,
+ 0); /* add alias at 0x0000 */
+#endif
+/* end-sanitize-sky */
+
+ device_init(sd);
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
-#if defined(HASFPU)
- /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
- and DOUBLE binary formats. This is a bit nasty, requiring that we
- trust the explicit manifests held in the source: */
- /* TODO: We need to cope with the simulated target and the host not
- having the same endianness. This will require the high and low
- words of a (double) to be swapped when converting between the
- host and the simulated target. */
- {
- union {
- unsigned int i[2];
- double d;
- float f[2];
- } s;
-
- s.d = (double)523.2939453125;
-
- if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125
- || s.i[1] != 0x40805A5A))
- || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125
- || s.i[0] != 0x40805A5A)))
- {
- fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
- return 0;
- }
- }
-#endif /* HASFPU */
-
/* This is NASTY, in that we are assuming the size of specific
registers: */
{
int rn;
- for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
- if (rn < 32)
- cpu->register_widths[rn] = GPRLEN;
- else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
- cpu->register_widths[rn] = GPRLEN;
- else if ((rn >= 33) && (rn <= 37))
- cpu->register_widths[rn] = GPRLEN;
- else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
- cpu->register_widths[rn] = 32;
- else
- cpu->register_widths[rn] = 0;
- }
+ for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
+ {
+ if (rn < 32)
+ cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
+ else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
+ cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
+ else if ((rn >= 33) && (rn <= 37))
+ cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
+ else if ((rn == SRIDX)
+ || (rn == FCR0IDX)
+ || (rn == FCR31IDX)
+ || ((rn >= 72) && (rn <= 89)))
+ cpu->register_widths[rn] = 32;
+ else
+ cpu->register_widths[rn] = 0;
+ }
/* start-sanitize-r5900 */
/* set the 5900 "upper" registers to 64 bits */
for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
cpu->register_widths[rn] = 64;
/* end-sanitize-r5900 */
+
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ /* Now the VU registers */
+ for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
+ cpu->register_widths[rn + NUM_R5900_REGS] = 16;
+ cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
+ }
+
+ for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
+ cpu->register_widths[rn + NUM_R5900_REGS] = 32;
+ cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
+ }
+#endif
+ /* end-sanitize-sky */
}
#if defined(TRACE)
if (tracefh != NULL && tracefh != stderr)
fclose(tracefh);
tracefh = NULL;
- STATE &= ~simTRACE;
#endif /* TRACE */
+ /* FIXME - free SD */
+
return;
}
int size;
{
int index;
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* Return the number of bytes written, or zero if error. */
#ifdef DEBUG
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
- if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
+ if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
break;
- if (sim_core_write_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
+ if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
break;
}
int size;
{
int index;
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* Return the number of bytes read, or zero if error. */
#ifdef DEBUG
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
- if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
+ if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
break;
- if (sim_core_read_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
+ if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
break;
}
return(index);
}
-void
-sim_store_register (sd,rn,memory)
+int
+sim_store_register (sd,rn,memory,length)
SIM_DESC sd;
int rn;
unsigned char *memory;
+ int length;
{
- sim_cpu *cpu = STATE_CPU (sd, 0);
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
#ifdef DEBUG
register number is for the architecture being simulated. */
if (cpu->register_widths[rn] == 0)
- sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
+ {
+ sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
+ return 0;
+ }
+
/* start-sanitize-r5900 */
- else if (rn == REGISTER_SA)
- SA = T2H_8(*(uword64*)memory);
- else if (rn > LAST_EMBED_REGNUM)
- cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory);
+ if (rn >= 90 && rn < 90 + 32)
+ {
+ GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
+ return 8;
+ }
+ switch (rn)
+ {
+ case REGISTER_SA:
+ SA = T2H_8(*(unsigned64*)memory);
+ return 8;
+ case 122: /* FIXME */
+ LO1 = T2H_8(*(unsigned64*)memory);
+ return 8;
+ case 123: /* FIXME */
+ HI1 = T2H_8(*(unsigned64*)memory);
+ return 8;
+ }
/* end-sanitize-r5900 */
- else if (cpu->register_widths[rn] == 32)
- cpu->registers[rn] = T2H_4 (*(unsigned int*)memory);
- else
- cpu->registers[rn] = T2H_8 (*(uword64*)memory);
- return;
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ if (rn >= NUM_R5900_REGS)
+ {
+ int size = 4; /* Default register size */
+
+ rn = rn - NUM_R5900_REGS;
+
+ if (rn < NUM_VU_INTEGER_REGS)
+ size = write_vu_int_reg (&(vu0_device.state->regs), rn, memory);
+ else if( rn < NUM_VU_REGS )
+ {
+ if (rn >= FIRST_VEC_REG)
+ {
+ rn -= FIRST_VEC_REG;
+ size = write_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn&3,
+ memory);
+ }
+ else switch (rn - NUM_VU_INTEGER_REGS)
+ {
+ case 0:
+ size = write_vu_special_reg (vu0_device.state, VU_REG_CIA,
+ memory);
+ break;
+ case 1:
+ size = write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
+ memory);
+ break;
+ case 2: /* VU0 has no P register */
+ break;
+ case 3:
+ size = write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
+ memory);
+ break;
+ case 4:
+ size = write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
+ memory);
+ break;
+ default:
+ size = write_vu_acc_reg (&(vu0_device.state->regs),
+ rn - (NUM_VU_INTEGER_REGS + 5),
+ memory);
+ break;
+ }
+ }
+ else {
+ rn = rn - NUM_VU_REGS;
+
+ if( rn < NUM_VU_INTEGER_REGS )
+ size = write_vu_int_reg (&(vu1_device.state->regs), rn, memory);
+ else if( rn < NUM_VU_REGS )
+ {
+ if (rn >= FIRST_VEC_REG)
+ {
+ rn -= FIRST_VEC_REG;
+ size = write_vu_vec_reg (&(vu1_device.state->regs),
+ rn >> 2, rn & 3, memory);
+ }
+ else switch (rn - NUM_VU_INTEGER_REGS)
+ {
+ case 0:
+ size = write_vu_special_reg (vu1_device.state, VU_REG_CIA,
+ memory);
+ break;
+ case 1:
+ size = write_vu_misc_reg (&(vu1_device.state->regs),
+ VU_REG_MR, memory);
+ break;
+ case 2:
+ size = write_vu_misc_reg (&(vu1_device.state->regs),
+ VU_REG_MP, memory);
+ break;
+ case 3:
+ size = write_vu_misc_reg (&(vu1_device.state->regs),
+ VU_REG_MI, memory);
+ break;
+ case 4:
+ size = write_vu_misc_reg (&(vu1_device.state->regs),
+ VU_REG_MQ, memory);
+ break;
+ default:
+ size = write_vu_acc_reg (&(vu1_device.state->regs),
+ rn - (NUM_VU_INTEGER_REGS + 5),
+ memory);
+ break;
+ }
+ }
+ else
+ sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
+ }
+
+ return size;
+ }
+#endif
+ /* end-sanitize-sky */
+
+ if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ {
+ if (cpu->register_widths[rn] == 32)
+ {
+ cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
+ return 4;
+ }
+ else
+ {
+ cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
+ return 8;
+ }
+ }
+
+ if (cpu->register_widths[rn] == 32)
+ {
+ cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
+ return 4;
+ }
+ else
+ {
+ cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
+ return 8;
+ }
}
-void
-sim_fetch_register (sd,rn,memory)
+int
+sim_fetch_register (sd,rn,memory,length)
SIM_DESC sd;
int rn;
unsigned char *memory;
+ int length;
{
- sim_cpu *cpu = STATE_CPU (sd, 0);
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
#ifdef DEBUG
#endif /* DEBUG */
if (cpu->register_widths[rn] == 0)
- sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
+ {
+ sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
+ return 0;
+ }
+
/* start-sanitize-r5900 */
- else if (rn == REGISTER_SA)
- *((uword64 *)memory) = H2T_8(SA);
- else if (rn > LAST_EMBED_REGNUM)
- *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
+ if (rn >= 90 && rn < 90 + 32)
+ {
+ *(unsigned64*)memory = GPR1[rn - 90];
+ return 8;
+ }
+ switch (rn)
+ {
+ case REGISTER_SA:
+ *((unsigned64*)memory) = H2T_8(SA);
+ return 8;
+ case 122: /* FIXME */
+ *((unsigned64*)memory) = H2T_8(LO1);
+ return 8;
+ case 123: /* FIXME */
+ *((unsigned64*)memory) = H2T_8(HI1);
+ return 8;
+ }
/* end-sanitize-r5900 */
- else if (cpu->register_widths[rn] == 32)
- *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF));
- else /* 64bit register */
- *((uword64 *)memory) = H2T_8 (cpu->registers[rn]);
- return;
-}
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ if (rn >= NUM_R5900_REGS)
+ {
+ int size = 4; /* default register width */
+ rn = rn - NUM_R5900_REGS;
-void
-sim_info (sd,verbose)
- SIM_DESC sd;
- int verbose;
-{
- /* Accessed from the GDB "info files" command: */
- if (STATE_VERBOSE_P (sd) || verbose)
+ if (rn < NUM_VU_INTEGER_REGS)
+ size = read_vu_int_reg (&(vu0_device.state->regs), rn, memory);
+ else if (rn < NUM_VU_REGS)
+ {
+ if (rn >= FIRST_VEC_REG)
+ {
+ rn -= FIRST_VEC_REG;
+ size = read_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn & 3,
+ memory);
+ }
+ else switch (rn - NUM_VU_INTEGER_REGS)
+ {
+ case 0:
+ size = read_vu_special_reg (vu0_device.state, VU_REG_CIA,
+ memory);
+
+ break;
+ case 1:
+ size = read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
+ memory);
+ break;
+ case 2: /* VU0 has no P register */
+ break;
+ case 3:
+ size = read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
+ memory);
+ break;
+ case 4:
+ size = read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
+ memory);
+ break;
+ default:
+ size = read_vu_acc_reg (&(vu0_device.state->regs),
+ rn - (NUM_VU_INTEGER_REGS + 5),
+ memory);
+ break;
+ }
+ }
+ else
+ {
+ rn = rn - NUM_VU_REGS;
+
+ if (rn < NUM_VU_INTEGER_REGS)
+ size = read_vu_int_reg (&(vu1_device.state->regs), rn, memory);
+ else if (rn < NUM_VU_REGS)
+ {
+ if (rn >= FIRST_VEC_REG)
+ {
+ rn -= FIRST_VEC_REG;
+ size = read_vu_vec_reg (&(vu1_device.state->regs),
+ rn >> 2, rn & 3, memory);
+ }
+ else switch (rn - NUM_VU_INTEGER_REGS)
+ {
+ case 0:
+ size = read_vu_special_reg (vu1_device.state, VU_REG_CIA,
+ memory);
+ break;
+ case 1:
+ size = read_vu_misc_reg (&(vu1_device.state->regs),
+ VU_REG_MR, memory);
+ break;
+ case 2:
+ size = read_vu_misc_reg (&(vu1_device.state->regs),
+ VU_REG_MP, memory);
+ break;
+ case 3:
+ size = read_vu_misc_reg (&(vu1_device.state->regs),
+ VU_REG_MI, memory);
+ break;
+ case 4:
+ size = read_vu_misc_reg (&(vu1_device.state->regs),
+ VU_REG_MQ, memory);
+ break;
+ default:
+ size = read_vu_acc_reg (&(vu1_device.state->regs),
+ rn - (NUM_VU_INTEGER_REGS + 5),
+ memory);
+ break;
+ }
+ }
+ else
+ sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
+ }
+
+ return size;
+ }
+#endif
+ /* end-sanitize-sky */
+
+ /* Any floating point register */
+ if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
{
-
- sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
- (PROCESSOR_64BIT ? 64 : 32),
- (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
-
-#if !defined(FASTSIM)
- /* It would be a useful feature, if when performing multi-cycle
- simulations (rather than single-stepping) we keep the start and
- end times of the execution, so that we can give a performance
- figure for the simulator. */
-#endif /* !FASTSIM */
- sim_io_printf (sd, "Number of execution cycles = %ld\n",
- (long) sim_events_time (sd));
-
- /* print information pertaining to MIPS ISA and architecture being simulated */
- /* things that may be interesting */
- /* instructions executed - if available */
- /* cycles executed - if available */
- /* pipeline stalls - if available */
- /* virtual time taken */
- /* profiling size */
- /* profiling frequency */
- /* profile minpc */
- /* profile maxpc */
- }
- profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL);
+ if (cpu->register_widths[rn] == 32)
+ {
+ *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
+ return 4;
+ }
+ else
+ {
+ *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
+ return 8;
+ }
+ }
+
+ if (cpu->register_widths[rn] == 32)
+ {
+ *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
+ return 4;
+ }
+ else
+ {
+ *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
+ return 8;
+ }
}
ColdReset(sd);
if (abfd != NULL)
- /* override PC value set by ColdReset () */
- PC = (unsigned64) bfd_get_start_address (abfd);
+ {
+ /* override PC value set by ColdReset () */
+ int cpu_nr;
+ for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
+ {
+ sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+ CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
+ }
+ }
#if 0 /* def DEBUG */
if (argv || env)
/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
static void
-sim_monitor(sd,cia,reason)
- SIM_DESC sd;
- address_word cia;
- unsigned int reason;
+sim_monitor (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ unsigned int reason)
{
#ifdef DEBUG
printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
case 2: /* Densan monitor: char inbyte(int waitflag) */
{
if (A0 == 0) /* waitflag == NOWAIT */
- V0 = (ut_reg)-1;
+ V0 = (unsigned_word)-1;
}
/* Drop through to case 11 */
if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
{
sim_io_error(sd,"Invalid return from character read");
- V0 = (ut_reg)-1;
+ V0 = (unsigned_word)-1;
}
else
- V0 = (ut_reg)tmp;
+ V0 = (unsigned_word)tmp;
break;
}
case 17: /* void _exit() */
{
sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
(unsigned int)(A0 & 0xFFFFFFFF));
break;
}
/* [A0 + 4] = instruction cache size */
/* [A0 + 8] = data cache size */
{
- address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
+ unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
+ unsigned_4 zero = 0;
H2T (value);
- sim_write (sd, A0, (char *)&value, sizeof (value));
+ sim_write (sd, A0 + 0, (char *)&value, 4);
+ sim_write (sd, A0 + 4, (char *)&zero, 4);
+ sim_write (sd, A0 + 8, (char *)&zero, 4);
/* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
break;
}
/* Store a word into memory. */
static void
-store_word (sd, cia, vaddr, val)
- SIM_DESC sd;
- address_word cia;
- uword64 vaddr;
- t_reg val;
+store_word (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ uword64 vaddr,
+ signed_word val)
{
address_word paddr;
int uncached;
/* Load a word from memory. */
-static t_reg
-load_word (sd, cia, vaddr)
- SIM_DESC sd;
- address_word cia;
- uword64 vaddr;
+static signed_word
+load_word (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ uword64 vaddr)
{
if ((vaddr & 3) != 0)
SignalExceptionAddressLoad ();
code, but for ease of simulation we just handle them directly. */
static void
-mips16_entry (sd,insn)
- SIM_DESC sd;
- unsigned int insn;
+mips16_entry (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ unsigned int insn)
{
int aregs, sregs, rreg;
if (aregs < 5)
{
int i;
- t_reg tsp;
+ signed_word tsp;
/* This is the entry pseudo-instruction. */
for (i = 0; i < aregs; i++)
- store_word ((uword64) (SP + 4 * i), GPR[i + 4]);
+ store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
tsp = SP;
SP -= 32;
if (rreg)
{
tsp -= 4;
- store_word ((uword64) tsp, RA);
+ store_word (SD, CPU, cia, (uword64) tsp, RA);
}
for (i = 0; i < sregs; i++)
{
tsp -= 4;
- store_word ((uword64) tsp, GPR[16 + i]);
+ store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
}
}
else
{
int i;
- t_reg tsp;
+ signed_word tsp;
/* This is the exit pseudo-instruction. */
if (rreg)
{
tsp -= 4;
- RA = load_word ((uword64) tsp);
+ RA = load_word (SD, CPU, cia, (uword64) tsp);
}
for (i = 0; i < sregs; i++)
{
tsp -= 4;
- GPR[i + 16] = load_word ((uword64) tsp);
+ GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
}
SP += 32;
-#if defined(HASFPU)
- if (aregs == 5)
- {
- FGR[0] = WORD64LO (GPR[4]);
- FPR_STATE[0] = fmt_uninterpreted;
- }
- else if (aregs == 6)
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
- FGR[0] = WORD64LO (GPR[5]);
- FGR[1] = WORD64LO (GPR[4]);
- FPR_STATE[0] = fmt_uninterpreted;
- FPR_STATE[1] = fmt_uninterpreted;
- }
-#endif /* defined(HASFPU) */
+ if (aregs == 5)
+ {
+ FGR[0] = WORD64LO (GPR[4]);
+ FPR_STATE[0] = fmt_uninterpreted;
+ }
+ else if (aregs == 6)
+ {
+ FGR[0] = WORD64LO (GPR[5]);
+ FGR[1] = WORD64LO (GPR[4]);
+ FPR_STATE[0] = fmt_uninterpreted;
+ FPR_STATE[1] = fmt_uninterpreted;
+ }
+ }
PC = RA;
}
+
}
/*-- trace support ----------------------------------------------------------*/
void
-dotrace (SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
+dotrace (SIM_DESC sd,
+ sim_cpu *cpu,
+ FILE *tracefh,
+ int type,
+ SIM_ADDR address,
+ int width,
+ char *comment,...)
{
if (STATE & simTRACE) {
va_list ap;
/*---------------------------------------------------------------------------*/
static void
-ColdReset (sd)
- SIM_DESC sd;
+ColdReset (SIM_DESC sd)
{
- /* RESET: Fixed PC address: */
- PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
- /* The reset vector address is in the unmapped, uncached memory space. */
-
- SR &= ~(status_SR | status_TS | status_RP);
- SR |= (status_ERL | status_BEV);
-
- /* Cheat and allow access to the complete register set immediately */
- if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
- && WITH_TARGET_WORD_BITSIZE == 64)
- SR |= status_FR; /* 64bit registers */
-
- /* Ensure that any instructions with pending register updates are
- cleared: */
- {
- int loop;
- for (loop = 0; (loop < PSLOTS); loop++)
- PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1);
- PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0;
- }
-
- /* Initialise the FPU registers to the unknown state */
- if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ int cpu_nr;
+ for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
{
- int rn;
- for (rn = 0; (rn < 32); rn++)
- FPR_STATE[rn] = fmt_uninterpreted;
+ sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+ /* RESET: Fixed PC address: */
+ PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
+ /* The reset vector address is in the unmapped, uncached memory space. */
+
+ SR &= ~(status_SR | status_TS | status_RP);
+ SR |= (status_ERL | status_BEV);
+
+ /* Cheat and allow access to the complete register set immediately */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
+ && WITH_TARGET_WORD_BITSIZE == 64)
+ SR |= status_FR; /* 64bit registers */
+
+ /* Ensure that any instructions with pending register updates are
+ cleared: */
+ PENDING_INVALIDATE();
+
+ /* Initialise the FPU registers to the unknown state */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ int rn;
+ for (rn = 0; (rn < 32); rn++)
+ FPR_STATE[rn] = fmt_uninterpreted;
+ }
+
}
-
- return;
}
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
function raises an exception and does not return. */
int
-address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
- SIM_DESC sd;
- address_word cia;
- address_word vAddr;
- int IorD;
- int LorS;
- address_word *pAddr;
- int *CCA;
- int raw;
+address_translation (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ address_word vAddr,
+ int IorD,
+ int LorS,
+ address_word *pAddr,
+ int *CCA,
+ int raw)
{
int res = -1; /* TRUE : Assume good return */
program, or alter architecturally-visible state. */
void
-prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
- SIM_DESC sd;
- address_word cia;
- int CCA;
- address_word pAddr;
- address_word vAddr;
- int DATA;
- int hint;
+prefetch (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int CCA,
+ address_word pAddr,
+ address_word vAddr,
+ int DATA,
+ int hint)
{
#ifdef DEBUG
sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
satisfy a load reference. At a minimum, the block is the entire
memory element. */
void
-load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
- SIM_DESC sd;
- address_word cia;
- uword64* memvalp;
- uword64* memval1p;
- int CCA;
- int AccessLength;
- address_word pAddr;
- address_word vAddr;
- int IorD;
+load_memory (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ uword64* memvalp,
+ uword64* memval1p,
+ int CCA,
+ unsigned int AccessLength,
+ address_word pAddr,
+ address_word vAddr,
+ int IorD)
{
uword64 value = 0;
uword64 value1 = 0;
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
{
/* In reality this should be a Bus Error */
- sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
+ sim_io_error (sd, "LOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
AccessLength,
- (LOADDRMASK + 1) << 2,
+ (LOADDRMASK + 1) << 3,
pr_addr (pAddr));
}
#if defined(TRACE)
- dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
+ dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
#endif /* TRACE */
/* Read the specified number of bytes from memory. Adjust for
{
case AccessLength_QUADWORD :
{
- unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_read_map, pAddr);
+ unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, read_map, pAddr);
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
case AccessLength_DOUBLEWORD :
- value = sim_core_read_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_read_map, pAddr);
+ value = sim_core_read_aligned_8 (cpu, NULL_CIA,
+ read_map, pAddr);
break;
case AccessLength_SEPTIBYTE :
- value = sim_core_read_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_read_map, pAddr);
+ value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
+ read_map, pAddr);
+ break;
case AccessLength_SEXTIBYTE :
- value = sim_core_read_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_read_map, pAddr);
+ value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
+ read_map, pAddr);
+ break;
case AccessLength_QUINTIBYTE :
- value = sim_core_read_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_read_map, pAddr);
+ value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
+ read_map, pAddr);
+ break;
case AccessLength_WORD :
- value = sim_core_read_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_read_map, pAddr);
+ value = sim_core_read_aligned_4 (cpu, NULL_CIA,
+ read_map, pAddr);
break;
case AccessLength_TRIPLEBYTE :
- value = sim_core_read_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_read_map, pAddr);
+ value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
+ read_map, pAddr);
+ break;
case AccessLength_HALFWORD :
- value = sim_core_read_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_read_map, pAddr);
+ value = sim_core_read_aligned_2 (cpu, NULL_CIA,
+ read_map, pAddr);
break;
case AccessLength_BYTE :
- value = sim_core_read_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_read_map, pAddr);
+ value = sim_core_read_aligned_1 (cpu, NULL_CIA,
+ read_map, pAddr);
break;
default:
abort ();
(int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
#endif /* DEBUG */
- /* See also store_memory. */
- if (AccessLength <= AccessLength_DOUBLEWORD)
+ /* See also store_memory. Position data in correct byte lanes. */
+ if (AccessLength <= LOADDRMASK)
{
if (BigEndianMem)
/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
shifted to the most significant byte position. */
- value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
+ value <<= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
else
/* For little endian target, byte (pAddr&LOADDRMASK == 0)
is already in the correct postition. */
will be changed. */
void
-store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
- SIM_DESC sd;
- address_word cia;
- int CCA;
- int AccessLength;
- uword64 MemElem;
- uword64 MemElem1; /* High order 64 bits */
- address_word pAddr;
- address_word vAddr;
+store_memory (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int CCA,
+ unsigned int AccessLength,
+ uword64 MemElem,
+ uword64 MemElem1, /* High order 64 bits */
+ address_word pAddr,
+ address_word vAddr)
{
#ifdef DEBUG
sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
#endif /* WARN_MEM */
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
- sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
+ sim_io_error (sd, "STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
+ AccessLength,
+ (LOADDRMASK + 1) << 3,
+ pr_addr(pAddr));
#if defined(TRACE)
- dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
+ dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
#endif /* TRACE */
#ifdef DEBUG
printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
#endif /* DEBUG */
- /* See also load_memory */
- if (AccessLength <= AccessLength_DOUBLEWORD)
+ /* See also load_memory. Position data in correct byte lanes. */
+ if (AccessLength <= LOADDRMASK)
{
if (BigEndianMem)
/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
shifted to the most significant byte position. */
- MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
+ MemElem >>= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
else
/* For little endian target, byte (pAddr&LOADDRMASK == 0)
is already in the correct postition. */
case AccessLength_QUADWORD :
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
- sim_core_write_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_write_map, pAddr, val);
+ sim_core_write_aligned_16 (cpu, NULL_CIA, write_map, pAddr, val);
break;
}
case AccessLength_DOUBLEWORD :
- sim_core_write_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
+ sim_core_write_aligned_8 (cpu, NULL_CIA,
+ write_map, pAddr, MemElem);
break;
case AccessLength_SEPTIBYTE :
- sim_core_write_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
+ sim_core_write_misaligned_7 (cpu, NULL_CIA,
+ write_map, pAddr, MemElem);
break;
case AccessLength_SEXTIBYTE :
- sim_core_write_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
+ sim_core_write_misaligned_6 (cpu, NULL_CIA,
+ write_map, pAddr, MemElem);
break;
case AccessLength_QUINTIBYTE :
- sim_core_write_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
+ sim_core_write_misaligned_5 (cpu, NULL_CIA,
+ write_map, pAddr, MemElem);
break;
case AccessLength_WORD :
- sim_core_write_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
+ sim_core_write_aligned_4 (cpu, NULL_CIA,
+ write_map, pAddr, MemElem);
break;
case AccessLength_TRIPLEBYTE :
- sim_core_write_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
+ sim_core_write_misaligned_3 (cpu, NULL_CIA,
+ write_map, pAddr, MemElem);
break;
case AccessLength_HALFWORD :
- sim_core_write_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
+ sim_core_write_aligned_2 (cpu, NULL_CIA,
+ write_map, pAddr, MemElem);
break;
case AccessLength_BYTE :
- sim_core_write_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
- sim_core_write_map, pAddr, MemElem);
+ sim_core_write_aligned_1 (cpu, NULL_CIA,
+ write_map, pAddr, MemElem);
break;
default:
abort ();
unsigned32
ifetch32 (SIM_DESC sd,
+ sim_cpu *cpu,
address_word cia,
address_word vaddr)
{
}
+unsigned16
+ifetch16 (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ address_word vaddr)
+{
+ /* Copy the action of the LW instruction */
+ address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
+ address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
+ unsigned64 value;
+ address_word paddr;
+ unsigned16 instruction;
+ unsigned byte;
+ int cca;
+ AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
+ paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
+ LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
+ byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
+ instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ return instruction;
+}
+
+
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* Order loads and stores to synchronise shared memory. Perform the
action necessary to make the effects of groups of synchronizable
loads and stores indicated by stype occur in the same order for all
processors. */
void
-sync_operation(sd,cia,stype)
- SIM_DESC sd;
- address_word cia;
- int stype;
+sync_operation (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int stype)
{
#ifdef DEBUG
sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
void
signal_exception (SIM_DESC sd,
+ sim_cpu *cpu,
address_word cia,
int exception,...)
{
code = (instruction >> 6) & 0xFFFFF;
sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
- code, pr_addr(cia));
+ code, pr_addr(cia));
}
break;
Debug |= Debug_DM; /* in debugging mode */
Debug |= Debug_DBp; /* raising a DBp exception */
PC = 0xBFC00200;
- sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
+ sim_engine_restart (SD, CPU, NULL, NULL_CIA);
}
break;
perform this magic. */
if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
{
- sim_monitor(sd, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
+ sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
/* NOTE: This assumes that a branch-and-link style
instruction was used to enter the vector (which is the
case with the current IDT monitor). */
- sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, RA);
+ sim_engine_restart (SD, CPU, NULL, RA);
}
/* Look for the mips16 entry and exit instructions, and
simulate a handler for them. */
&& (instruction & 0xf81f) == 0xe809
&& (instruction & 0x0c0) != 0x0c0)
{
- mips16_entry (instruction);
+ mips16_entry (SD, CPU, cia, instruction);
sim_engine_restart (sd, NULL, NULL, NULL_CIA);
}
/* else fall through to normal exception processing */
va_end(ap);
/* Check for our special terminating BREAK: */
if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
+ sim_engine_halt (SD, CPU, NULL, cia,
sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
}
}
PC = cia - 4; /* reference the branch instruction */
else
PC = cia;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
+ sim_engine_halt (SD, CPU, NULL, cia,
sim_stopped, SIM_SIGTRAP);
default:
/* The following is so that the simulator will continue from the
exception address on breakpoint operations. */
PC = EPC;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGBUS);
case ReservedInstruction:
case CoProcessorUnusable:
PC = EPC;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGILL);
case IntegerOverflow:
case FPE:
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGFPE);
case Trap:
case Watch:
case SystemCall:
PC = EPC;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGTRAP);
case BreakPoint:
PC = EPC;
- sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
+ sim_engine_abort (SD, CPU, NULL_CIA,
"FATAL: Should not encounter a breakpoint\n");
default : /* Unknown internal exception */
PC = EPC;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGABRT);
}
va_start(ap,exception);
msg = va_arg(ap,char *);
va_end(ap);
- sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
+ sim_engine_abort (SD, CPU, NULL_CIA,
"FATAL: Simulator error \"%s\"\n",msg);
}
}
#endif /* WARN_RESULT */
void
-cache_op(sd,cia,op,pAddr,vAddr,instruction)
- SIM_DESC sd;
- address_word cia;
- int op;
- address_word pAddr;
- address_word vAddr;
- unsigned int instruction;
+cache_op (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int op,
+ address_word pAddr,
+ address_word vAddr,
+ unsigned int instruction)
{
#if 1 /* stop warning message being displayed (we should really just remove the code) */
static int icache_warning = 1;
/*-- FPU support routines ---------------------------------------------------*/
-#if defined(HASFPU) /* Only needed when building FPU aware simulators */
-
/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
formats conform to ANSI/IEEE Std 754-1985. */
/* SINGLE precision floating:
#endif /* DEBUG */
uword64
-value_fpr(sd,cia,fpr,fmt)
- SIM_DESC sd;
- address_word cia;
- int fpr;
- FP_formats fmt;
+value_fpr (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int fpr,
+ FP_formats fmt)
{
uword64 value = 0;
int err = 0;
}
void
-store_fpr(sd,cia,fpr,fmt,value)
- SIM_DESC sd;
- address_word cia;
- int fpr;
- FP_formats fmt;
- uword64 value;
+store_fpr (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int fpr,
+ FP_formats fmt,
+ uword64 value)
{
int err = 0;
return(result);
}
+#if 0
uword64
-convert(sd,cia,rm,op,from,to)
- SIM_DESC sd;
- address_word cia;
- int rm;
- uword64 op;
- FP_formats from;
- FP_formats to;
+Max (uword64 op1,
+ uword64 op2,
+ FP_formats fmt)
+{
+ int cmp;
+ unsigned64 result;
+
+#ifdef DEBUG
+ printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
+#endif /* DEBUG */
+
+ /* The registers must specify FPRs valid for operands of type
+ "fmt". If they are not valid, the result is undefined. */
+
+ /* The format type should already have been checked: */
+ switch (fmt)
+ {
+ case fmt_single:
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ cmp = sim_fpu_cmp (&wop1, &wop2);
+ break;
+ }
+ case fmt_double:
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ cmp = sim_fpu_cmp (&wop1, &wop2);
+ break;
+ }
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
+ }
+
+ switch (cmp)
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_QNAN:
+ result = op1;
+ case SIM_FPU_IS_NINF:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NDENORM:
+ case SIM_FPU_IS_NZERO:
+ result = op2; /* op1 - op2 < 0 */
+ case SIM_FPU_IS_PINF:
+ case SIM_FPU_IS_PNUMBER:
+ case SIM_FPU_IS_PDENORM:
+ case SIM_FPU_IS_PZERO:
+ result = op1; /* op1 - op2 > 0 */
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
+ }
+
+#ifdef DEBUG
+ printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
+#endif /* DEBUG */
+
+ return(result);
+}
+#endif
+
+#if 0
+uword64
+Min (uword64 op1,
+ uword64 op2,
+ FP_formats fmt)
+{
+ int cmp;
+ unsigned64 result;
+
+#ifdef DEBUG
+ printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
+#endif /* DEBUG */
+
+ /* The registers must specify FPRs valid for operands of type
+ "fmt". If they are not valid, the result is undefined. */
+
+ /* The format type should already have been checked: */
+ switch (fmt)
+ {
+ case fmt_single:
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ cmp = sim_fpu_cmp (&wop1, &wop2);
+ break;
+ }
+ case fmt_double:
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ cmp = sim_fpu_cmp (&wop1, &wop2);
+ break;
+ }
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
+ }
+
+ switch (cmp)
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_QNAN:
+ result = op1;
+ case SIM_FPU_IS_NINF:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NDENORM:
+ case SIM_FPU_IS_NZERO:
+ result = op1; /* op1 - op2 < 0 */
+ case SIM_FPU_IS_PINF:
+ case SIM_FPU_IS_PNUMBER:
+ case SIM_FPU_IS_PDENORM:
+ case SIM_FPU_IS_PZERO:
+ result = op2; /* op1 - op2 > 0 */
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
+ }
+
+#ifdef DEBUG
+ printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
+#endif /* DEBUG */
+
+ return(result);
+}
+#endif
+
+uword64
+convert (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int rm,
+ uword64 op,
+ FP_formats from,
+ FP_formats to)
{
sim_fpu wop;
sim_fpu_round round;
return(result64);
}
-#endif /* HASFPU */
/*-- co-processor support routines ------------------------------------------*/
}
void
-cop_lw(sd,cia,coproc_num,coproc_reg,memword)
- SIM_DESC sd;
- address_word cia;
- int coproc_num, coproc_reg;
- unsigned int memword;
+cop_lw (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ unsigned int memword)
{
- switch (coproc_num) {
-#if defined(HASFPU)
+ switch (coproc_num)
+ {
case 1:
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
#ifdef DEBUG
- printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
+ printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
#endif
- StoreFPR(coproc_reg,fmt_word,(uword64)memword);
- FPR_STATE[coproc_reg] = fmt_uninterpreted;
- break;
-#endif /* HASFPU */
+ StoreFPR(coproc_reg,fmt_word,(uword64)memword);
+ FPR_STATE[coproc_reg] = fmt_uninterpreted;
+ break;
+ }
default:
#if 0 /* this should be controlled by a configuration option */
- sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
+ sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
#endif
- break;
- }
+ break;
+ }
return;
}
void
-cop_ld(sd,cia,coproc_num,coproc_reg,memword)
- SIM_DESC sd;
- address_word cia;
- int coproc_num, coproc_reg;
- uword64 memword;
+cop_ld (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ uword64 memword)
{
switch (coproc_num) {
-#if defined(HASFPU)
case 1:
- StoreFPR(coproc_reg,fmt_uninterpreted,memword);
- break;
-#endif /* HASFPU */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ StoreFPR(coproc_reg,fmt_uninterpreted,memword);
+ break;
+ }
default:
#if 0 /* this message should be controlled by a configuration option */
return;
}
+
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+void
+cop_lq (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ unsigned128 memword)
+{
+ switch (coproc_num)
+ {
+ case 2:
+ /* XXX COP2 */
+ break;
+
+ default:
+ sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
+ coproc_num,coproc_reg,pr_addr(cia));
+ break;
+ }
+
+ return;
+}
+#endif /* TARGET_SKY */
+/* end-sanitize-sky */
+
+
unsigned int
-cop_sw(sd,cia,coproc_num,coproc_reg)
- SIM_DESC sd;
- address_word cia;
- int coproc_num, coproc_reg;
+cop_sw (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg)
{
unsigned int value = 0;
- switch (coproc_num) {
-#if defined(HASFPU)
+ switch (coproc_num)
+ {
case 1:
-#if 1
- {
- FP_formats hold;
- hold = FPR_STATE[coproc_reg];
- FPR_STATE[coproc_reg] = fmt_word;
- value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
- FPR_STATE[coproc_reg] = hold;
- }
-#else
-#if 1
- value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
-#else
-#ifdef DEBUG
- printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg]));
-#endif /* DEBUG */
- value = (unsigned int)ValueFPR(coproc_reg,fmt_single);
-#endif
-#endif
- break;
-#endif /* HASFPU */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ FP_formats hold;
+ hold = FPR_STATE[coproc_reg];
+ FPR_STATE[coproc_reg] = fmt_word;
+ value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
+ FPR_STATE[coproc_reg] = hold;
+ break;
+ }
default:
#if 0 /* should be controlled by configuration option */
- sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
+ sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
#endif
- break;
- }
+ break;
+ }
return(value);
}
uword64
-cop_sd(sd,cia,coproc_num,coproc_reg)
- SIM_DESC sd;
- address_word cia;
- int coproc_num, coproc_reg;
+cop_sd (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg)
{
uword64 value = 0;
- switch (coproc_num) {
-#if defined(HASFPU)
+ switch (coproc_num)
+ {
case 1:
-#if 1
- value = ValueFPR(coproc_reg,fmt_uninterpreted);
-#else
-#if 1
- value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
-#else
-#ifdef DEBUG
- printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg]));
-#endif /* DEBUG */
- value = ValueFPR(coproc_reg,fmt_double);
-#endif
-#endif
- break;
-#endif /* HASFPU */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ value = ValueFPR(coproc_reg,fmt_uninterpreted);
+ break;
+ }
default:
#if 0 /* should be controlled by configuration option */
- sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
+ sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
#endif
- break;
- }
+ break;
+ }
+
+ return(value);
+}
+
+
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+unsigned128
+cop_sq (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg)
+{
+ unsigned128 value = U16_8(0, 0);
+ switch (coproc_num)
+ {
+ case 2:
+ /* XXX COP2 */
+ break;
+
+ default:
+ sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
+ coproc_num,coproc_reg,pr_addr(cia));
+ break;
+ }
return(value);
}
+#endif /* TARGET_SKY */
+/* end-sanitize-sky */
+
void
-decode_coproc(sd,cia,instruction)
- SIM_DESC sd;
- address_word cia;
- unsigned int instruction;
+decode_coproc (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ unsigned int instruction)
{
int coprocnum = ((instruction >> 26) & 3);
break;
case 2: /* undefined co-processor */
- sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
- break;
-
+ {
+ int handle = 0;
+
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ /* On the R5900, this refers to a "VU" vector co-processor. */
+
+ int i_25_21 = (instruction >> 21) & 0x1f;
+ int i_20_16 = (instruction >> 16) & 0x1f;
+ int i_15_11 = (instruction >> 11) & 0x1f;
+ int i_15_0 = instruction & 0xffff;
+ int i_10_1 = (instruction >> 1) & 0x3ff;
+ int i_5_0 = instruction & 0x03f;
+ int interlock = instruction & 0x01;
+ int co = (instruction >> 25) & 0x01;
+ /* setup for semantic.c-like actions below */
+ typedef unsigned_4 instruction_word;
+ int CIA = cia;
+ int NIA = cia + 4;
+ sim_cpu* CPU_ = cpu;
+
+ handle = 1;
+
+ /* test COP2 usability */
+ if(! (SR & status_CU2))
+ {
+ SignalException(CoProcessorUnusable,instruction);
+ /* NOTREACHED */
+ }
+
+ /* classify & execute basic COP2 instructions */
+ if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
+ {
+ address_word offset = EXTEND16(i_15_0) << 2;
+ if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
+ }
+ else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
+ {
+ address_word offset = EXTEND16(i_15_0) << 2;
+ if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
+ else NULLIFY_NEXT_INSTRUCTION();
+ }
+ else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
+ {
+ address_word offset = EXTEND16(i_15_0) << 2;
+ if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
+ }
+ else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
+ {
+ address_word offset = EXTEND16(i_15_0) << 2;
+ if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
+ else NULLIFY_NEXT_INSTRUCTION();
+ }
+ else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
+ (i_25_21 == 0x01)) /* QMFC2 */
+ {
+ int rt = i_20_16;
+ int id = i_15_11;
+ address_word vu_cr_addr; /* VU control register address */
+ unsigned_4 data;
+
+ /* interlock checking */
+ if(vu0_busy_in_macro_mode()) /* busy in macro mode */
+ {
+ /* interlock bit invalid here */
+ if(interlock)
+ ; /* XXX: warning */
+
+ /* always check data hazard */
+ while(vu0_macro_hazard_check(id))
+ vu0_issue(sd);
+ }
+ else if(vu0_busy_in_micro_mode() && interlock)
+ {
+ while(vu0_busy_in_micro_mode())
+ vu0_issue(sd);
+ }
+
+ /* compute VU register address */
+ if(i_25_21 == 0x01) /* QMFC2 */
+ vu_cr_addr = VU0_REGISTER_WINDOW_START + (id * 16);
+ else /* CFC2 */
+ vu_cr_addr = VU0_MST + (id * 16);
+
+ /* read or write word */
+ data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr);
+ GPR[rt] = EXTEND64(data);
+ }
+ else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
+ (i_25_21 == 0x05)) /* QMTC2 */
+ {
+ int rt = i_20_16;
+ int id = i_15_11;
+ address_word vu_cr_addr; /* VU control register address */
+ unsigned_4 data;
+
+ /* interlock checking */
+ if(vu0_busy_in_macro_mode()) /* busy in macro mode */
+ {
+ /* interlock bit invalid here */
+ if(interlock)
+ ; /* XXX: warning */
+
+ /* always check data hazard */
+ while(vu0_macro_hazard_check(id))
+ vu0_issue(sd);
+ }
+ else if(vu0_busy_in_micro_mode())
+ {
+ if(interlock)
+ {
+ while(! vu0_micro_interlock_released())
+ vu0_issue(sd);
+ }
+ }
+
+ /* compute VU register address */
+ if(i_25_21 == 0x05) /* QMTC2 */
+ vu_cr_addr = VU0_REGISTER_WINDOW_START + (id * 16);
+ else /* CTC2 */
+ vu_cr_addr = VU0_MST + (id * 16);
+
+ data = GPR[rt];
+ sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data);
+ }
+ else if( 0 /* XXX: ... upper ... */)
+ {
+ unsigned_4 vu_upper, vu_lower;
+ vu_upper =
+ 0x00000000 | /* bits 31 .. 25 */
+ instruction & 0x01ffffff; /* bits 24 .. 0 */
+ vu_lower = 0x8000033c; /* NOP */
+
+ while(vu0_busy_in_micro_mode())
+ vu0_issue(sd);
+
+ vu0_macro_issue(vu_upper, vu_lower);
+ }
+ else if( 0 /* XXX: ... lower ... */)
+ {
+ unsigned_4 vu_upper, vu_lower;
+ vu_upper = 0x000002ff; /* NOP */
+ vu_lower =
+ 0x10000000 | /* bits 31 .. 25 */
+ instruction & 0x01ffffff; /* bits 24 .. 0 */
+
+ while(vu0_busy_in_micro_mode())
+ vu0_issue(sd);
+
+ vu0_macro_issue(vu_upper, vu_lower);
+ }
+ /* XXX */
+ /* ... other COP2 instructions ... */
+ else
+ {
+ SignalException(ReservedInstruction, instruction);
+ /* NOTREACHED */
+ }
+
+ /* cleanup for semantic.c-like actions above */
+ PC = NIA;
+
+#endif /* TARGET_SKY */
+ /* end-sanitize-sky */
+
+ if(! handle)
+ {
+ sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
+ instruction,pr_addr(cia));
+ }
+ }
+ break;
+
case 1: /* should not occur (FPU co-processor) */
case 3: /* should not occur (FPU co-processor) */
SignalException(ReservedInstruction,instruction);
return;
}
+
/*-- instruction simulation -------------------------------------------------*/
/* When the IGEN simulator is being built, the function below is be
#if (WITH_IGEN > 1)
void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
void
-old_engine_run (sd, next_cpu_nr, siggnal)
+old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
#else
void
-sim_engine_run (sd, next_cpu_nr, siggnal)
+sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
#endif
SIM_DESC sd;
int next_cpu_nr; /* ignore */
+ int nr_cpus; /* ignore */
int siggnal; /* ignore */
{
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
#if !defined(FASTSIM)
unsigned int pipeline_count = 1;
#endif
CANCELDELAYSLOT();
}
- if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
- /* Deal with pending register updates: */
-#ifdef DEBUG
- printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
-#endif /* DEBUG */
- if (PENDING_OUT != PENDING_IN) {
- int loop;
- int index = PENDING_OUT;
- int total = PENDING_TOTAL;
- if (PENDING_TOTAL == 0) {
- fprintf(stderr,"FATAL: Mis-match on pending update pointers\n");
- exit(1);
- }
- for (loop = 0; (loop < total); loop++) {
-#ifdef DEBUG
- printf("DBG: BEFORE index = %d, loop = %d\n",index,loop);
-#endif /* DEBUG */
- if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) {
-#ifdef DEBUG
- printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]);
-#endif /* DEBUG */
- if (--(PENDING_SLOT_COUNT[index]) == 0) {
-#ifdef DEBUG
- printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]);
- printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index]));
-#endif /* DEBUG */
- if (PENDING_SLOT_REG[index] == COCIDX) {
-#if defined(HASFPU)
- SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
-#else
- ;
-#endif
- } else {
- REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
-#if defined(HASFPU)
- /* The only time we have PENDING updates to FPU
- registers, is when performing binary transfers. This
- means we should update the register type field. */
- if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
- FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
-#endif /* HASFPU */
- }
-#ifdef DEBUG
- printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]]));
-#endif /* DEBUG */
- PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1);
- PENDING_OUT++;
- if (PENDING_OUT == PSLOTS)
- PENDING_OUT = 0;
- PENDING_TOTAL--;
- }
- }
-#ifdef DEBUG
- printf("DBG: AFTER index = %d, loop = %d\n",index,loop);
-#endif /* DEBUG */
- index++;
- if (index == PSLOTS)
- index = 0;
- }
- }
-#ifdef DEBUG
- printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);
-#endif /* DEBUG */
- }
+ if (MIPSISA < 4)
+ PENDING_TICK();
#if !defined(FASTSIM)
if (sim_events_tickn (sd, pipeline_count))
}
+void
+pending_tick (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia)
+{
+ if (PENDING_TRACE)
+ sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
+ if (PENDING_OUT != PENDING_IN)
+ {
+ int loop;
+ int index = PENDING_OUT;
+ int total = PENDING_TOTAL;
+ if (PENDING_TOTAL == 0)
+ sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
+ for (loop = 0; (loop < total); loop++)
+ {
+ if (PENDING_SLOT_DEST[index] != NULL)
+ {
+ PENDING_SLOT_DELAY[index] -= 1;
+ if (PENDING_SLOT_DELAY[index] == 0)
+ {
+ if (PENDING_SLOT_BIT[index] >= 0)
+ switch (PENDING_SLOT_SIZE[index])
+ {
+ case 32:
+ if (PENDING_SLOT_VALUE[index])
+ *(unsigned32*)PENDING_SLOT_DEST[index] |=
+ BIT32 (PENDING_SLOT_BIT[index]);
+ else
+ *(unsigned32*)PENDING_SLOT_DEST[index] &=
+ BIT32 (PENDING_SLOT_BIT[index]);
+ break;
+ case 64:
+ if (PENDING_SLOT_VALUE[index])
+ *(unsigned64*)PENDING_SLOT_DEST[index] |=
+ BIT64 (PENDING_SLOT_BIT[index]);
+ else
+ *(unsigned64*)PENDING_SLOT_DEST[index] &=
+ BIT64 (PENDING_SLOT_BIT[index]);
+ break;
+ break;
+ }
+ else
+ switch (PENDING_SLOT_SIZE[index])
+ {
+ case 32:
+ *(unsigned32*)PENDING_SLOT_DEST[index] =
+ PENDING_SLOT_VALUE[index];
+ break;
+ case 64:
+ *(unsigned64*)PENDING_SLOT_DEST[index] =
+ PENDING_SLOT_VALUE[index];
+ break;
+ }
+ }
+ if (PENDING_OUT == index)
+ {
+ PENDING_SLOT_DEST[index] = NULL;
+ PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
+ PENDING_TOTAL--;
+ }
+ }
+ }
+ index = (index + 1) % PSLOTS;
+ }
+}
+
/*---------------------------------------------------------------------------*/
/*> EOF interp.c <*/
projects / deliverable / binutils-gdb.git / blobdiff