Implement 32 bit MIPS16 instructions listed in m16.igen.

[deliverable/binutils-gdb.git] / sim / mips / interp.c

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 2d5d4f4b78a7363f0b34f2ca9532feabfbbe4459..a8788d7393926152a8aa0622b78cac8381a585d7 100644 (file)
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -3375,7 +3375,9 @@ decode_coproc (SIM_DESC sd,
              vu0_issue(sd);
 
            /* write to reserved CIA register to get VU0 moving */
-           write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
+           write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
+
+           ASSERT(vu0_busy());
          }
        else if(i_5_0 == 0x39) /* VCALLMSR */
          {
@@ -3384,9 +3386,11 @@ decode_coproc (SIM_DESC sd,
            while(vu0_busy())
              vu0_issue(sd);
 
-           read_vu_misc_reg(&(vu0_device.regs), VU_REG_CMSAR0, & data);
+           read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
            /* write to reserved CIA register to get VU0 moving */
-           write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
+           write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
+
+           ASSERT(vu0_busy());
          }
        /* handle all remaining UPPER VU instructions in one block */
        else if((i_5_0 <  0x30) || /* VADDx .. VMINI */
@@ -3415,7 +3419,7 @@ decode_coproc (SIM_DESC sd,
            unsigned_4 vu_upper, vu_lower;
            vu_upper = 0x000002ff; /* NOP/NOP */
            vu_lower =
-             0x10000000 | /* bits 31 .. 25 */
+             0x80000000 | /* bits 31 .. 25 */
              (instruction & 0x01ffffff); /* bits 24 .. 0 */
 
            /* POLICY: never busy in macro mode */