Implement 32 bit MIPS16 instructions listed in m16.igen.

[deliverable/binutils-gdb.git] / sim / mips / interp.c

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index dac3a60e65704242dc2d7388b48e6195bf7e22be..a8788d7393926152a8aa0622b78cac8381a585d7 100644 (file)
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -2971,9 +2971,22 @@ cop_lq (SIM_DESC sd,
   switch (coproc_num)
     {
     case 2:
-      /* XXX COP2 */
-      break;
-      
+      {
+       unsigned_16 xyzw;
+
+       while(vu0_busy())
+         vu0_issue(sd);
+       
+       memcpy(& xyzw, & memword, sizeof(xyzw));
+       xyzw = H2T_16(xyzw);
+       /* one word at a time, argh! */
+       write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 0, A4_16(& xyzw, 3));
+       write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 1, A4_16(& xyzw, 2));
+       write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 2, A4_16(& xyzw, 1));
+       write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 3, A4_16(& xyzw, 0));
+      }
+    break;
+    
     default:
       sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
                    coproc_num,coproc_reg,pr_addr(cia));
@@ -3059,9 +3072,22 @@ cop_sq (SIM_DESC sd,
   switch (coproc_num)
     {
     case 2:
-      /* XXX COP2 */
-      break;
+      {
+       unsigned_16 xyzw;
 
+       while(vu0_busy())
+         vu0_issue(sd);
+       
+       /* one word at a time, argh! */
+       read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 0, A4_16(& xyzw, 3));
+       read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 1, A4_16(& xyzw, 2));
+       read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 2, A4_16(& xyzw, 1));
+       read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 3, A4_16(& xyzw, 0));
+       xyzw = T2H_16(xyzw);
+       return xyzw;
+      }
+    break;
+    
     default:
       sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
                    coproc_num,coproc_reg,pr_addr(cia));
@@ -3349,7 +3375,9 @@ decode_coproc (SIM_DESC sd,
              vu0_issue(sd);
 
            /* write to reserved CIA register to get VU0 moving */
-           write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
+           write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
+
+           ASSERT(vu0_busy());
          }
        else if(i_5_0 == 0x39) /* VCALLMSR */
          {
@@ -3358,9 +3386,11 @@ decode_coproc (SIM_DESC sd,
            while(vu0_busy())
              vu0_issue(sd);
 
-           read_vu_misc_reg(&(vu0_device.regs), VU_REG_CMSAR0, & data);
+           read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
            /* write to reserved CIA register to get VU0 moving */
-           write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
+           write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
+
+           ASSERT(vu0_busy());
          }
        /* handle all remaining UPPER VU instructions in one block */
        else if((i_5_0 <  0x30) || /* VADDx .. VMINI */
@@ -3368,7 +3398,7 @@ decode_coproc (SIM_DESC sd,
          {
            unsigned_4 vu_upper, vu_lower;
            vu_upper =
-             0x40000000 | /* bits 31 .. 25 */
+             0x00000000 | /* bits 31 .. 25 */
              (instruction & 0x01ffffff); /* bits 24 .. 0 */
            vu_lower = 0x8000033c; /* NOP */
 
@@ -3387,9 +3417,9 @@ decode_coproc (SIM_DESC sd,
                (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
          {                            /* N.B.: VWAITQ already covered by prior case */
            unsigned_4 vu_upper, vu_lower;
-           vu_upper = 0x400002ff; /* END/NOP */
+           vu_upper = 0x000002ff; /* NOP/NOP */
            vu_lower =
-             0x10000000 | /* bits 31 .. 25 */
+             0x80000000 | /* bits 31 .. 25 */
              (instruction & 0x01ffffff); /* bits 24 .. 0 */
 
            /* POLICY: never busy in macro mode */