$Revision$
$Author$
- $Date$
+ $Date$
NOTEs:
#define PROFILE (1)
#endif
+#include "config.h"
+
#include <stdio.h>
#include <stdarg.h>
#include <ansidecl.h>
#include <ctype.h>
#include <limits.h>
#include <math.h>
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#ifdef HAVE_STRING_H
+#include <string.h>
+#else
+#ifdef HAVE_STRINGS_H
+#include <strings.h>
+#endif
+#endif
#include "getopt.h"
#include "libiberty.h"
-#include "remote-sim.h" /* GDB simulator interface */
#include "callback.h" /* GDB simulator callback interface */
+#include "remote-sim.h" /* GDB simulator interface */
#include "support.h" /* internal support manifests */
+#include "sysdep.h"
+
+#ifndef SIGBUS
+#define SIGBUS SIGSEGV
+#endif
+
/* Get the simulator engine description, without including the code: */
#define SIM_MANIFESTS
#include "engine.c"
static host_callback *callback = NULL; /* handle onto the current callback structure */
-/* The warning system should be improved, to allow more information to
- be passed about the cause: */
-#define WARNING(m) { callback->printf_filtered(callback,"SIM Warning: %s\n",(m)); }
-
/* This is nasty, since we have to rely on matching the register
numbers used by GDB. Unfortunately, depending on the MIPS target
GDB uses different register numbers. We cannot just include the
order that the tools are built, we cannot rely on a configured GDB
world whilst constructing the simulator. This means we have to
assume the GDB register number mapping. */
+#ifndef TM_MIPS_H
#define LAST_EMBED_REGNUM (89)
+#endif
/* To keep this default simulator simple, and fast, we use a direct
vector of registers. The internal simulator engine then uses
manifests to access the correct slot. */
-ut_reg registers[LAST_EMBED_REGNUM + 1];
-int register_widths[LAST_EMBED_REGNUM + 1];
+static ut_reg registers[LAST_EMBED_REGNUM + 1];
+static int register_widths[LAST_EMBED_REGNUM + 1];
#define GPR (®isters[0])
#if defined(HASFPU)
#define SP (registers[29])
#define RA (registers[31])
-ut_reg EPC = 0; /* Exception PC */
+static ut_reg EPC = 0; /* Exception PC */
#if defined(HASFPU)
/* Keep the current format state for each register: */
-FP_formats fpr_state[32];
+static FP_formats fpr_state[32];
#endif /* HASFPU */
-/* VR4300 CP0 configuration register: */
-unsigned int CONFIG = 0;
-
/* The following are internal simulator state variables: */
-ut_reg IPC = 0; /* internal Instruction PC */
-ut_reg DSPC = 0; /* delay-slot PC */
+static ut_reg IPC = 0; /* internal Instruction PC */
+static ut_reg DSPC = 0; /* delay-slot PC */
/* TODO : these should be the bitmasks for these bits within the
#define status_ERL (1 << 2) /* Error level */
#define status_RP (1 << 27) /* Reduced Power mode */
-#define config_EP_mask (0xF)
-#define config_EP_shift (27)
-#define config_EP_D (0x0)
-#define config_EP_DxxDxx (0x6)
-
-#define config_BE (1 << 15)
-
#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
#if defined(HASFPU)
the register update to be delayed for a single instruction
cycle. */
#define PSLOTS (5) /* Maximum number of instruction cycles */
-int pending_in;
-int pending_out;
-int pending_total;
-int pending_slot_count[PSLOTS];
-int pending_slot_reg[PSLOTS];
-ut_reg pending_slot_value[PSLOTS];
+static int pending_in;
+static int pending_out;
+static int pending_total;
+static int pending_slot_count[PSLOTS];
+static int pending_slot_reg[PSLOTS];
+static ut_reg pending_slot_value[PSLOTS];
+
+/*---------------------------------------------------------------------------*/
+/*-- GDB simulator interface ------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+
+static void dotrace PARAMS((FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...));
+static void sim_warning PARAMS((char *fmt,...));
+extern void sim_error PARAMS((char *fmt,...));
+static void set_endianness PARAMS((void));
+static void ColdReset PARAMS((void));
+static int AddressTranslation PARAMS((uword64 vAddr,int IorD,int LorS,uword64 *pAddr,int *CCA,int host,int raw));
+static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64 pAddr,uword64 vAddr,int raw));
+static uword64 LoadMemory PARAMS((int CCA,int AccessLength,uword64 pAddr,uword64 vAddr,int IorD,int raw));
+static void SignalException PARAMS((int exception,...));
+static void simulate PARAMS((void));
+static long getnum PARAMS((char *value));
+extern void sim_size PARAMS((unsigned int newsize));
+extern void sim_set_profile PARAMS((int frequency));
+static unsigned int power2 PARAMS((unsigned int value));
+
+/*---------------------------------------------------------------------------*/
/* The following are not used for MIPS IV onwards: */
#define PENDING_FILL(r,v) {\
-printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\
+/* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); */\
if (pending_slot_reg[pending_in] != (LAST_EMBED_REGNUM + 1))\
- callback->printf_filtered(callback,"SIM Warning: Attempt to over-write pending value\n");\
+ sim_warning("Attempt to over-write pending value");\
pending_slot_count[pending_in] = 2;\
pending_slot_reg[pending_in] = (r);\
pending_slot_value[pending_in] = (uword64)(v);\
-printf("DBG: FILL reg %d value = 0x%08X%08X\n",(r),WORD64HI(v),WORD64LO(v));\
+/*printf("DBG: FILL reg %d value = 0x%08X%08X\n",(r),WORD64HI(v),WORD64LO(v));*/\
pending_total++;\
pending_in++;\
if (pending_in == PSLOTS)\
pending_in = 0;\
-printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\
+/*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);*/\
}
-int LLBIT = 0;
+static int LLBIT = 0;
/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
read-write instructions. It is set when a linked load occurs. It is
tested and cleared by the conditional store. It is cleared (during
be atomic. In particular, it is cleared by exception return
instructions. */
-int HIACCESS = 0;
-int LOACCESS = 0;
+static int HIACCESS = 0;
+static int LOACCESS = 0;
/* The HIACCESS and LOACCESS counts are used to ensure that
corruptions caused by using the HI or LO register to close to a
following operation are spotted. */
+static ut_reg HLPC = 0;
+/* ??? The 4300 and a few other processors have interlocks on hi/lo register
+ reads, and hence do not have this problem. To avoid spurious warnings,
+ we just disable this always. */
+#if 1
+#define CHECKHILO(s)
+#else
/* If either of the preceding two instructions have accessed the HI or
LO registers, then the values they see should be
undefined. However, to keep the simulator world simple, we just let
them use the value read and raise a warning to notify the user: */
#define CHECKHILO(s) {\
if ((HIACCESS != 0) || (LOACCESS != 0))\
- callback->printf_filtered(callback,"SIM Warning: %s over-writing HI and LO registers values\n",(s));\
- /* Set the access counts, since we are about\
- to update the HI and LO registers: */\
- HIACCESS = LOACCESS = 3; /* 3rd instruction will be safe */\
+ sim_warning("%s over-writing HI and LO registers values (PC = 0x%08X%08X HLPC = 0x%08X%08X)\n",(s),(unsigned int)(PC>>32),(unsigned int)(PC&0xFFFFFFFF),(unsigned int)(HLPC>>32),(unsigned int)(HLPC&0xFFFFFFFF));\
}
+#endif
/* NOTE: We keep the following status flags as bit values (1 for true,
0 for false). This allows them to be used in binary boolean
/* Hardware configuration. Affects endianness of LoadMemory and
StoreMemory and the endianness of Kernel and Supervisor mode
execution. The value is 0 for little-endian; 1 for big-endian. */
-#define BigEndianMem ((CONFIG & config_BE) ? 1 : 0)
-/* NOTE: Problems will occur if the simulator memory model does not
- match the host program expectation. i.e. if the host is writing
- big-endian values to a little-endian memory model. */
+#define BigEndianMem ((state & simBE) ? 1 : 0)
+
+/* ByteSwapMem */
+/* This is true if the host and target have different endianness. */
+#define ByteSwapMem (!(state & simHOSTBE) != !(state & simBE))
/* ReverseEndian */
/* This mode is selected if in User mode with the RE bit being set in
/* The endianness for load and store instructions (0=little;1=big). In
User mode this endianness may be switched by setting the state_RE
bit in the SR register. Thus, BigEndianCPU may be computed as
- (BigEndienMem EOR ReverseEndian). */
+ (BigEndianMem EOR ReverseEndian). */
#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
#if !defined(FASTSIM) || defined(PROFILE)
/* At the moment these values will be the same, since we do not have
access to the pipeline cycle count information from the simulator
engine. */
-unsigned int instruction_fetches = 0;
-unsigned int instruction_fetch_overflow = 0;
-unsigned int pipeline_ticks = 0;
+static unsigned int instruction_fetches = 0;
+static unsigned int instruction_fetch_overflow = 0;
+static unsigned int pipeline_ticks = 0;
#endif
/* Flags in the "state" variable: */
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
#define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
#define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
+#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
+#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
-unsigned int state = 0;
-unsigned int rcexit = 0; /* _exit() reason code holder */
+static unsigned int state = 0;
+static unsigned int rcexit = 0; /* _exit() reason code holder */
#define DELAYSLOT() {\
- if (state & simDELAYSLOT) callback->printf_filtered(callback,"SIM Warning: Delay slot already activated (branch in delay slot?)\n");\
+ if (state & simDELAYSLOT)\
+ sim_warning("Delay slot already activated (branch in delay slot?)");\
state |= simDELAYSLOT;\
}
+#define JALDELAYSLOT() {\
+ DELAYSLOT ();\
+ state |= simJALDELAYSLOT;\
+ }
+
#define NULLIFY() {\
state &= ~simDELAYSLOT;\
state |= simSKIPNEXT;\
}
+#define INDELAYSLOT() ((state & simDELAYSLOT) != 0)
+#define INJALDELAYSLOT() ((state & simJALDELAYSLOT) != 0)
+
#define K0BASE (0x80000000)
#define K0SIZE (0x20000000)
#define K1BASE (0xA0000000)
#define K1SIZE (0x20000000)
/* Very simple memory model to start with: */
-unsigned char *membank = NULL;
-ut_reg membank_base = K1BASE;
-unsigned membank_size = (1 << 20); /* (16 << 20); */ /* power-of-2 */
+static unsigned char *membank = NULL;
+static ut_reg membank_base = K1BASE;
+/* The ddb.ld linker script loads text at K1BASE+1MB, and the idt.ld linker
+ script loads text at K1BASE+128KB. We allocate 2MB, so that we have a
+ minimum of 1 MB available for the user process. We must have memory
+ above _end in order for sbrk to work. */
+static unsigned membank_size = (2 << 20);
/* Simple run-time monitor support */
-unsigned char *monitor = NULL;
-ut_reg monitor_base = 0xBFC00000;
-unsigned monitor_size = (1 << 11); /* power-of-2 */
+static unsigned char *monitor = NULL;
+static ut_reg monitor_base = 0xBFC00000;
+static unsigned monitor_size = (1 << 11); /* power-of-2 */
+
+static char *logfile = NULL; /* logging disabled by default */
+static FILE *logfh = NULL;
#if defined(TRACE)
-char *tracefile = "trace.din"; /* default filename for trace log */
-FILE *tracefh = NULL;
+static char *tracefile = "trace.din"; /* default filename for trace log */
+static FILE *tracefh = NULL;
+static void open_trace PARAMS((void));
#endif /* TRACE */
#if defined(PROFILE)
-unsigned profile_frequency = 256;
-unsigned profile_nsamples = (128 << 10);
-unsigned short *profile_hist = NULL;
-ut_reg profile_minpc;
-ut_reg profile_maxpc;
-int profile_shift = 0; /* address shift amount */
+static unsigned profile_frequency = 256;
+static unsigned profile_nsamples = (128 << 10);
+static unsigned short *profile_hist = NULL;
+static ut_reg profile_minpc;
+static ut_reg profile_maxpc;
+static int profile_shift = 0; /* address shift amount */
#endif /* PROFILE */
/* The following are used to provide shortcuts to the required version
typedef uword64 (*fnptr_read_long) PARAMS((unsigned char *memory));
typedef uword64 (*fnptr_swap_long) PARAMS((uword64 data));
-fnptr_read_word host_read_word;
-fnptr_read_long host_read_long;
-fnptr_swap_word host_swap_word;
-fnptr_swap_long host_swap_long;
+static fnptr_read_word host_read_word;
+static fnptr_read_long host_read_long;
+static fnptr_swap_word host_swap_word;
+static fnptr_swap_long host_swap_long;
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
-static void dotrace PARAMS((FILE *tracefh,int type,unsigned int address,int width,char *comment,...));
-extern void sim_error PARAMS((char *fmt,...));
-static void ColdReset PARAMS((void));
-static int AddressTranslation PARAMS((uword64 vAddr,int IorD,int LorS,uword64 *pAddr,int *CCA,int host,int raw));
-static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64 pAddr,uword64 vAddr,int raw));
-static uword64 LoadMemory PARAMS((int CCA,int AccessLength,uword64 pAddr,uword64 vAddr,int IorD,int raw));
-static void SignalException PARAMS((int exception,...));
-static void simulate PARAMS((void));
-static long getnum PARAMS((char *value));
-extern void sim_size PARAMS((unsigned int newsize));
-extern void sim_set_profile PARAMS((int frequency));
-static unsigned int power2 PARAMS((unsigned int value));
-
-/*---------------------------------------------------------------------------*/
-
void
sim_open (args)
char *args;
state |= simHOSTBE; /* big-endian host */
}
+ set_endianness ();
+
#if defined(HASFPU)
/* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
and DOUBLE binary formats. This is a bit nasty, requiring that we
int argc;
static struct option cmdline[] = {
{"help", 0,0,'h'},
+ {"log", 1,0,'l'},
{"name", 1,0,'n'},
{"profile", 0,0,'p'},
{"size", 1,0,'s'},
switch (c) {
case 'h':
callback->printf_filtered(callback,"Usage:\n\t\
-target sim [-h] [--name=<model>] [--size=<amount>]");
+target sim [-h] [--
log=<file>] [--name=<model>] [--size=<amount>]");
#if defined(TRACE)
callback->printf_filtered(callback," [-t [--tracefile=<name>]]");
#endif /* TRACE */
callback->printf_filtered(callback,"\n");
break;
+ case 'l':
+ if (optarg != NULL) {
+ char *tmp;
+ tmp = (char *)malloc(strlen(optarg) + 1);
+ if (tmp == NULL)
+ callback->printf_filtered(callback,"Failed to allocate buffer for logfile name \"%s\"\n",optarg);
+ else {
+ strcpy(tmp,optarg);
+ logfile = tmp;
+ }
+ }
+ break;
+
case 'n':
callback->printf_filtered(callback,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg);
break;
}
}
+#if 0
if (optind < argc) {
callback->printf_filtered(callback,"Warning: Ignoring spurious non-option arguments ");
while (optind < argc)
callback->printf_filtered(callback,"\"%s\" ",argv[optind++]);
callback->printf_filtered(callback,"\n");
}
+#endif
freeargv(argv);
}
+ if (logfile != NULL) {
+ if (strcmp(logfile,"-") == 0)
+ logfh = stdout;
+ else {
+ logfh = fopen(logfile,"wb+");
+ if (logfh == NULL) {
+ callback->printf_filtered(callback,"Failed to create file \"%s\", writing log information to stderr.\n",tracefile);
+ logfh = stderr;
+ }
+ }
+ }
+
/* If the host has "mmap" available we could use it to provide a
very large virtual address space for the simulator, since memory
would only be allocated within the "mmap" space as it is
if (!monitor) {
fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size);
} else {
- int loop;
+ unsigned loop;
/* Entry into the IDT monitor is via fixed address vectors, and
not using machine instructions. To avoid clashing with use of
the MIPS TRAP system, we place our own (simulator specific)
case 8: /* cliexit */
value = 17;
break;
+
+ case 11: /* flush_cache */
+ value = 28;
+ break;
}
- value = (monitor_base + (value * 8));
+ /* FIXME - should monitor_base be SIM_ADDR?? */
+ value = ((unsigned int)monitor_base + (value * 8));
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
else
- callback->printf_filtered(callback,"Failed to write to monitor space 0x%08X%08X\n",WORD64HI(vaddr),WORD64LO(vaddr));
+ sim_error("Failed to write to monitor space 0x%08X%08X",WORD64HI(vaddr),WORD64LO(vaddr));
}
}
#if defined(TRACE)
- if (state & simTRACE) {
- tracefh = fopen(tracefile,"wb+");
- if (tracefh == NULL) {
- callback->printf_filtered(callback,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
- tracefh = stderr;
- }
- }
+ if (state & simTRACE)
+ open_trace();
#endif /* TRACE */
return;
}
+#if defined(TRACE)
+static void
+open_trace()
+{
+ tracefh = fopen(tracefile,"wb+");
+ if (tracefh == NULL)
+ {
+ sim_warning("Failed to create file \"%s\", writing trace information to stderr.",tracefile);
+ tracefh = stderr;
+ }
+}
+#endif /* TRACE */
+
/* For the profile writing, we write the data in the host
endianness. This unfortunately means we are assuming that the
profile file we create is processed on the same host executing the
buff[3] = ((val >> 24) & 0xFF);
}
if (fwrite(buff,4,1,fh) != 1) {
- callback->printf_filtered(callback,"Failed to write 4bytes to the profile file\n");
+ sim_warning("Failed to write 4bytes to the profile file");
res = 0;
}
return(res);
buff[1] = ((val >> 8) & 0xFF);
}
if (fwrite(buff,2,1,fh) != 1) {
- callback->printf_filtered(callback,"Failed to write 2bytes to the profile file\n");
+ sim_warning("Failed to write 2bytes to the profile file");
res = 0;
}
return(res);
if ((state & simPROFILE) && (profile_hist != NULL)) {
unsigned short *p = profile_hist;
FILE *pf = fopen("gmon.out","wb");
- int loop;
+ unsigned loop;
if (pf == NULL)
- callback->printf_filtered(callback,"Failed to open \"gmon.out\" profile file\n");
+ sim_warning("Failed to open \"gmon.out\" profile file");
else {
int ok;
#ifdef DEBUG
#endif /* PROFILE */
#if defined(TRACE)
- if (tracefh != stderr)
+ if (tracefh != NULL && tracefh != stderr)
fclose(tracefh);
+ tracefh = NULL;
state &= ~simTRACE;
#endif /* TRACE */
+ if (logfh != NULL && logfh != stdout && logfh != stderr)
+ fclose(logfh);
+ logfh = NULL;
+
if (membank)
free(membank); /* cfree not available on all hosts */
membank = NULL;
}
void
-sim_resume (step,signal)
- int step, signal;
+control_c (sig, code, scp, addr)
+ int sig;
+ int code;
+ char *scp;
+ char *addr;
+{
+ state |= (simSTOP | simSIGINT);
+}
+
+void
+sim_resume (step,signal_number)
+ int step, signal_number;
{
+ void (*prev) ();
+
#ifdef DEBUG
- printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step,signal,membank);
+ printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step,signal_number,membank);
#endif /* DEBUG */
if (step)
/* Start executing instructions from the current state (set
explicitly by register updates, or by sim_create_inferior): */
+ prev = signal (SIGINT, control_c);
+
simulate();
+
+ signal (SIGINT, prev);
+
return;
}
numbering one. We need to know what the width of each logical
register number is for the architecture being simulated. */
if (register_widths[rn] == 0)
- callback->printf_filtered(callback,"Warning: Invalid register width for %d (register store ignored)\n",rn);
+ sim_warning("Invalid register width for %d (register store ignored)",rn);
else {
if (register_widths[rn] == 32)
registers[rn] = host_read_word(memory);
#endif /* DEBUG */
if (register_widths[rn] == 0)
- callback->printf_filtered(callback,"Warning: Invalid register width for %d (register fetch ignored)\n",rn);
+ sim_warning("Invalid register width for %d (register fetch ignored)",rn);
else {
if (register_widths[rn] == 32)
- *((unsigned int *)memory) = host_swap_word(registers[rn] & 0xFFFFFFFF);
+ *((unsigned int *)memory) = host_swap_word((unsigned int)(registers[rn] & 0xFFFFFFFF));
else /* 64bit register */
*((uword64 *)memory) = host_swap_long(registers[rn]);
}
break;
}
} else if (state & simEXIT) {
+#if 0
printf("DBG: simEXIT (%d)\n",rcexit);
+#endif
*reason = sim_exited;
*sigrc = rcexit;
+ } else if (state & simSIGINT) {
+ *reason = sim_stopped;
+ *sigrc = SIGINT;
} else { /* assume single-stepping */
*reason = sim_stopped;
*sigrc = SIGTRAP;
}
- state &= ~(simEXCEPTION | simEXIT);
+ state &= ~(simEXCEPTION | simEXIT | simSIGINT);
return;
}
callback->printf_filtered(callback,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT ? 64 : 32));
- callback->printf_filtered(callback,"%s endian memory model\n",(BigEndianMem ? "Big" : "Little"));
+ callback->printf_filtered(callback,"%s endian memory model\n",(state & simBE ? "Big" : "Little"));
callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%08X%08X\n",(unsigned int)membank_size,WORD64HI(membank_base),WORD64LO(membank_base));
used by other clients of the simulator. */
if (argv || env) {
+#if 0 /* def DEBUG */
callback->printf_filtered(callback,"sim_create_inferior() : passed arguments ignored\n");
-#if 1 /* def DEBUG */
{
char **cptr;
for (cptr = argv; (cptr && *cptr); cptr++)
return;
}
-int
+ut_reg
sim_get_quit_code ()
{
/* The standard MIPS PCS (Procedure Calling Standard) uses V0(r2) as
else
profile_hist = (unsigned short *)realloc(profile_hist,bsize);
if (profile_hist == NULL) {
- callback->printf_filtered(callback,"Failed to allocate VM for profiling buffer (0x%08X bytes)\n",bsize);
+ sim_warning("Failed to allocate VM for profiling buffer (0x%08X bytes)",bsize);
state &= ~simPROFILE;
}
}
{
char *new;
/* Used by "run", and internally, to set the simulated memory size */
+ if (newsize == 0) {
+ callback->printf_filtered(callback,"Zero not valid: Memory size still 0x%08X bytes\n",membank_size);
+ return;
+ }
newsize = power2(newsize);
if (membank == NULL)
new = (char *)calloc(64,(membank_size / 64));
new = (char *)realloc(membank,newsize);
if (new == NULL) {
if (membank == NULL)
- callback->printf_filtered(callback,"Not enough VM for simulation memory of 0x%08X bytes\n",membank_size);
+ sim_error("Not enough VM for simulation memory of 0x%08X bytes",membank_size);
else
- callback->printf_filtered(callback,"Failed to resize memory (still 0x%08X bytes)\n",membank_size);
+ sim_warning("Failed to resize memory (still 0x%08X bytes)",membank_size);
} else {
membank_size = (unsigned)newsize;
membank = new;
- callback->printf_filtered(callback,"Memory size now 0x%08X bytes\n",membank_size);
#if defined(PROFILE)
/* Ensure that we sample across the new memory range */
sim_set_profile_size(profile_nsamples);
#if defined(TRACE)
/* Ensure tracing is enabled, if available */
- if (tracefh != NULL)
- state |= simTRACE;
+ if (tracefh == NULL)
+ {
+ open_trace();
+ state |= simTRACE;
+ }
#endif /* TRACE */
state &= ~(simSTOP | simSTEP); /* execute until event */
switch (reason) {
case 6: /* int open(char *path,int flags) */
{
- const char *ptr;
uword64 paddr;
int cca;
if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
V0 = callback->open(callback,(char *)((int)paddr),(int)A1);
else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ sim_error("Attempt to pass pointer that does not reference simulated memory");
}
break;
case 7: /* int read(int file,char *ptr,int len) */
{
- const char *ptr;
uword64 paddr;
int cca;
if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
V0 = callback->read(callback,(int)A0,(char *)((int)paddr),(int)A2);
else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ sim_error("Attempt to pass pointer that does not reference simulated memory");
}
break;
case 8: /* int write(int file,char *ptr,int len) */
{
- const char *ptr;
uword64 paddr;
int cca;
if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
V0 = callback->write(callback,(int)A0,(const char *)((int)paddr),(int)A2);
else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ sim_error("Attempt to pass pointer that does not reference simulated memory");
}
break;
{
char tmp;
if (callback->read_stdin(callback,&tmp,sizeof(char)) != sizeof(char)) {
- callback->printf_filtered(callback,"WARNING: Invalid return from character read\n");
- V0 = -1;
+ sim_error("Invalid return from character read");
+ V0 = (ut_reg)-1;
}
else
- V0 = tmp;
+ V0 = (ut_reg)tmp;
}
break;
break;
case 17: /* void _exit() */
- callback->printf_filtered(callback,"sim_monitor(17): _exit(int reason) to be coded\n");
+ sim_warning("sim_monitor(17): _exit(int reason) to be coded");
state |= (simSTOP | simEXIT); /* stop executing code */
rcexit = (unsigned int)(A0 & 0xFFFFFFFF);
break;
+ case 28 : /* PMON flush_cache */
+ break;
+
case 55: /* void get_mem_info(unsigned int *ptr) */
/* in: A0 = pointer to three word memory location */
/* out: [A0 + 0] = size */
failed = -1;
if (failed)
- callback->printf_filtered(callback,"WARNING: Invalid pointer passed into monitor call\n");
+ sim_error("Invalid pointer passed into monitor call");
}
break;
/* A2 = optional argument 2 */
/* A3 = optional argument 3 */
/* out: void */
+ /* The following is based on the PMON printf source */
{
uword64 paddr;
int cca;
- if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
- callback->printf_filtered(callback,(char *)((int)paddr),(int)A1,(int)A2,(int)A2);
- else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ /* This isn't the quickest way, since we call the host print
+ routine for every character almost. But it does avoid
+ having to allocate and manage a temporary string buffer. */
+ if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) {
+ char *s = (char *)((int)paddr);
+ ut_reg *ap = &A1; /* 1st argument */
+ /* TODO: Include check that we only use three arguments (A1, A2 and A3) */
+ for (; *s;) {
+ if (*s == '%') {
+ char tmp[40];
+ enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
+ int width = 0, trunc = 0, haddot = 0, longlong = 0;
+ int base = 10;
+ s++;
+ for (; *s; s++) {
+ if (strchr ("dobxXulscefg%", *s))
+ break;
+ else if (*s == '-')
+ fmt = FMT_LJUST;
+ else if (*s == '0')
+ fmt = FMT_RJUST0;
+ else if (*s == '~')
+ fmt = FMT_CENTER;
+ else if (*s == '*') {
+ if (haddot)
+ trunc = (int)*ap++;
+ else
+ width = (int)*ap++;
+ } else if (*s >= '1' && *s <= '9') {
+ char *t;
+ unsigned int n;
+ for (t = s; isdigit (*s); s++);
+ strncpy (tmp, t, s - t);
+ tmp[s - t] = '\0';
+ n = (unsigned int)strtol(tmp,NULL,10);
+ if (haddot)
+ trunc = n;
+ else
+ width = n;
+ s--;
+ } else if (*s == '.')
+ haddot = 1;
+ }
+ if (*s == '%') {
+ callback->printf_filtered(callback,"%%");
+ } else if (*s == 's') {
+ if ((int)*ap != 0) {
+ if (AddressTranslation(*ap++,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) {
+ char *p = (char *)((int)paddr);;
+ callback->printf_filtered(callback,p);
+ } else {
+ ap++;
+ sim_error("Attempt to pass pointer that does not reference simulated memory");
+ }
+ }
+ else
+ callback->printf_filtered(callback,"(null)");
+ } else if (*s == 'c') {
+ int n = (int)*ap++;
+ callback->printf_filtered(callback,"%c",n);
+ } else {
+ if (*s == 'l') {
+ if (*++s == 'l') {
+ longlong = 1;
+ ++s;
+ }
+ }
+ if (strchr ("dobxXu", *s)) {
+ word64 lv = (word64) *ap++;
+ if (*s == 'b')
+ callback->printf_filtered(callback,"<binary not supported>");
+ else {
+ sprintf(tmp,"%%%s%c",longlong ? "ll" : "",*s);
+ if (longlong)
+ callback->printf_filtered(callback,tmp,lv);
+ else
+ callback->printf_filtered(callback,tmp,(int)lv);
+ }
+ } else if (strchr ("eEfgG", *s)) {
+#ifdef _MSC_VER /* MSVC version 2.x can't convert from uword64 directly */
+ double dbl = (double)((word64)*ap++);
+#else
+ double dbl = (double)*ap++;
+#endif
+ sprintf(tmp,"%%%d.%d%c",width,trunc,*s);
+ callback->printf_filtered(callback,tmp,dbl);
+ trunc = 0;
+ }
+ }
+ s++;
+ } else
+ callback->printf_filtered(callback,"%c",*s++);
+ }
+ } else
+ sim_error("Attempt to pass pointer that does not reference simulated memory");
}
break;
default:
- callback->printf_filtered(callback,"TODO: sim_monitor(%d) : PC = 0x%08X%08X\n",reason,WORD64HI(IPC),WORD64LO(IPC));
- callback->printf_filtered(callback,"(Arguments : A0 = 0x%08X%08X : A1 = 0x%08X%08X : A2 = 0x%08X%08X : A3 = 0x%08X%08X)\n",WORD64HI(A0),WORD64LO(A0),WORD64HI(A1),WORD64LO(A1),WORD64HI(A2),WORD64LO(A2),WORD64HI(A3),WORD64LO(A3));
+ sim_warning("TODO: sim_monitor(%d) : PC = 0x%08X%08X",reason,WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("(Arguments : A0 = 0x%08X%08X : A1 = 0x%08X%08X : A2 = 0x%08X%08X : A3 = 0x%08X%08X)",WORD64HI(A0),WORD64LO(A0),WORD64HI(A1),WORD64LO(A1),WORD64HI(A2),WORD64LO(A2),WORD64HI(A3),WORD64LO(A3));
break;
}
return;
}
+/* Store a word into memory. */
+
+static void
+store_word (vaddr, val)
+ uword64 vaddr;
+ t_reg val;
+{
+ uword64 paddr;
+ int uncached;
+
+ if ((vaddr & 3) != 0)
+ SignalException (AddressStore);
+ else
+ {
+ if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
+ isTARGET, isREAL))
+ {
+ const uword64 mask = 7;
+ uword64 memval;
+ unsigned int byte;
+
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
+ byte = (vaddr & mask) ^ (BigEndianCPU << 2);
+ memval = ((uword64) val) << (8 * byte);
+ StoreMemory (uncached, AccessLength_WORD, memval, paddr, vaddr,
+ isREAL);
+ }
+ }
+}
+
+/* Load a word from memory. */
+
+static t_reg
+load_word (vaddr)
+ uword64 vaddr;
+{
+ if ((vaddr & 3) != 0)
+ SignalException (AddressLoad);
+ else
+ {
+ uword64 paddr;
+ int uncached;
+
+ if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
+ isTARGET, isREAL))
+ {
+ const uword64 mask = 0x7;
+ const unsigned int reverse = ReverseEndian ? 1 : 0;
+ const unsigned int bigend = BigEndianCPU ? 1 : 0;
+ uword64 memval;
+ unsigned int byte;
+
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
+ memval = LoadMemory (uncached, AccessLength_WORD, paddr, vaddr,
+ isDATA, isREAL);
+ byte = (vaddr & mask) ^ (bigend << 2);
+ return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
+ }
+ }
+
+ return 0;
+}
+
+/* Simulate the mips16 entry and exit pseudo-instructions. These
+ would normally be handled by the reserved instruction exception
+ code, but for ease of simulation we just handle them directly. */
+
+static void
+mips16_entry (insn)
+ unsigned int insn;
+{
+ int aregs, sregs, rreg;
+
+ aregs = (insn & 0x700) >> 8;
+ sregs = (insn & 0x0c0) >> 6;
+ rreg = (insn & 0x020) >> 5;
+
+ /* These should be checked by the caller. */
+ if (aregs == 5 || aregs == 6 || sregs == 3)
+ abort ();
+
+ if (aregs != 7)
+ {
+ int i;
+ t_reg tsp;
+
+ /* This is the entry pseudo-instruction. */
+
+ for (i = 0; i < aregs; i++)
+ store_word ((uword64) (SP + 4 * i), registers[i + 4]);
+
+ tsp = SP;
+ SP -= 32;
+
+ if (rreg)
+ {
+ tsp -= 4;
+ store_word ((uword64) tsp, RA);
+ }
+
+ for (i = 0; i < sregs; i++)
+ {
+ tsp -= 4;
+ store_word ((uword64) tsp, registers[16 + i]);
+ }
+ }
+ else
+ {
+ int i;
+ t_reg tsp;
+
+ /* This is the exit pseudo-instruction. */
+
+ tsp = SP + 32;
+
+ if (rreg)
+ {
+ tsp -= 4;
+ RA = load_word ((uword64) tsp);
+ }
+
+ for (i = 0; i < sregs; i++)
+ {
+ tsp -= 4;
+ registers[i + 16] = load_word ((uword64) tsp);
+ }
+
+ SP += 32;
+
+ PC = RA;
+ }
+}
+
+void
+sim_warning(char *fmt,...)
+{
+ char buf[256];
+ va_list ap;
+
+ va_start (ap,fmt);
+ vsprintf (buf, fmt, ap);
+ va_end (ap);
+
+ if (logfh != NULL) {
+ fprintf(logfh,"SIM Warning: %s\n", buf);
+ } else {
+ callback->printf_filtered(callback,"SIM Warning: %s\n", buf);
+ }
+ /* This used to call SignalException with a SimulatorFault, but that causes
+ the simulator to exit, and that is inappropriate for a warning. */
+ return;
+}
+
void
-sim_error(fmt)
- char *fmt;
+sim_error(char *fmt,...)
{
+ char buf[256];
va_list ap;
- va_start(ap,fmt);
- callback->printf_filtered(callback,"SIM Error: ");
- callback->printf_filtered(callback,fmt,ap);
- va_end(ap);
- SignalException(SimulatorFault,"");
+
+ va_start (ap,fmt);
+ vsprintf (buf, fmt, ap);
+ va_end (ap);
+
+ callback->printf_filtered(callback,"SIM Error: %s", buf);
+ SignalException (SimulatorFault, buf);
return;
}
to construct an end product, rather than a processor). They
currently have an ARM version of their tool called ChARM. */
+
static
-void dotrace(tracefh,type,address,width,comment)
- FILE *tracefh;
- int type;
- unsigned int address;
- int width;
- char *comment;
+void dotrace(FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
{
if (state & simTRACE) {
va_list ap;
- fprintf(tracefh,"%d %08x ; width %d ; ",type,address,width);
+ fprintf(tracefh,"%d %08x%08x ; width %d ; ",
+ type,
+ sizeof (address) > 4 ? (unsigned long)(address>>32) : 0,
+ (unsigned long)(address&0xffffffff),width);
va_start(ap,comment);
- fprintf(tracefh,comment,ap);
+ vfprintf(tracefh,comment,ap);
va_end(ap);
fprintf(tracefh,"\n");
}
simulation, at the cost of increasing the image and source size. */
static unsigned int
-xfer_direct_word(memory)
- unsigned char *memory;
+xfer_direct_word(unsigned char *memory)
{
return *((unsigned int *)memory);
}
static uword64
-xfer_direct_long(memory)
- unsigned char *memory;
+xfer_direct_long(unsigned char *memory)
{
return *((uword64 *)memory);
}
static unsigned int
-swap_direct_word(data)
- unsigned int data;
+swap_direct_word(unsigned int data)
{
return data;
}
static uword64
-swap_direct_long(data)
- uword64 data;
+swap_direct_long(uword64 data)
{
return data;
}
static unsigned int
-xfer_big_word(memory)
- unsigned char *memory;
+xfer_big_word(unsigned char *memory)
{
return ((memory[0] << 24) | (memory[1] << 16) | (memory[2] << 8) | memory[3]);
}
static uword64
-xfer_big_long(memory)
- unsigned char *memory;
+xfer_big_long(unsigned char *memory)
{
return (((uword64)memory[0] << 56) | ((uword64)memory[1] << 48)
| ((uword64)memory[2] << 40) | ((uword64)memory[3] << 32)
- | (memory[4] << 24) | (memory[5] << 16) | (memory[6] << 8) | memory[7]);
+ | ((uword64)memory[4] << 24) | ((uword64)memory[5] << 16)
+ | ((uword64)memory[6] << 8) | ((uword64)memory[7]));
}
static unsigned int
-xfer_little_word(memory)
- unsigned char *memory;
+xfer_little_word(unsigned char *memory)
{
return ((memory[3] << 24) | (memory[2] << 16) | (memory[1] << 8) | memory[0]);
}
static uword64
-xfer_little_long(memory)
- unsigned char *memory;
+xfer_little_long(unsigned char *memory)
{
return (((uword64)memory[7] << 56) | ((uword64)memory[6] << 48)
| ((uword64)memory[5] << 40) | ((uword64)memory[4] << 32)
- | (memory[3] << 24) | (memory[2] << 16) | (memory[1] << 8) | memory[0]);
+ | ((uword64)memory[3] << 24) | ((uword64)memory[2] << 16)
+ | ((uword64)memory[1] << 8) | (uword64)memory[0]);
}
static unsigned int
-swap_word(data)
- unsigned int data;
+swap_word(unsigned int data)
{
unsigned int result;
- result = data ^ ((data << 16) | (data >> 16));
- result &= ~0x00FF0000;
- data = (data << 24) | (data >> 8);
- return data ^ (result >> 8);
+ result = (((data & 0xff) << 24) | ((data & 0xff00) << 8)
+ | ((data >> 8) & 0xff00) | ((data >> 24) & 0xff));
+ return result;
}
static uword64
-swap_long(data)
- uword64 data;
+swap_long(uword64 data)
{
unsigned int tmphi = WORD64HI(data);
unsigned int tmplo = WORD64LO(data);
/*-- simulator engine -------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
+static void
+set_endianness ()
+{
+ /* In reality this check should be performed at various points
+ within the simulation, since it is possible to change the
+ endianness of user programs. However, we perform the check here
+ to ensure that the start-of-day values agree. */
+ if (target_byte_order == 4321)
+ state |= simBE;
+
+ /* ??? This is a lot more code than is necessary to solve the problem.
+ It would be simpler to handle this like the SH simulator. */
+ if (!ByteSwapMem) {
+ host_read_word = xfer_direct_word;
+ host_read_long = xfer_direct_long;
+ host_swap_word = swap_direct_word;
+ host_swap_long = swap_direct_long;
+ } else if (state & simHOSTBE) {
+ host_read_word = xfer_little_word;
+ host_read_long = xfer_little_long;
+ host_swap_word = swap_word;
+ host_swap_long = swap_long;
+ } else { /* HOST little-endian */
+ host_read_word = xfer_big_word;
+ host_read_long = xfer_big_long;
+ host_swap_word = swap_word;
+ host_swap_long = swap_long;
+ }
+}
+
static void
ColdReset()
{
SR &= ~(status_SR | status_TS | status_RP);
SR |= (status_ERL | status_BEV);
- /* VR4300 starts in Big-Endian mode */
- CONFIG &= ~(config_EP_mask << config_EP_shift);
- CONFIG |= ((config_EP_D << config_EP_shift) | config_BE);
- /* TODO: The VR4300 CONFIG register is not modelled fully at the moment */
#if defined(HASFPU) && (GPRLEN == (64))
/* Cheat and allow access to the complete register set immediately: */
}
#endif /* HASFPU */
- /* In reality this check should be performed at various points
- within the simulation, since it is possible to change the
- endianness of user programs. However, we perform the check here
- to ensure that the start-of-day values agree: */
- state |= (BigEndianCPU ? simBE : 0);
- if ((target_byte_order == 1234) != !(state & simBE)) {
- fprintf(stderr,"ColdReset: GDB (%s) and simulator (%s) do not agree on target endianness\n",
- target_byte_order == 1234 ? "little" : "big",
- state & simBE ? "big" : "little");
- exit(1);
- }
-
- if ((state & simHOSTBE) == (state & simBE)) {
- host_read_word = xfer_direct_word;
- host_read_long = xfer_direct_long;
- host_swap_word = swap_direct_word;
- host_swap_long = swap_direct_long;
- } else if (state & simHOSTBE) {
- host_read_word = xfer_little_word;
- host_read_long = xfer_little_long;
- host_swap_word = swap_word;
- host_swap_long = swap_long;
- } else { /* HOST little-endian */
- host_read_word = xfer_big_word;
- host_read_long = xfer_big_long;
- host_swap_word = swap_word;
- host_swap_long = swap_long;
- }
-
return;
}
if (host)
*pAddr = (int)&monitor[((unsigned int)(vAddr - monitor_base) & (monitor_size - 1))];
} else {
-#if 1 /* def DEBUG */
- callback->printf_filtered(callback,"Failed: AddressTranslation(0x%08X%08X,%s,%s,...) IPC = 0x%08X%08X\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),WORD64HI(IPC),WORD64LO(IPC));
+#ifdef DEBUG
+ sim_warning("Failed: AddressTranslation(0x%08X%08X,%s,%s,...) IPC = 0x%08X%08X",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),WORD64HI(IPC),WORD64LO(IPC));
#endif /* DEBUG */
res = 0; /* AddressTranslation has failed */
- *pAddr = -1;
+ *pAddr = (SIM_ADDR)-1;
if (!raw) /* only generate exceptions on real memory transfers */
SignalException((LorS == isSTORE) ? AddressStore : AddressLoad);
+#ifdef DEBUG
else
- callback->printf_filtered(callback,"AddressTranslation for %s %s from 0x%08X%08X failed\n",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),WORD64HI(vAddr),WORD64LO(vAddr));
+ /* This is a normal occurance during gdb operation, for instance trying
+ to print parameters at function start before they have been setup,
+ and hence we should not print a warning except when debugging the
+ simulator. */
+ sim_warning("AddressTranslation for %s %s from 0x%08X%08X failed",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),WORD64HI(vAddr),WORD64LO(vAddr));
+#endif
}
return(res);
#if defined(WARN_MEM)
if (CCA != uncached)
- callback->printf_filtered(callback,"SIM Warning: LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
+ sim_warning("LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)",CCA);
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) {
/* In reality this should be a Bus Error */
- sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength,WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%08X%08X\n",AccessLength,(LOADDRMASK + 1)<<2,WORD64HI(pAddr),WORD64LO(pAddr));
}
#endif /* WARN_MEM */
/* If instruction fetch then we need to check that the two lo-order
bits are zero, otherwise raise a InstructionFetch exception: */
- if ((IorD == isINSTRUCTION) && ((pAddr & 0x3) != 0))
+ if ((IorD == isINSTRUCTION)
+ && ((pAddr & 0x3) != 0)
+ && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
SignalException(InstructionFetch);
else {
unsigned int index;
#if defined(WARN_MEM)
if (CCA != uncached)
- callback->printf_filtered(callback,"SIM Warning: StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
+ sim_warning("StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)",CCA);
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
- sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength,WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%08X%08X\n",AccessLength,(LOADDRMASK + 1)<<2,WORD64HI(pAddr),WORD64LO(pAddr));
#endif /* WARN_MEM */
#if defined(TRACE)
that aborts the instruction. The instruction operation pseudocode
will never see a return from this function call. */
static void
-SignalException(exception)
- int exception;
+SignalException (int exception,...)
{
/* Ensure that any active atomic read/modify/write operation will fail: */
LLBIT = 0;
reality we should either simulate them, or allow the user to
ignore them at run-time. */
case Trap :
- callback->printf_filtered(callback,"Ignoring instruction TRAP (PC 0x%08X%08X)\n",WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("Ignoring instruction TRAP (PC 0x%08X%08X)",WORD64HI(IPC),WORD64LO(IPC));
break;
case ReservedInstruction :
instruction was used to enter the vector (which is the
case with the current IDT monitor). */
break; /* out of the switch statement */
+ }
+ /* Look for the mips16 entry and exit instructions, and
+ simulate a handler for them. */
+ else if ((IPC & 1) != 0
+ && (instruction & 0xf81f) == 0xe809
+ && (instruction & 0x700) != 0x500
+ && (instruction & 0x700) != 0x600
+ && (instruction & 0x0c0) != 0x0c0) {
+ mips16_entry (instruction);
+ break;
} /* else fall through to normal exception processing */
- callback->printf_filtered(callback,"DBG: ReservedInstruction 0x%08X at IPC = 0x%08X%08X\n",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("ReservedInstruction 0x%08X at IPC = 0x%08X%08X",instruction,WORD64HI(IPC),WORD64LO(IPC));
}
default:
-#if 1 /* def DEBUG */
- callback->printf_filtered(callback,"DBG: SignalException(%d) IPC = 0x%08X%08X\n",exception,WORD64HI(IPC),WORD64LO(IPC));
+#ifdef DEBUG
+ if (exception != BreakPoint)
+ callback->printf_filtered(callback,"DBG: SignalException(%d) IPC = 0x%08X%08X\n",exception,WORD64HI(IPC),WORD64LO(IPC));
#endif /* DEBUG */
/* Store exception code into current exception id variable (used
by exit code): */
/* TODO: If not simulating exceptions then stop the simulator
execution. At the moment we always stop the simulation. */
state |= (simSTOP | simEXCEPTION);
+
+ /* Keep a copy of the current A0 in-case this is the program exit
+ breakpoint: */
+ if (exception == BreakPoint) {
+ va_list ap;
+ unsigned int instruction;
+ va_start(ap,exception);
+ instruction = va_arg(ap,unsigned int);
+ va_end(ap);
+ /* Check for our special terminating BREAK: */
+ if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
+ rcexit = (unsigned int)(A0 & 0xFFFFFFFF);
+ state &= ~simEXCEPTION;
+ state |= simEXIT;
+ }
+ }
+
+ /* Store exception code into current exception id variable (used
+ by exit code): */
CAUSE = (exception << 2);
if (state & simDELAYSLOT) {
CAUSE |= cause_BD;
static void
UndefinedResult()
{
- callback->printf_filtered(callback,"UndefinedResult: IPC = 0x%08X%08X\n",WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("UndefinedResult: IPC = 0x%08X%08X",WORD64HI(IPC),WORD64LO(IPC));
#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
state |= simSTOP;
#endif
uword64 vAddr;
unsigned int instruction;
{
+#if 1 /* stop warning message being displayed (we should really just remove the code) */
+ static int icache_warning = 1;
+ static int dcache_warning = 1;
+#else
static int icache_warning = 0;
static int dcache_warning = 0;
+#endif
/* If CP0 is not useable (User or Supervisor mode) and the CP0
enable bit in the Status Register is clear - a coprocessor
case 6: /* Hit Writeback */
if (!icache_warning)
{
- callback->printf_filtered(callback,"SIM Warning: Instruction CACHE operation %d to be coded\n",(op >> 2));
+ sim_warning("Instruction CACHE operation %d to be coded",(op >> 2));
icache_warning = 1;
}
break;
case 6: /* Hit Writeback */
if (!dcache_warning)
{
- callback->printf_filtered(callback,"SIM Warning: Data CACHE operation %d to be coded\n",(op >> 2));
+ sim_warning("Data CACHE operation %d to be coded",(op >> 2));
dcache_warning = 1;
}
break;
#endif /* DEBUG */
}
if (fmt != fpr_state[fpr]) {
- callback->printf_filtered(callback,"Warning: FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%08X%08X)\n",fpr,DOFMT(fpr_state[fpr]),DOFMT(fmt),WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%08X%08X)",fpr,DOFMT(fpr_state[fpr]),DOFMT(fmt),WORD64HI(IPC),WORD64LO(IPC));
fpr_state[fpr] = fmt_unknown;
}
case fmt_uninterpreted:
case fmt_double:
case fmt_long:
- value = ((FGR[fpr+1] << 32) | (FGR[fpr] & 0xFFFFFFFF));
+ value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
break;
default :
case fmt_single:
{
unsigned int wop = (unsigned int)op;
+#ifdef HAVE_SQRT
float tmp = ((float)sqrt((double)*(float *)&wop));
result = (uword64)*(unsigned int *)&tmp;
+#else
+ /* TODO: Provide square-root */
+ result = (uword64)0;
+#endif
}
break;
case fmt_double:
{
+#ifdef HAVE_SQRT
double tmp = (sqrt(*(double *)&op));
result = *(uword64 *)&tmp;
+#else
+ /* TODO: Provide square-root */
+ result = (uword64)0;
+#endif
}
break;
}
break;
case fmt_long:
- tmp = (float)((int)op);
+ tmp = (float)((word64)op);
break;
}
+#if 0
+ /* FIXME: This code is incorrect. The rounding mode does not
+ round to integral values; it rounds to the nearest
+ representable value in the format. */
+
switch (rm) {
case FP_RM_NEAREST:
/* Round result to nearest representable value. When two
representable values are equally near, round to the value
that has a least significant bit of zero (i.e. is even). */
-#if defined(sun)
+#ifdef HAVE_ANINT
tmp = (float)anint((double)tmp);
#else
/* TODO: Provide round-to-nearest */
case FP_RM_TOZERO:
/* Round result to the value closest to, and not greater in
magnitude than, the result. */
-#if defined(sun)
+#ifdef HAVE_AINT
tmp = (float)aint((double)tmp);
#else
/* TODO: Provide round-to-zero */
tmp = (float)floor((double)tmp);
break;
}
+#endif /* 0 */
+
result = (uword64)*(unsigned int *)&tmp;
}
break;
case fmt_double:
{
double tmp;
+ word64 xxx;
switch (from) {
case fmt_single:
break;
case fmt_word:
- tmp = (double)((word64)SIGNEXTEND((op & 0xFFFFFFFF),32));
+ xxx = SIGNEXTEND((op & 0xFFFFFFFF),32);
+ tmp = (double)xxx;
break;
case fmt_long:
break;
}
+#if 0
+ /* FIXME: This code is incorrect. The rounding mode does not
+ round to integral values; it rounds to the nearest
+ representable value in the format. */
+
switch (rm) {
case FP_RM_NEAREST:
-#if defined(sun)
+#ifdef HAVE_ANINT
tmp = anint(*(double *)&tmp);
#else
/* TODO: Provide round-to-nearest */
break;
case FP_RM_TOZERO:
-#if defined(sun)
+#ifdef HAVE_AINT
tmp = aint(*(double *)&tmp);
#else
/* TODO: Provide round-to-zero */
tmp = floor(*(double *)&tmp);
break;
}
+#endif /* 0 */
+
result = *(uword64 *)&tmp;
}
break;
SignalException(FPE);
} else {
if (to == fmt_word) {
- unsigned int tmp;
+ int tmp;
switch (from) {
case fmt_single:
{
unsigned int wop = (unsigned int)op;
- tmp = (unsigned int)*((float *)&wop);
+ tmp = (int)*((float *)&wop);
}
break;
case fmt_double:
- tmp = (unsigned int)*((double *)&op);
+ tmp = (int)*((double *)&op);
#ifdef DEBUG
printf("DBG: from double %.30f (0x%08X%08X) to word: 0x%08X\n",*((double *)&op),WORD64HI(op),WORD64LO(op),tmp);
#endif /* DEBUG */
}
result = (uword64)tmp;
} else { /* fmt_long */
+ word64 tmp;
switch (from) {
case fmt_single:
{
unsigned int wop = (unsigned int)op;
- result = (uword64)*((float *)&wop);
+ tmp = (word64)*((float *)&wop);
}
break;
case fmt_double:
- result = (uword64)*((double *)&op);
+ tmp = (word64)*((double *)&op);
break;
}
+ result = (uword64)tmp;
}
}
break;
#endif /* HASFPU */
default:
+#if 0 /* this should be controlled by a configuration option */
callback->printf_filtered(callback,"COP_LW(%d,%d,0x%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,WORD64HI(IPC),WORD64LO(IPC));
+#endif
break;
}
#endif /* HASFPU */
default:
+#if 0 /* this message should be controlled by a configuration option */
callback->printf_filtered(callback,"COP_LD(%d,%d,0x%08X%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(memword),WORD64LO(memword),WORD64HI(IPC),WORD64LO(IPC));
+#endif
break;
}
#endif /* HASFPU */
default:
+#if 0 /* should be controlled by configuration option */
callback->printf_filtered(callback,"COP_SW(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC));
+#endif
break;
}
#endif /* HASFPU */
default:
+#if 0 /* should be controlled by configuration option */
callback->printf_filtered(callback,"COP_SD(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC));
+#endif
break;
}
int rt = ((instruction >> 16) & 0x1F);
int rd = ((instruction >> 11) & 0x1F);
if (code == 0x00) { /* MF : move from */
+#if 0 /* message should be controlled by configuration option */
callback->printf_filtered(callback,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
+#endif
GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
} else { /* MT : move to */
/* CPR[0,rd] = GPR[rt]; */
+#if 0 /* should be controlled by configuration option */
callback->printf_filtered(callback,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
+#endif
}
} else
- callback->printf_filtered(callback,"Warning: Unrecognised COP0 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("Unrecognised COP0 instruction 0x%08X at IPC = 0x%08X%08X : No handler present",instruction,WORD64HI(IPC),WORD64LO(IPC));
/* TODO: When executing an ERET or RFE instruction we should
clear LLBIT, to ensure that any out-standing atomic
read/modify/write sequence fails. */
break;
case 2: /* undefined co-processor */
- callback->printf_filtered(callback,"Warning: COP2 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("COP2 instruction 0x%08X at IPC = 0x%08X%08X : No handler present",instruction,WORD64HI(IPC),WORD64LO(IPC));
break;
case 1: /* should not occur (FPU co-processor) */
callback->printf_filtered(callback,"DBG: DSPC = 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
#endif /* DEBUG */
- if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { /* Copy the action of the LW instruction */
- unsigned int reverse = (ReverseEndian ? 1 : 0);
- unsigned int bigend = (BigEndianCPU ? 1 : 0);
- uword64 value;
- unsigned int byte;
- paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 2)));
- value = LoadMemory(cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
- byte = ((vaddr & 0x7) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
+ if ((vaddr & 1) == 0) {
+ /* Copy the action of the LW instruction */
+ unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
+ unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
+ uword64 value;
+ unsigned int byte;
+ paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
+ value = LoadMemory(cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
+ byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
+ instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ } else {
+ /* Copy the action of the LH instruction */
+ unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
+ unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
+ uword64 value;
+ unsigned int byte;
+ paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
+ | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
+ value = LoadMemory(cca, AccessLength_HALFWORD,
+ paddr & ~ (uword64) 1,
+ vaddr, isINSTRUCTION, isREAL);
+ byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
+ instruction = ((value >> (8 * byte)) & 0xFFFF);
+ }
} else {
fprintf(stderr,"Cannot translate address for PC = 0x%08X%08X failed\n",WORD64HI(PC),WORD64LO(PC));
exit(1);
instruction_fetch_overflow++;
#if defined(PROFILE)
if ((state & simPROFILE) && ((instruction_fetches % profile_frequency) == 0) && profile_hist) {
- int n = ((unsigned int)(PC - profile_minpc) >> (profile_shift + 2));
+ unsigned n = ((unsigned int)(PC - profile_minpc) >> (profile_shift + 2));
if (n < profile_nsamples) {
/* NOTE: The counts for the profiling bins are only 16bits wide */
if (profile_hist[n] != USHRT_MAX)
/* This is required by exception processing, to ensure that we can
cope with exceptions in the delay slots of branches that may
already have changed the PC. */
- PC += 4; /* increment ready for the next fetch */
+ if ((vaddr & 1) == 0)
+ PC += 4; /* increment ready for the next fetch */
+ else
+ PC += 2;
/* NOTE: If we perform a delay slot change to the PC, this
increment is not requuired. However, it would make the
simulator more complicated to try and avoid this small hit. */
if (!(state & simSKIPNEXT)) {
/* Include the simulator engine */
#include "engine.c"
-#if ((GPRLEN == 64) && !defined(PROCESSOR_64BIT)) || ((GPRLEN == 32) && defined(PROCESSOR_64BIT))
+#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
#error "Mismatch between run-time simulator code and simulation engine"
#endif
than within the simulator, since it will help keep the simulator
small. */
if (ZERO != 0) {
- callback->printf_filtered(callback,"SIM Warning: The ZERO register has been updated with 0x%08X%08X (PC = 0x%08X%08X)\nSIM Warning: Resetting back to zero\n",WORD64HI(ZERO),WORD64LO(ZERO),WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("The ZERO register has been updated with 0x%08X%08X (PC = 0x%08X%08X) (reset back to zero)",WORD64HI(ZERO),WORD64LO(ZERO),WORD64HI(IPC),WORD64LO(IPC));
ZERO = 0; /* reset back to zero before next instruction */
}
#endif /* WARN_ZERO */
printf("DBG: dsstate set before instruction execution - updating PC to 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
#endif /* DEBUG */
PC = DSPC;
- state &= ~simDELAYSLOT;
+ state &= ~(simDELAYSLOT | simJALDELAYSLOT);
}
if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
registers, is when performing binary transfers. This
means we should update the register type field. */
if ((pending_slot_reg[index] >= FGRIDX) && (pending_slot_reg[index] < (FGRIDX + 32)))
- fpr_state[pending_slot_reg[index]] = fmt_uninterpreted;
+ fpr_state[pending_slot_reg[index] - FGRIDX] = fmt_uninterpreted;
#endif /* HASFPU */
}
#ifdef DEBUG
projects / deliverable / binutils-gdb.git / blobdiff