/* Get the simulator engine description, without including the code: */
+#if (WITH_IGEN)
+#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
+#else
#define SIM_MANIFESTS
#include "oengine.c"
#undef SIM_MANIFESTS
+#endif
+
+/* Within interp.c we refer to the sim_state and sim_cpu directly. */
+#define SD sd
+#define CPU cpu
/* The following reserved instruction value is used when a simulator
int opt;
char *arg;
{
+ int cpu_nr;
switch (opt)
{
case OPTION_DINERO_TRACE: /* ??? */
allow external control of the program points being traced
(i.e. only from main onwards, excluding the run-time setup,
etc.). */
- if (arg == NULL)
- STATE |= simTRACE;
- else if (strcmp (arg, "yes") == 0)
- STATE |= simTRACE;
- else if (strcmp (arg, "no") == 0)
- STATE &= ~simTRACE;
- else if (strcmp (arg, "on") == 0)
- STATE |= simTRACE;
- else if (strcmp (arg, "off") == 0)
- STATE &= ~simTRACE;
- else
+ for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
{
- fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
- return SIM_RC_FAIL;
+ sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+ if (arg == NULL)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "yes") == 0)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "no") == 0)
+ STATE &= ~simTRACE;
+ else if (strcmp (arg, "on") == 0)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "off") == 0)
+ STATE &= ~simTRACE;
+ else
+ {
+ fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
}
return SIM_RC_OK;
#else /* !TRACE */
static void
interrupt_event (SIM_DESC sd, void *data)
{
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
if (SR & status_IE)
{
interrupt_pending = 0;
}
+/*---------------------------------------------------------------------------*/
+/*-- Device registration hook -----------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+static void device_init(SIM_DESC sd) {
+#ifdef DEVICE_INIT
+ extern void register_devices(SIM_DESC);
+ register_devices(sd);
+#endif
+}
+
+/* start-sanitize-sky */
+static struct {
+ short i[16];
+ int f[NUM_VU_REGS - 16];
+} vu_regs[2];
+/* end-sanitize-sky */
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
char **argv;
{
SIM_DESC sd = sim_state_alloc (kind, cb);
- sim_cpu *cpu = STATE_CPU (sd, 0);
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
MEM_SIZE, /* actual size */
K0BASE);
+ device_init(sd);
+
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
print_filtered. */
SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
-#if defined(HASFPU)
- /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
- and DOUBLE binary formats. This is a bit nasty, requiring that we
- trust the explicit manifests held in the source: */
- /* TODO: We need to cope with the simulated target and the host not
- having the same endianness. This will require the high and low
- words of a (double) to be swapped when converting between the
- host and the simulated target. */
- {
- union {
- unsigned int i[2];
- double d;
- float f[2];
- } s;
-
- s.d = (double)523.2939453125;
-
- if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125
- || s.i[1] != 0x40805A5A))
- || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125
- || s.i[0] != 0x40805A5A)))
- {
- fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
- return 0;
- }
- }
-#endif /* HASFPU */
-
/* This is NASTY, in that we are assuming the size of specific
registers: */
{
int rn;
- for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
- if (rn < 32)
- cpu->register_widths[rn] = GPRLEN;
- else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
- cpu->register_widths[rn] = GPRLEN;
- else if ((rn >= 33) && (rn <= 37))
- cpu->register_widths[rn] = GPRLEN;
- else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
- cpu->register_widths[rn] = 32;
- else
- cpu->register_widths[rn] = 0;
- }
+ for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
+ {
+ if (rn < 32)
+ cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
+ else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
+ cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
+ else if ((rn >= 33) && (rn <= 37))
+ cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
+ else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
+ cpu->register_widths[rn] = 32;
+ else
+ cpu->register_widths[rn] = 0;
+ }
/* start-sanitize-r5900 */
/* set the 5900 "upper" registers to 64 bits */
for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
cpu->register_widths[rn] = 64;
/* end-sanitize-r5900 */
+
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ /* Now the VU registers */
+ for( rn = 0; rn < 16; rn++ ) { /* first the integer registers */
+ cpu->register_widths[rn + NUM_R5900_REGS] = 16;
+ cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
+
+ /* Hack for now - to test gdb interface */
+ vu_regs[0].i[rn] = rn + 0x100;
+ vu_regs[1].i[rn] = rn + 0x200;
+ }
+
+ for( rn = 16; rn < NUM_VU_REGS; rn++ ) { /* then the FP registers */
+ float f;
+
+ cpu->register_widths[rn + NUM_R5900_REGS] = 32;
+ cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
+
+ /* Hack for now - to test gdb interface */
+ if( rn < 24 ) {
+ f = rn - 16 + 100.0;
+ vu_regs[0].f[rn-16] = *((unsigned *) &f);
+ f = rn - 16 + 200.0;
+ vu_regs[1].f[rn-16] = *((unsigned *) &f);
+ }
+ else {
+ f = (rn - 24)/4 + (rn - 24)%4 + 1000.0;
+ vu_regs[0].f[rn-16] = *((unsigned *) &f);
+ f = (rn - 24)/4 + (rn - 24)%4 + 2000.0;
+ vu_regs[1].f[rn-16] = *((unsigned *) &f);
+ }
+ }
+#endif
+ /* end-sanitize-sky */
}
#if defined(TRACE)
if (tracefh != NULL && tracefh != stderr)
fclose(tracefh);
tracefh = NULL;
- STATE &= ~simTRACE;
#endif /* TRACE */
+ /* FIXME - free SD */
+
return;
}
int size;
{
int index;
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* Return the number of bytes written, or zero if error. */
#ifdef DEBUG
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
- if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
+ if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
break;
- if (sim_core_write_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
+ if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
break;
}
int size;
{
int index;
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* Return the number of bytes read, or zero if error. */
#ifdef DEBUG
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
- if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
+ if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
break;
- if (sim_core_read_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
+ if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
break;
}
int rn;
unsigned char *memory;
{
- sim_cpu *cpu = STATE_CPU (sd, 0);
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
#ifdef DEBUG
if (cpu->register_widths[rn] == 0)
sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ else if( rn > NUM_R5900_REGS ) {
+ rn = rn - NUM_R5900_REGS;
+
+ if( rn < 16 )
+ vu_regs[0].i[rn] = T2H_2( *(unsigned short *) memory );
+ else if( rn < NUM_VU_REGS )
+ vu_regs[0].f[rn - 16] = T2H_4( *(unsigned int *) memory );
+ else {
+ rn = rn - NUM_VU_REGS;
+
+ if( rn < 16 )
+ vu_regs[1].i[rn] = T2H_2( *(unsigned short *) memory );
+ else if( rn < NUM_VU_REGS )
+ vu_regs[1].f[rn - 16] = T2H_4( *(unsigned int *) memory );
+ else
+ sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
+ }
+ }
+#endif
+ /* end-sanitize-sky */
/* start-sanitize-r5900 */
else if (rn == REGISTER_SA)
- SA = T2H_8(*(uword64*)memory);
+ SA = T2H_8(*(unsigned64*)memory);
else if (rn > LAST_EMBED_REGNUM)
- cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory);
+ cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(unsigned64*)memory);
/* end-sanitize-r5900 */
+ else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ {
+ if (cpu->register_widths[rn] == 32)
+ cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
+ else
+ cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
+ }
else if (cpu->register_widths[rn] == 32)
- cpu->registers[rn] = T2H_4 (*(unsigned int*)memory);
+ cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
else
- cpu->registers[rn] = T2H_8 (*(uword64*)memory);
+ cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
return;
}
int rn;
unsigned char *memory;
{
- sim_cpu *cpu = STATE_CPU (sd, 0);
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
#ifdef DEBUG
if (cpu->register_widths[rn] == 0)
sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ else if( rn > NUM_R5900_REGS ) {
+ rn = rn - NUM_R5900_REGS;
+
+ if( rn < 16 )
+ *((unsigned short *) memory) = H2T_2( vu_regs[0].i[rn] );
+ else if( rn < NUM_VU_REGS )
+ *((unsigned int *) memory) = H2T_4( vu_regs[0].f[rn - 16] );
+ else {
+ rn = rn - NUM_VU_REGS;
+
+ if( rn < 16 )
+ (*(unsigned short *) memory) = H2T_2( vu_regs[1].i[rn] );
+ else if( rn < NUM_VU_REGS )
+ (*(unsigned int *) memory) = H2T_4( vu_regs[1].f[rn - 16] );
+ else
+ sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
+ }
+ }
+#endif
+ /* end-sanitize-sky */
/* start-sanitize-r5900 */
else if (rn == REGISTER_SA)
- *((uword64 *)memory) = H2T_8(SA);
+ *((unsigned64*)memory) = H2T_8(SA);
else if (rn > LAST_EMBED_REGNUM)
- *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
+ *((unsigned64*)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
/* end-sanitize-r5900 */
+ else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ {
+ if (cpu->register_widths[rn] == 32)
+ *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
+ else
+ *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
+ }
else if (cpu->register_widths[rn] == 32)
- *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF));
+ *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
else /* 64bit register */
- *((uword64 *)memory) = H2T_8 (cpu->registers[rn]);
+ *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
return;
}
{
sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
- (PROCESSOR_64BIT ? 64 : 32),
+ WITH_TARGET_WORD_BITSIZE,
(CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
#if !defined(FASTSIM)
ColdReset(sd);
if (abfd != NULL)
- /* override PC value set by ColdReset () */
- PC = (unsigned64) bfd_get_start_address (abfd);
+ {
+ /* override PC value set by ColdReset () */
+ int cpu_nr;
+ for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
+ {
+ sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+ CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
+ }
+ }
#if 0 /* def DEBUG */
if (argv || env)
/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
static void
-sim_monitor(sd,cia,reason)
- SIM_DESC sd;
- address_word cia;
- unsigned int reason;
+sim_monitor (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ unsigned int reason)
{
#ifdef DEBUG
printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
break;
}
+ case 2: /* Densan monitor: char inbyte(int waitflag) */
+ {
+ if (A0 == 0) /* waitflag == NOWAIT */
+ V0 = (unsigned_word)-1;
+ }
+ /* Drop through to case 11 */
+
case 11: /* char inbyte(void) */
{
char tmp;
if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
{
sim_io_error(sd,"Invalid return from character read");
- V0 = (ut_reg)-1;
+ V0 = (unsigned_word)-1;
}
else
- V0 = (ut_reg)tmp;
+ V0 = (unsigned_word)tmp;
break;
}
+ case 3: /* Densan monitor: void co(char chr) */
case 12: /* void outbyte(char chr) : write a byte to "stdout" */
{
char tmp = (char)(A0 & 0xFF);
case 17: /* void _exit() */
{
sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
(unsigned int)(A0 & 0xFFFFFFFF));
break;
}
/* Store a word into memory. */
static void
-store_word (sd, cia, vaddr, val)
- SIM_DESC sd;
- address_word cia;
- uword64 vaddr;
- t_reg val;
+store_word (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ uword64 vaddr,
+ signed_word val)
{
address_word paddr;
int uncached;
/* Load a word from memory. */
-static t_reg
-load_word (sd, cia, vaddr)
- SIM_DESC sd;
- address_word cia;
- uword64 vaddr;
+static signed_word
+load_word (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ uword64 vaddr)
{
if ((vaddr & 3) != 0)
SignalExceptionAddressLoad ();
code, but for ease of simulation we just handle them directly. */
static void
-mips16_entry (sd,insn)
- SIM_DESC sd;
- unsigned int insn;
+mips16_entry (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ unsigned int insn)
{
int aregs, sregs, rreg;
if (aregs < 5)
{
int i;
- t_reg tsp;
+ signed_word tsp;
/* This is the entry pseudo-instruction. */
for (i = 0; i < aregs; i++)
- store_word ((uword64) (SP + 4 * i), GPR[i + 4]);
+ store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
tsp = SP;
SP -= 32;
if (rreg)
{
tsp -= 4;
- store_word ((uword64) tsp, RA);
+ store_word (SD, CPU, cia, (uword64) tsp, RA);
}
for (i = 0; i < sregs; i++)
{
tsp -= 4;
- store_word ((uword64) tsp, GPR[16 + i]);
+ store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
}
}
else
{
int i;
- t_reg tsp;
+ signed_word tsp;
/* This is the exit pseudo-instruction. */
if (rreg)
{
tsp -= 4;
- RA = load_word ((uword64) tsp);
+ RA = load_word (SD, CPU, cia, (uword64) tsp);
}
for (i = 0; i < sregs; i++)
{
tsp -= 4;
- GPR[i + 16] = load_word ((uword64) tsp);
+ GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
}
SP += 32;
-#if defined(HASFPU)
- if (aregs == 5)
- {
- FGR[0] = WORD64LO (GPR[4]);
- FPR_STATE[0] = fmt_uninterpreted;
- }
- else if (aregs == 6)
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
- FGR[0] = WORD64LO (GPR[5]);
- FGR[1] = WORD64LO (GPR[4]);
- FPR_STATE[0] = fmt_uninterpreted;
- FPR_STATE[1] = fmt_uninterpreted;
- }
-#endif /* defined(HASFPU) */
+ if (aregs == 5)
+ {
+ FGR[0] = WORD64LO (GPR[4]);
+ FPR_STATE[0] = fmt_uninterpreted;
+ }
+ else if (aregs == 6)
+ {
+ FGR[0] = WORD64LO (GPR[5]);
+ FGR[1] = WORD64LO (GPR[4]);
+ FPR_STATE[0] = fmt_uninterpreted;
+ FPR_STATE[1] = fmt_uninterpreted;
+ }
+ }
PC = RA;
}
+
}
/*-- trace support ----------------------------------------------------------*/
void
-dotrace (SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
+dotrace (SIM_DESC sd,
+ sim_cpu *cpu,
+ FILE *tracefh,
+ int type,
+ SIM_ADDR address,
+ int width,
+ char *comment,...)
{
if (STATE & simTRACE) {
va_list ap;
/*---------------------------------------------------------------------------*/
static void
-ColdReset (sd)
- SIM_DESC sd;
+ColdReset (SIM_DESC sd)
{
- /* RESET: Fixed PC address: */
- PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
- /* The reset vector address is in the unmapped, uncached memory space. */
-
- SR &= ~(status_SR | status_TS | status_RP);
- SR |= (status_ERL | status_BEV);
-
- /* Cheat and allow access to the complete register set immediately */
- if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
- && WITH_TARGET_WORD_BITSIZE == 64)
- SR |= status_FR; /* 64bit registers */
-
- /* Ensure that any instructions with pending register updates are
- cleared: */
- {
- int loop;
- for (loop = 0; (loop < PSLOTS); loop++)
- PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1);
- PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0;
- }
-
- /* Initialise the FPU registers to the unknown state */
- if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ int cpu_nr;
+ for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
{
- int rn;
- for (rn = 0; (rn < 32); rn++)
- FPR_STATE[rn] = fmt_uninterpreted;
+ sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+ /* RESET: Fixed PC address: */
+ PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
+ /* The reset vector address is in the unmapped, uncached memory space. */
+
+ SR &= ~(status_SR | status_TS | status_RP);
+ SR |= (status_ERL | status_BEV);
+
+ /* Cheat and allow access to the complete register set immediately */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
+ && WITH_TARGET_WORD_BITSIZE == 64)
+ SR |= status_FR; /* 64bit registers */
+
+ /* Ensure that any instructions with pending register updates are
+ cleared: */
+ PENDING_INVALIDATE();
+
+ /* Initialise the FPU registers to the unknown state */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ int rn;
+ for (rn = 0; (rn < 32); rn++)
+ FPR_STATE[rn] = fmt_uninterpreted;
+ }
+
}
-
- return;
}
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
function raises an exception and does not return. */
int
-address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
- SIM_DESC sd;
- address_word cia;
- address_word vAddr;
- int IorD;
- int LorS;
- address_word *pAddr;
- int *CCA;
- int raw;
+address_translation (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ address_word vAddr,
+ int IorD,
+ int LorS,
+ address_word *pAddr,
+ int *CCA,
+ int raw)
{
int res = -1; /* TRUE : Assume good return */
program, or alter architecturally-visible state. */
void
-prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
- SIM_DESC sd;
- address_word cia;
- int CCA;
- address_word pAddr;
- address_word vAddr;
- int DATA;
- int hint;
+prefetch (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int CCA,
+ address_word pAddr,
+ address_word vAddr,
+ int DATA,
+ int hint)
{
#ifdef DEBUG
sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
satisfy a load reference. At a minimum, the block is the entire
memory element. */
void
-load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
- SIM_DESC sd;
- address_word cia;
- uword64* memvalp;
- uword64* memval1p;
- int CCA;
- int AccessLength;
- address_word pAddr;
- address_word vAddr;
- int IorD;
+load_memory (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ uword64* memvalp,
+ uword64* memval1p,
+ int CCA,
+ int AccessLength,
+ address_word pAddr,
+ address_word vAddr,
+ int IorD)
{
uword64 value = 0;
uword64 value1 = 0;
}
#if defined(TRACE)
- dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
+ dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
#endif /* TRACE */
/* Read the specified number of bytes from memory. Adjust for
{
case AccessLength_QUADWORD :
{
- unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
+ unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
case AccessLength_DOUBLEWORD :
- value = sim_core_read_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
+ value = sim_core_read_aligned_8 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
break;
case AccessLength_SEPTIBYTE :
- value = sim_core_read_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
+ value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
case AccessLength_SEXTIBYTE :
- value = sim_core_read_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
+ value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
case AccessLength_QUINTIBYTE :
- value = sim_core_read_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
+ value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
case AccessLength_WORD :
- value = sim_core_read_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
+ value = sim_core_read_aligned_4 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
break;
case AccessLength_TRIPLEBYTE :
- value = sim_core_read_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
+ value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
case AccessLength_HALFWORD :
- value = sim_core_read_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
+ value = sim_core_read_aligned_2 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
break;
case AccessLength_BYTE :
- value = sim_core_read_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
+ value = sim_core_read_aligned_1 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
break;
default:
will be changed. */
void
-store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
- SIM_DESC sd;
- address_word cia;
- int CCA;
- int AccessLength;
- uword64 MemElem;
- uword64 MemElem1; /* High order 64 bits */
- address_word pAddr;
- address_word vAddr;
+store_memory (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int CCA,
+ int AccessLength,
+ uword64 MemElem,
+ uword64 MemElem1, /* High order 64 bits */
+ address_word pAddr,
+ address_word vAddr)
{
#ifdef DEBUG
sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
#if defined(TRACE)
- dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
+ dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
#endif /* TRACE */
#ifdef DEBUG
case AccessLength_QUADWORD :
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
- sim_core_write_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
+ sim_core_write_aligned_16 (cpu, NULL_CIA,
sim_core_write_map, pAddr, val);
break;
}
case AccessLength_DOUBLEWORD :
- sim_core_write_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
+ sim_core_write_aligned_8 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
break;
case AccessLength_SEPTIBYTE :
- sim_core_write_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
+ sim_core_write_misaligned_7 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
break;
case AccessLength_SEXTIBYTE :
- sim_core_write_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
+ sim_core_write_misaligned_6 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
break;
case AccessLength_QUINTIBYTE :
- sim_core_write_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
+ sim_core_write_misaligned_5 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
break;
case AccessLength_WORD :
- sim_core_write_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
+ sim_core_write_aligned_4 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
break;
case AccessLength_TRIPLEBYTE :
- sim_core_write_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
+ sim_core_write_misaligned_3 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
break;
case AccessLength_HALFWORD :
- sim_core_write_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
+ sim_core_write_aligned_2 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
break;
case AccessLength_BYTE :
- sim_core_write_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
+ sim_core_write_aligned_1 (cpu, NULL_CIA,
sim_core_write_map, pAddr, MemElem);
break;
default:
unsigned32
ifetch32 (SIM_DESC sd,
+ sim_cpu *cpu,
address_word cia,
address_word vaddr)
{
}
+unsigned16
+ifetch16 (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ address_word vaddr)
+{
+ /* Copy the action of the LW instruction */
+ address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
+ address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
+ unsigned64 value;
+ address_word paddr;
+ unsigned16 instruction;
+ unsigned byte;
+ int cca;
+ AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
+ paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
+ LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
+ byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
+ instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ return instruction;
+}
+
+
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* Order loads and stores to synchronise shared memory. Perform the
action necessary to make the effects of groups of synchronizable
loads and stores indicated by stype occur in the same order for all
processors. */
void
-sync_operation(sd,cia,stype)
- SIM_DESC sd;
- address_word cia;
- int stype;
+sync_operation (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int stype)
{
#ifdef DEBUG
sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
void
signal_exception (SIM_DESC sd,
+ sim_cpu *cpu,
address_word cia,
int exception,...)
{
Debug |= Debug_DM; /* in debugging mode */
Debug |= Debug_DBp; /* raising a DBp exception */
PC = 0xBFC00200;
- sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
+ sim_engine_restart (SD, CPU, NULL, NULL_CIA);
}
break;
perform this magic. */
if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
{
- sim_monitor(sd, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
+ sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
/* NOTE: This assumes that a branch-and-link style
instruction was used to enter the vector (which is the
case with the current IDT monitor). */
- sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, RA);
+ sim_engine_restart (SD, CPU, NULL, RA);
}
/* Look for the mips16 entry and exit instructions, and
simulate a handler for them. */
&& (instruction & 0xf81f) == 0xe809
&& (instruction & 0x0c0) != 0x0c0)
{
- mips16_entry (instruction);
+ mips16_entry (SD, CPU, cia, instruction);
sim_engine_restart (sd, NULL, NULL, NULL_CIA);
}
/* else fall through to normal exception processing */
va_end(ap);
/* Check for our special terminating BREAK: */
if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
+ sim_engine_halt (SD, CPU, NULL, cia,
sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
}
}
PC = cia - 4; /* reference the branch instruction */
else
PC = cia;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
+ sim_engine_halt (SD, CPU, NULL, cia,
sim_stopped, SIM_SIGTRAP);
default:
/* The following is so that the simulator will continue from the
exception address on breakpoint operations. */
PC = EPC;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGBUS);
case ReservedInstruction:
case CoProcessorUnusable:
PC = EPC;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGILL);
case IntegerOverflow:
case FPE:
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGFPE);
case Trap:
case Watch:
case SystemCall:
PC = EPC;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGTRAP);
case BreakPoint:
PC = EPC;
- sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
+ sim_engine_abort (SD, CPU, NULL_CIA,
"FATAL: Should not encounter a breakpoint\n");
default : /* Unknown internal exception */
PC = EPC;
- sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
sim_stopped, SIM_SIGABRT);
}
va_start(ap,exception);
msg = va_arg(ap,char *);
va_end(ap);
- sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
+ sim_engine_abort (SD, CPU, NULL_CIA,
"FATAL: Simulator error \"%s\"\n",msg);
}
}
#endif /* WARN_RESULT */
void
-cache_op(sd,cia,op,pAddr,vAddr,instruction)
- SIM_DESC sd;
- address_word cia;
- int op;
- address_word pAddr;
- address_word vAddr;
- unsigned int instruction;
+cache_op (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int op,
+ address_word pAddr,
+ address_word vAddr,
+ unsigned int instruction)
{
#if 1 /* stop warning message being displayed (we should really just remove the code) */
static int icache_warning = 1;
/*-- FPU support routines ---------------------------------------------------*/
-#if defined(HASFPU) /* Only needed when building FPU aware simulators */
-
/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
formats conform to ANSI/IEEE Std 754-1985. */
/* SINGLE precision floating:
#endif /* DEBUG */
uword64
-value_fpr(sd,cia,fpr,fmt)
- SIM_DESC sd;
- address_word cia;
- int fpr;
- FP_formats fmt;
+value_fpr (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int fpr,
+ FP_formats fmt)
{
uword64 value = 0;
int err = 0;
}
void
-store_fpr(sd,cia,fpr,fmt,value)
- SIM_DESC sd;
- address_word cia;
- int fpr;
- FP_formats fmt;
- uword64 value;
+store_fpr (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int fpr,
+ FP_formats fmt,
+ uword64 value)
{
int err = 0;
FP_formats fmt;
{
int boolean = 0;
-
- /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
- know that the exponent field is biased... we we cheat and avoid
- removing the bias value. */
switch (fmt) {
case fmt_single:
- boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) != 0));
- /* We could use "FP_S_fb(1,op)" to ascertain whether we are
- dealing with a SNaN or QNaN */
- break;
- case fmt_double:
- boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) != 0));
- /* We could use "FP_S_fb(1,op)" to ascertain whether we are
- dealing with a SNaN or QNaN */
- break;
case fmt_word:
- boolean = (op == FPQNaN_WORD);
- break;
+ {
+ sim_fpu wop;
+ sim_fpu_32to (&wop, op);
+ boolean = sim_fpu_is_nan (&wop);
+ break;
+ }
+ case fmt_double:
case fmt_long:
- boolean = (op == FPQNaN_LONG);
- break;
+ {
+ sim_fpu wop;
+ sim_fpu_64to (&wop, op);
+ boolean = sim_fpu_is_nan (&wop);
+ break;
+ }
default:
fprintf (stderr, "Bad switch\n");
abort ();
printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
- /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
- know that the exponent field is biased... we we cheat and avoid
- removing the bias value. */
switch (fmt) {
case fmt_single:
- boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) == 0));
- break;
+ {
+ sim_fpu wop;
+ sim_fpu_32to (&wop, op);
+ boolean = sim_fpu_is_infinity (&wop);
+ break;
+ }
case fmt_double:
- boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) == 0));
- break;
+ {
+ sim_fpu wop;
+ sim_fpu_64to (&wop, op);
+ boolean = sim_fpu_is_infinity (&wop);
+ break;
+ }
default:
printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
break;
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- boolean = (*(float *)&wop1 < *(float *)&wop2);
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ boolean = sim_fpu_is_lt (&wop1, &wop2);
+ break;
}
- break;
case fmt_double:
- boolean = (*(double *)&op1 < *(double *)&op2);
- break;
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ boolean = sim_fpu_is_lt (&wop1, &wop2);
+ break;
+ }
default:
fprintf (stderr, "Bad switch\n");
abort ();
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
- boolean = ((op1 & 0xFFFFFFFF) == (op2 & 0xFFFFFFFF));
- break;
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ boolean = sim_fpu_is_eq (&wop1, &wop2);
+ break;
+ }
case fmt_double:
- boolean = (op1 == op2);
- break;
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ boolean = sim_fpu_is_eq (&wop1, &wop2);
+ break;
+ }
default:
fprintf (stderr, "Bad switch\n");
abort ();
switch (fmt) {
case fmt_single:
{
- unsigned int wop = (unsigned int)op;
- float tmp = ((float)fabs((double)*(float *)&wop));
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop;
+ unsigned32 ans;
+ sim_fpu_32to (&wop, op);
+ sim_fpu_abs (&wop, &wop);
+ sim_fpu_to32 (&ans, &wop);
+ result = ans;
+ break;
}
- break;
case fmt_double:
{
- double tmp = (fabs(*(double *)&op));
- result = *(uword64 *)&tmp;
+ sim_fpu wop;
+ unsigned64 ans;
+ sim_fpu_64to (&wop, op);
+ sim_fpu_abs (&wop, &wop);
+ sim_fpu_to64 (&ans, &wop);
+ result = ans;
+ break;
}
default:
fprintf (stderr, "Bad switch\n");
switch (fmt) {
case fmt_single:
{
- unsigned int wop = (unsigned int)op;
- float tmp = ((float)0.0 - *(float *)&wop);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop;
+ unsigned32 ans;
+ sim_fpu_32to (&wop, op);
+ sim_fpu_neg (&wop, &wop);
+ sim_fpu_to32 (&ans, &wop);
+ result = ans;
+ break;
}
- break;
case fmt_double:
{
- double tmp = ((double)0.0 - *(double *)&op);
- result = *(uword64 *)&tmp;
+ sim_fpu wop;
+ unsigned64 ans;
+ sim_fpu_64to (&wop, op);
+ sim_fpu_neg (&wop, &wop);
+ sim_fpu_to64 (&ans, &wop);
+ result = ans;
+ break;
}
- break;
default:
fprintf (stderr, "Bad switch\n");
abort ();
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- float tmp = (*(float *)&wop1 + *(float *)&wop2);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ sim_fpu_add (&ans, &wop1, &wop2);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
}
- break;
case fmt_double:
{
- double tmp = (*(double *)&op1 + *(double *)&op2);
- result = *(uword64 *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ sim_fpu_add (&ans, &wop1, &wop2);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
}
- break;
default:
fprintf (stderr, "Bad switch\n");
abort ();
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- float tmp = (*(float *)&wop1 - *(float *)&wop2);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ sim_fpu_sub (&ans, &wop1, &wop2);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
}
break;
case fmt_double:
{
- double tmp = (*(double *)&op1 - *(double *)&op2);
- result = *(uword64 *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ sim_fpu_sub (&ans, &wop1, &wop2);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
}
break;
default:
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- float tmp = (*(float *)&wop1 * *(float *)&wop2);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ sim_fpu_mul (&ans, &wop1, &wop2);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
}
- break;
case fmt_double:
{
- double tmp = (*(double *)&op1 * *(double *)&op2);
- result = *(uword64 *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ sim_fpu_mul (&ans, &wop1, &wop2);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
}
- break;
default:
fprintf (stderr, "Bad switch\n");
abort ();
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- float tmp = (*(float *)&wop1 / *(float *)&wop2);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ sim_fpu_div (&ans, &wop1, &wop2);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
}
- break;
case fmt_double:
{
- double tmp = (*(double *)&op1 / *(double *)&op2);
- result = *(uword64 *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ sim_fpu_div (&ans, &wop1, &wop2);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
}
- break;
default:
fprintf (stderr, "Bad switch\n");
abort ();
switch (fmt) {
case fmt_single:
{
- unsigned int wop = (unsigned int)op;
- float tmp = ((float)1.0 / *(float *)&wop);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop, op);
+ sim_fpu_inv (&ans, &wop);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
}
- break;
case fmt_double:
{
- double tmp = ((double)1.0 / *(double *)&op);
- result = *(uword64 *)&tmp;
+ sim_fpu wop;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop, op);
+ sim_fpu_inv (&ans, &wop);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
}
- break;
default:
fprintf (stderr, "Bad switch\n");
abort ();
switch (fmt) {
case fmt_single:
{
- unsigned int wop = (unsigned int)op;
-#ifdef HAVE_SQRT
- float tmp = ((float)sqrt((double)*(float *)&wop));
- result = (uword64)*(unsigned int *)&tmp;
-#else
- /* TODO: Provide square-root */
- result = (uword64)0;
-#endif
+ sim_fpu wop;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop, op);
+ sim_fpu_sqrt (&ans, &wop);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
}
- break;
case fmt_double:
{
-#ifdef HAVE_SQRT
- double tmp = (sqrt(*(double *)&op));
- result = *(uword64 *)&tmp;
-#else
- /* TODO: Provide square-root */
- result = (uword64)0;
-#endif
+ sim_fpu wop;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop, op);
+ sim_fpu_sqrt (&ans, &wop);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
}
- break;
default:
fprintf (stderr, "Bad switch\n");
abort ();
}
uword64
-convert(sd,cia,rm,op,from,to)
- SIM_DESC sd;
- address_word cia;
- int rm;
- uword64 op;
- FP_formats from;
- FP_formats to;
+convert (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int rm,
+ uword64 op,
+ FP_formats from,
+ FP_formats to)
{
- uword64 result = 0;
+ sim_fpu wop;
+ sim_fpu_round round;
+ unsigned32 result32;
+ unsigned64 result64;
#ifdef DEBUG
printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
#endif /* DEBUG */
- /* The value "op" is converted to the destination format, rounding
- using mode "rm". When the destination is a fixed-point format,
- then a source value of Infinity, NaN or one which would round to
- an integer outside the fixed point range then an IEEE Invalid
- Operation condition is raised. */
- switch (to) {
- case fmt_single:
+ switch (rm)
{
- float tmp;
- switch (from) {
- case fmt_double:
- tmp = (float)(*(double *)&op);
- break;
-
- case fmt_word:
- tmp = (float)((int)(op & 0xFFFFFFFF));
- break;
-
- case fmt_long:
- tmp = (float)((word64)op);
- break;
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#if 0
- /* FIXME: This code is incorrect. The rounding mode does not
- round to integral values; it rounds to the nearest
- representable value in the format. */
-
- switch (rm) {
- case FP_RM_NEAREST:
- /* Round result to nearest representable value. When two
- representable values are equally near, round to the value
- that has a least significant bit of zero (i.e. is even). */
-#ifdef HAVE_ANINT
- tmp = (float)anint((double)tmp);
-#else
- /* TODO: Provide round-to-nearest */
-#endif
- break;
-
- case FP_RM_TOZERO:
- /* Round result to the value closest to, and not greater in
- magnitude than, the result. */
-#ifdef HAVE_AINT
- tmp = (float)aint((double)tmp);
-#else
- /* TODO: Provide round-to-zero */
-#endif
- break;
-
- case FP_RM_TOPINF:
- /* Round result to the value closest to, and not less than,
- the result. */
- tmp = (float)ceil((double)tmp);
- break;
-
- case FP_RM_TOMINF:
- /* Round result to the value closest to, and not greater than,
- the result. */
- tmp = (float)floor((double)tmp);
- break;
- }
-#endif /* 0 */
-
- result = (uword64)*(unsigned int *)&tmp;
+ case FP_RM_NEAREST:
+ /* Round result to nearest representable value. When two
+ representable values are equally near, round to the value
+ that has a least significant bit of zero (i.e. is even). */
+ round = sim_fpu_round_near;
+ break;
+ case FP_RM_TOZERO:
+ /* Round result to the value closest to, and not greater in
+ magnitude than, the result. */
+ round = sim_fpu_round_zero;
+ break;
+ case FP_RM_TOPINF:
+ /* Round result to the value closest to, and not less than,
+ the result. */
+ round = sim_fpu_round_up;
+ break;
+
+ case FP_RM_TOMINF:
+ /* Round result to the value closest to, and not greater than,
+ the result. */
+ round = sim_fpu_round_down;
+ break;
+ default:
+ round = 0;
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
- break;
-
- case fmt_double:
+
+ /* Convert the input to sim_fpu internal format */
+ switch (from)
{
- double tmp;
- word64 xxx;
-
- switch (from) {
- case fmt_single:
- {
- unsigned int wop = (unsigned int)op;
- tmp = (double)(*(float *)&wop);
- }
- break;
-
- case fmt_word:
- xxx = SIGNEXTEND((op & 0xFFFFFFFF),32);
- tmp = (double)xxx;
- break;
-
- case fmt_long:
- tmp = (double)((word64)op);
- break;
-
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#if 0
- /* FIXME: This code is incorrect. The rounding mode does not
- round to integral values; it rounds to the nearest
- representable value in the format. */
-
- switch (rm) {
- case FP_RM_NEAREST:
-#ifdef HAVE_ANINT
- tmp = anint(*(double *)&tmp);
-#else
- /* TODO: Provide round-to-nearest */
-#endif
- break;
-
- case FP_RM_TOZERO:
-#ifdef HAVE_AINT
- tmp = aint(*(double *)&tmp);
-#else
- /* TODO: Provide round-to-zero */
-#endif
- break;
-
- case FP_RM_TOPINF:
- tmp = ceil(*(double *)&tmp);
- break;
-
- case FP_RM_TOMINF:
- tmp = floor(*(double *)&tmp);
- break;
- }
-#endif /* 0 */
-
- result = *(uword64 *)&tmp;
+ case fmt_double:
+ sim_fpu_64to (&wop, op);
+ break;
+ case fmt_single:
+ sim_fpu_32to (&wop, op);
+ break;
+ case fmt_word:
+ sim_fpu_i32to (&wop, op, round);
+ break;
+ case fmt_long:
+ sim_fpu_i64to (&wop, op, round);
+ break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
- break;
- case fmt_word:
- case fmt_long:
- if (Infinity(op,from) || NaN(op,from) || (1 == 0/*TODO: check range */)) {
- printf("DBG: TODO: update FCSR\n");
- SignalExceptionFPE ();
- } else {
- if (to == fmt_word) {
- int tmp = 0;
- switch (from) {
- case fmt_single:
- {
- unsigned int wop = (unsigned int)op;
- tmp = (int)*((float *)&wop);
- }
- break;
- case fmt_double:
- tmp = (int)*((double *)&op);
-#ifdef DEBUG
- printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op),pr_addr(op),tmp);
-#endif /* DEBUG */
- break;
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
- result = (uword64)tmp;
- } else { /* fmt_long */
- word64 tmp = 0;
- switch (from) {
- case fmt_single:
- {
- unsigned int wop = (unsigned int)op;
- tmp = (word64)*((float *)&wop);
- }
- break;
- case fmt_double:
- tmp = (word64)*((double *)&op);
- break;
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
- result = (uword64)tmp;
- }
+ /* Convert sim_fpu format into the output */
+ /* The value WOP is converted to the destination format, rounding
+ using mode RM. When the destination is a fixed-point format, then
+ a source value of Infinity, NaN or one which would round to an
+ integer outside the fixed point range then an IEEE Invalid
+ Operation condition is raised. */
+ switch (to)
+ {
+ case fmt_single:
+ sim_fpu_round_32 (&wop, round, 0);
+ sim_fpu_to32 (&result32, &wop);
+ result64 = result32;
+ break;
+ case fmt_double:
+ sim_fpu_round_64 (&wop, round, 0);
+ sim_fpu_to64 (&result64, &wop);
+ break;
+ case fmt_word:
+ sim_fpu_to32i (&result32, &wop, round);
+ result64 = result32;
+ break;
+ case fmt_long:
+ sim_fpu_to64i (&result64, &wop, round);
+ break;
+ default:
+ result64 = 0;
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
- break;
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
+
#ifdef DEBUG
- printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result),DOFMT(to));
+ printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
#endif /* DEBUG */
- return(result);
+ return(result64);
}
-#endif /* HASFPU */
+
/*-- co-processor support routines ------------------------------------------*/
}
void
-cop_lw(sd,cia,coproc_num,coproc_reg,memword)
- SIM_DESC sd;
- address_word cia;
- int coproc_num, coproc_reg;
- unsigned int memword;
+cop_lw (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ unsigned int memword)
{
- switch (coproc_num) {
-#if defined(HASFPU)
+ switch (coproc_num)
+ {
case 1:
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
#ifdef DEBUG
- printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
+ printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
#endif
- StoreFPR(coproc_reg,fmt_word,(uword64)memword);
- FPR_STATE[coproc_reg] = fmt_uninterpreted;
- break;
-#endif /* HASFPU */
+ StoreFPR(coproc_reg,fmt_word,(uword64)memword);
+ FPR_STATE[coproc_reg] = fmt_uninterpreted;
+ break;
+ }
default:
#if 0 /* this should be controlled by a configuration option */
- sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
+ sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
#endif
- break;
- }
+ break;
+ }
return;
}
void
-cop_ld(sd,cia,coproc_num,coproc_reg,memword)
- SIM_DESC sd;
- address_word cia;
- int coproc_num, coproc_reg;
- uword64 memword;
+cop_ld (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ uword64 memword)
{
switch (coproc_num) {
-#if defined(HASFPU)
case 1:
- StoreFPR(coproc_reg,fmt_uninterpreted,memword);
- break;
-#endif /* HASFPU */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ StoreFPR(coproc_reg,fmt_uninterpreted,memword);
+ break;
+ }
default:
#if 0 /* this message should be controlled by a configuration option */
}
unsigned int
-cop_sw(sd,cia,coproc_num,coproc_reg)
- SIM_DESC sd;
- address_word cia;
- int coproc_num, coproc_reg;
+cop_sw (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg)
{
unsigned int value = 0;
- switch (coproc_num) {
-#if defined(HASFPU)
+ switch (coproc_num)
+ {
case 1:
-#if 1
- {
- FP_formats hold;
- hold = FPR_STATE[coproc_reg];
- FPR_STATE[coproc_reg] = fmt_word;
- value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
- FPR_STATE[coproc_reg] = hold;
- }
-#else
-#if 1
- value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
-#else
-#ifdef DEBUG
- printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg]));
-#endif /* DEBUG */
- value = (unsigned int)ValueFPR(coproc_reg,fmt_single);
-#endif
-#endif
- break;
-#endif /* HASFPU */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ FP_formats hold;
+ hold = FPR_STATE[coproc_reg];
+ FPR_STATE[coproc_reg] = fmt_word;
+ value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
+ FPR_STATE[coproc_reg] = hold;
+ break;
+ }
default:
#if 0 /* should be controlled by configuration option */
- sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
+ sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
#endif
- break;
- }
+ break;
+ }
return(value);
}
uword64
-cop_sd(sd,cia,coproc_num,coproc_reg)
- SIM_DESC sd;
- address_word cia;
- int coproc_num, coproc_reg;
+cop_sd (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg)
{
uword64 value = 0;
- switch (coproc_num) {
-#if defined(HASFPU)
+ switch (coproc_num)
+ {
case 1:
-#if 1
- value = ValueFPR(coproc_reg,fmt_uninterpreted);
-#else
-#if 1
- value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
-#else
-#ifdef DEBUG
- printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg]));
-#endif /* DEBUG */
- value = ValueFPR(coproc_reg,fmt_double);
-#endif
-#endif
- break;
-#endif /* HASFPU */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ value = ValueFPR(coproc_reg,fmt_uninterpreted);
+ break;
+ }
default:
#if 0 /* should be controlled by configuration option */
- sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
+ sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
#endif
- break;
- }
+ break;
+ }
return(value);
}
void
-decode_coproc(sd,cia,instruction)
- SIM_DESC sd;
- address_word cia;
- unsigned int instruction;
+decode_coproc (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ unsigned int instruction)
{
int coprocnum = ((instruction >> 26) & 3);
#if (WITH_IGEN > 1)
void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
void
-old_engine_run (sd, next_cpu_nr, siggnal)
+old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
#else
void
-sim_engine_run (sd, next_cpu_nr, siggnal)
+sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
#endif
SIM_DESC sd;
int next_cpu_nr; /* ignore */
+ int nr_cpus; /* ignore */
int siggnal; /* ignore */
{
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
#if !defined(FASTSIM)
unsigned int pipeline_count = 1;
#endif
#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
#endif
-#if (WITH_FLOATING_POINT == HARD_FLOATING_POINT != defined (HASFPU))
+#if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
#endif
CANCELDELAYSLOT();
}
- if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
- /* Deal with pending register updates: */
-#ifdef DEBUG
- printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
-#endif /* DEBUG */
- if (PENDING_OUT != PENDING_IN) {
- int loop;
- int index = PENDING_OUT;
- int total = PENDING_TOTAL;
- if (PENDING_TOTAL == 0) {
- fprintf(stderr,"FATAL: Mis-match on pending update pointers\n");
- exit(1);
- }
- for (loop = 0; (loop < total); loop++) {
-#ifdef DEBUG
- printf("DBG: BEFORE index = %d, loop = %d\n",index,loop);
-#endif /* DEBUG */
- if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) {
-#ifdef DEBUG
- printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]);
-#endif /* DEBUG */
- if (--(PENDING_SLOT_COUNT[index]) == 0) {
-#ifdef DEBUG
- printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]);
- printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index]));
-#endif /* DEBUG */
- if (PENDING_SLOT_REG[index] == COCIDX) {
-#if defined(HASFPU)
- SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
-#else
- ;
-#endif
- } else {
- REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
-#if defined(HASFPU)
- /* The only time we have PENDING updates to FPU
- registers, is when performing binary transfers. This
- means we should update the register type field. */
- if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
- FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
-#endif /* HASFPU */
- }
-#ifdef DEBUG
- printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]]));
-#endif /* DEBUG */
- PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1);
- PENDING_OUT++;
- if (PENDING_OUT == PSLOTS)
- PENDING_OUT = 0;
- PENDING_TOTAL--;
- }
- }
-#ifdef DEBUG
- printf("DBG: AFTER index = %d, loop = %d\n",index,loop);
-#endif /* DEBUG */
- index++;
- if (index == PSLOTS)
- index = 0;
- }
- }
-#ifdef DEBUG
- printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);
-#endif /* DEBUG */
- }
+ if (MIPSISA < 4)
+ PENDING_TICK();
#if !defined(FASTSIM)
if (sim_events_tickn (sd, pipeline_count))
}
+void
+pending_tick (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia)
+{
+ if (PENDING_TRACE)
+ sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
+ if (PENDING_OUT != PENDING_IN)
+ {
+ int loop;
+ int index = PENDING_OUT;
+ int total = PENDING_TOTAL;
+ if (PENDING_TOTAL == 0)
+ sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
+ for (loop = 0; (loop < total); loop++)
+ {
+ if (PENDING_SLOT_DEST[index] != NULL)
+ {
+ PENDING_SLOT_DELAY[index] -= 1;
+ if (PENDING_SLOT_DELAY[index] == 0)
+ {
+ if (PENDING_SLOT_BIT[index] >= 0)
+ switch (PENDING_SLOT_SIZE[index])
+ {
+ case 32:
+ if (PENDING_SLOT_VALUE[index])
+ *(unsigned32*)PENDING_SLOT_DEST[index] |=
+ BIT32 (PENDING_SLOT_BIT[index]);
+ else
+ *(unsigned32*)PENDING_SLOT_DEST[index] &=
+ BIT32 (PENDING_SLOT_BIT[index]);
+ break;
+ case 64:
+ if (PENDING_SLOT_VALUE[index])
+ *(unsigned64*)PENDING_SLOT_DEST[index] |=
+ BIT64 (PENDING_SLOT_BIT[index]);
+ else
+ *(unsigned64*)PENDING_SLOT_DEST[index] &=
+ BIT64 (PENDING_SLOT_BIT[index]);
+ break;
+ break;
+ }
+ else
+ switch (PENDING_SLOT_SIZE[index])
+ {
+ case 32:
+ *(unsigned32*)PENDING_SLOT_DEST[index] =
+ PENDING_SLOT_VALUE[index];
+ break;
+ case 64:
+ *(unsigned64*)PENDING_SLOT_DEST[index] =
+ PENDING_SLOT_VALUE[index];
+ break;
+ }
+ }
+ if (PENDING_OUT == index)
+ {
+ PENDING_SLOT_DEST[index] = NULL;
+ PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
+ PENDING_TOTAL--;
+ }
+ }
+ }
+ index = (index + 1) % PSLOTS;
+ }
+}
+
/*---------------------------------------------------------------------------*/
/*> EOF interp.c <*/