#define PROFILE (1)
#endif
+#include "bfd.h"
+#include "sim-main.h"
+#include "sim-utils.h"
+#include "sim-options.h"
+#include "sim-assert.h"
+
#include "config.h"
#include <stdio.h>
#include "getopt.h"
#include "libiberty.h"
-
+#include "bfd.h"
#include "callback.h" /* GDB simulator callback interface */
#include "remote-sim.h" /* GDB simulator interface */
#include "sysdep.h"
+#ifndef PARAMS
+#define PARAMS(x)
+#endif
+
+char* pr_addr PARAMS ((SIM_ADDR addr));
+char* pr_uword64 PARAMS ((uword64 addr));
+
#ifndef SIGBUS
#define SIGBUS SIGSEGV
#endif
#include "engine.c"
#undef SIM_MANIFESTS
-/* This variable holds the GDB view of the target endianness: */
-extern int target_byte_order;
+struct sim_state simulator;
/* The following reserved instruction value is used when a simulator
trap is required. NOTE: Care must be taken, since this value may be
used in later revisions of the MIPS ISA. */
-#define RSVD_INSTRUCTION (0x7C000000)
-#define RSVD_INSTRUCTION_AMASK (0x03FFFFFF)
+#define RSVD_INSTRUCTION (0x00000005)
+#define RSVD_INSTRUCTION_MASK (0xFC00003F)
+
+#define RSVD_INSTRUCTION_ARG_SHIFT 6
+#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
+
/* NOTE: These numbers depend on the processor architecture being
simulated: */
#define AccessLength_SEXTIBYTE (5)
#define AccessLength_SEPTIBYTE (6)
#define AccessLength_DOUBLEWORD (7)
+#define AccessLength_QUADWORD (15)
#if defined(HASFPU)
/* FPU registers must be one of the following types. All other values
and then going back to the point where the context was saved and
changing some state before continuing. i.e. the ability to perform
UNDOs on simulations. It would also allow the simulation of
- shared-memory multi-processor systems. */
+ shared-memory multi-processor systems.
+
+ [NOTE: This is now partially implemented] */
static host_callback *callback = NULL; /* handle onto the current callback structure */
#define SP (registers[29])
#define RA (registers[31])
+
+/* start-sanitize-r5900 */
+/*
+The R5900 has 128 bit registers, but the hi 64 bits are only touched by
+multimedia (MMI) instructions. The normal mips instructions just use the
+lower 64 bits. To avoid changing the older parts of the simulator to
+handle this weirdness, the high 64 bits of each register are kept in
+a separate array (registers1). The high 64 bits of any register are by
+convention refered by adding a '1' to the end of the normal register's
+name. So LO still refers to the low 64 bits of the LO register, LO1
+refers to the high 64 bits of that same register.
+*/
+
+/* The high part of each register */
+static ut_reg registers1[LAST_EMBED_REGNUM + 1];
+
+#define GPR1 (®isters1[0])
+
+#define LO1 (registers1[33])
+#define HI1 (registers1[34])
+
+#define BYTES_IN_MMI_REGS (sizeof(registers[0])+sizeof(registers1[0]))
+#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
+#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
+#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
+
+#define BYTES_IN_MIPS_REGS (sizeof(registers[0]))
+#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
+#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
+#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
+
+
+/*
+SUB_REG_FETCH - return as lvalue some sub-part of a "register"
+ T - type of the sub part
+ TC - # of T's in the mips part of the "register"
+ I - index (from 0) of desired sub part
+ A - low part of "register"
+ A1 - high part of register
+*/
+#define SUB_REG_FETCH(T,TC,A,A1,I) (*(((T*)(((I) < (TC)) ? (A) : (A1))) + ((I) % (TC))))
+
+/*
+GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
+ where <type> has two letters:
+ 1 is S=signed or U=unsigned
+ 2 is B=byte H=halfword W=word D=doubleword
+*/
+
+#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed char, BYTES_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed short, HALFWORDS_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed int, WORDS_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed long long, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
+
+#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned char, BYTES_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned short, HALFWORDS_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned int, WORDS_IN_MIPS_REGS, A, A1, I)
+#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned long long,DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
+
+
+
+#define GPR_SB(R,I) SUB_REG_SB(®isters[R], ®isters1[R], I)
+#define GPR_SH(R,I) SUB_REG_SH(®isters[R], ®isters1[R], I)
+#define GPR_SW(R,I) SUB_REG_SW(®isters[R], ®isters1[R], I)
+#define GPR_SD(R,I) SUB_REG_SD(®isters[R], ®isters1[R], I)
+
+#define GPR_UB(R,I) SUB_REG_UB(®isters[R], ®isters1[R], I)
+#define GPR_UH(R,I) SUB_REG_UH(®isters[R], ®isters1[R], I)
+#define GPR_UW(R,I) SUB_REG_UW(®isters[R], ®isters1[R], I)
+#define GPR_UD(R,I) SUB_REG_UD(®isters[R], ®isters1[R], I)
+
+
+#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
+#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
+#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
+#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
+
+#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
+#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
+#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
+#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
+
+#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
+#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
+#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
+#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
+
+#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
+#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
+#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
+#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
+
+
+
+#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
+#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
+#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
+#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
+
+#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
+#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
+#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
+#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
+
+#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
+#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
+#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
+#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
+
+#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
+#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
+#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
+#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
+/* end-sanitize-r5900 */
+
+
+/* start-sanitize-r5900 */
+static ut_reg SA; /* the shift amount register */
+/* end-sanitize-r5900 */
+
static ut_reg EPC = 0; /* Exception PC */
#if defined(HASFPU)
static FP_formats fpr_state[32];
#endif /* HASFPU */
-/* VR4300 CP0 configuration register: */
-static unsigned int CONFIG = 0;
-
/* The following are internal simulator state variables: */
static ut_reg IPC = 0; /* internal Instruction PC */
static ut_reg DSPC = 0; /* delay-slot PC */
#define status_ERL (1 << 2) /* Error level */
#define status_RP (1 << 27) /* Reduced Power mode */
-#define config_EP_mask (0xF)
-#define config_EP_shift (27)
-#define config_EP_D (0x0)
-#define config_EP_DxxDxx (0x6)
-
-#define config_BE (1 << 15)
-
#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
#if defined(HASFPU)
extern void sim_error PARAMS((char *fmt,...));
static void ColdReset PARAMS((void));
static int AddressTranslation PARAMS((uword64 vAddr,int IorD,int LorS,uword64 *pAddr,int *CCA,int host,int raw));
-static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64 pAddr,uword64 vAddr,int raw));
-static uword64 LoadMemory PARAMS((int CCA,int AccessLength,uword64 pAddr,uword64 vAddr,int IorD,int raw));
+static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64 MemElem1,uword64 pAddr,uword64 vAddr,int raw));
+static void LoadMemory PARAMS((uword64*memvalp,uword64*memval1p,int CCA,int AccessLength,uword64 pAddr,uword64 vAddr,int IorD,int raw));
static void SignalException PARAMS((int exception,...));
-static void simulate PARAMS((void));
static long getnum PARAMS((char *value));
-extern void sim_size PARAMS((unsigned int newsize));
extern void sim_set_profile PARAMS((int frequency));
static unsigned int power2 PARAMS((unsigned int value));
pending_slot_count[pending_in] = 2;\
pending_slot_reg[pending_in] = (r);\
pending_slot_value[pending_in] = (uword64)(v);\
-/*printf("DBG: FILL reg %d value = 0x%08X%08X\n",(r),WORD64HI(v),WORD64LO(v));*/\
+/*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\
pending_total++;\
pending_in++;\
if (pending_in == PSLOTS)\
static int HIACCESS = 0;
static int LOACCESS = 0;
+static int HI1ACCESS = 0;
+static int LO1ACCESS = 0;
+
+/* ??? The 4300 and a few other processors have interlocks on hi/lo register
+ reads, and hence do not have this problem. To avoid spurious warnings,
+ we just disable this always. */
+#if 1
+#define CHECKHILO(s)
+#else
/* The HIACCESS and LOACCESS counts are used to ensure that
corruptions caused by using the HI or LO register to close to a
following operation are spotted. */
static ut_reg HLPC = 0;
-
-/* TODO: The 4300 has interlocks so we should not need to warn of the possible over-write (CHECK THIS) */
/* If either of the preceding two instructions have accessed the HI or
LO registers, then the values they see should be
undefined. However, to keep the simulator world simple, we just let
them use the value read and raise a warning to notify the user: */
#define CHECKHILO(s) {\
- if ((HIACCESS != 0) || (LOACCESS != 0))\
- sim_warning("%s over-writing HI and LO registers values (PC = 0x%08X%08X HLPC = 0x%08X%08X)\n",(s),(unsigned int)(PC>>32),(unsigned int)(PC&0xFFFFFFFF),(unsigned int)(HLPC>>32),(unsigned int)(HLPC&0xFFFFFFFF));\
+ if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
+ sim_warning("%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
}
+#endif
/* NOTE: We keep the following status flags as bit values (1 for true,
0 for false). This allows them to be used in binary boolean
/* Hardware configuration. Affects endianness of LoadMemory and
StoreMemory and the endianness of Kernel and Supervisor mode
execution. The value is 0 for little-endian; 1 for big-endian. */
-#define BigEndianMem ((CONFIG & config_BE) ? 1 : 0)
-/* NOTE: Problems will occur if the simulator memory model does not
- match the host program expectation. i.e. if the host is writing
- big-endian values to a little-endian memory model. */
+#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
+/*(state & simBE) ? 1 : 0)*/
+
+/* ByteSwapMem */
+/* This is true if the host and target have different endianness. */
+#define ByteSwapMem (CURRENT_TARGET_BYTE_ORDER != CURRENT_HOST_BYTE_ORDER)
/* ReverseEndian */
/* This mode is selected if in User mode with the RE bit being set in
/* The endianness for load and store instructions (0=little;1=big). In
User mode this endianness may be switched by setting the state_RE
bit in the SR register. Thus, BigEndianCPU may be computed as
- (BigEndienMem EOR ReverseEndian). */
+ (BigEndianMem EOR ReverseEndian). */
#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
#if !defined(FASTSIM) || defined(PROFILE)
engine. */
static unsigned int instruction_fetches = 0;
static unsigned int instruction_fetch_overflow = 0;
-static unsigned int pipeline_ticks = 0;
#endif
/* Flags in the "state" variable: */
-#define simSTOP (1 << 0) /* 0 = execute; 1 = stop simulation */
-#define simSTEP (1 << 1) /* 0 = run; 1 = single-step */
#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
#define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */
-#define simHOSTBE (1 << 10) /* 0 = little-endian; 1 = big-endian (host endianness) */
-/* Whilst simSTOP is not set, the simulator control loop should just
- keep simulating instructions. The simSTEP flag is used to force
- single-step execution. */
-#define simBE (1 << 16) /* 0 = little-endian; 1 = big-endian (target endianness) */
#define simPCOC0 (1 << 17) /* COC[1] from current */
#define simPCOC1 (1 << 18) /* COC[1] from previous */
#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
-#define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
-#define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
+#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
+#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
static unsigned int state = 0;
-static unsigned int rcexit = 0; /* _exit() reason code holder */
#define DELAYSLOT() {\
if (state & simDELAYSLOT)\
state |= simDELAYSLOT;\
}
+#define JALDELAYSLOT() {\
+ DELAYSLOT ();\
+ state |= simJALDELAYSLOT;\
+ }
+
#define NULLIFY() {\
state &= ~simDELAYSLOT;\
state |= simSKIPNEXT;\
}
+#define INDELAYSLOT() ((state & simDELAYSLOT) != 0)
+#define INJALDELAYSLOT() ((state & simJALDELAYSLOT) != 0)
+
#define K0BASE (0x80000000)
#define K0SIZE (0x20000000)
#define K1BASE (0xA0000000)
#define K1SIZE (0x20000000)
-/* Very simple memory model to start with: */
-static unsigned char *membank = NULL;
-static ut_reg membank_base = K1BASE;
-static unsigned membank_size = (1 << 20); /* (16 << 20); */ /* power-of-2 */
-
/* Simple run-time monitor support */
static unsigned char *monitor = NULL;
static ut_reg monitor_base = 0xBFC00000;
#if defined(TRACE)
static char *tracefile = "trace.din"; /* default filename for trace log */
static FILE *tracefh = NULL;
+static void open_trace PARAMS((void));
#endif /* TRACE */
#if defined(PROFILE)
static int profile_shift = 0; /* address shift amount */
#endif /* PROFILE */
-/* The following are used to provide shortcuts to the required version
- of host<->target copying. This avoids run-time conditionals, which
- would slow the simulator throughput. */
-typedef unsigned int (*fnptr_read_word) PARAMS((unsigned char *memory));
-typedef unsigned int (*fnptr_swap_word) PARAMS((unsigned int data));
-typedef uword64 (*fnptr_read_long) PARAMS((unsigned char *memory));
-typedef uword64 (*fnptr_swap_long) PARAMS((uword64 data));
-static fnptr_read_word host_read_word;
-static fnptr_read_long host_read_long;
-static fnptr_swap_word host_swap_word;
-static fnptr_swap_long host_swap_long;
+static SIM_RC
+mips_option_handler (sd, opt, arg)
+ SIM_DESC sd;
+ int opt;
+ char *arg;
+{
+ switch (opt)
+ {
+ case 'l':
+ if (arg != NULL) {
+ char *tmp;
+ tmp = (char *)malloc(strlen(arg) + 1);
+ if (tmp == NULL)
+ callback->printf_filtered(callback,"Failed to allocate buffer for logfile name \"%s\"\n",optarg);
+ else {
+ strcpy(tmp,optarg);
+ logfile = tmp;
+ }
+ }
+ return SIM_RC_OK;
+
+ case 'n': /* OK */
+ callback->printf_filtered(callback,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg);
+ return SIM_RC_FAIL;
+
+ case 't': /* ??? */
+#if defined(TRACE)
+ /* Eventually the simTRACE flag could be treated as a toggle, to
+ allow external control of the program points being traced
+ (i.e. only from main onwards, excluding the run-time setup,
+ etc.). */
+ if (arg == NULL)
+ state |= simTRACE;
+ else if (strcmp (arg, "yes") == 0)
+ state |= simTRACE;
+ else if (strcmp (arg, "no") == 0)
+ state &= ~simTRACE;
+ else
+ {
+ fprintf (stderr, "Unreconized trace option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+ return SIM_RC_OK;
+#else /* !TRACE */
+ fprintf(stderr,"\
+Simulator constructed without tracing support (for performance).\n\
+Re-compile simulator with \"-DTRACE\" to enable this option.\n");
+ return SIM_RC_FAIL;
+#endif /* !TRACE */
+
+ case 'z':
+#if defined(TRACE)
+ if (optarg != NULL) {
+ char *tmp;
+ tmp = (char *)malloc(strlen(optarg) + 1);
+ if (tmp == NULL)
+ {
+ callback->printf_filtered(callback,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
+ return SIM_RC_FAIL;
+ }
+ else {
+ strcpy(tmp,optarg);
+ tracefile = tmp;
+ callback->printf_filtered(callback,"Placing trace information into file \"%s\"\n",tracefile);
+ }
+ }
+#endif /* TRACE */
+ return SIM_RC_OK;
+
+ case 'p':
+#if defined(PROFILE)
+ state |= simPROFILE;
+ return SIM_RC_OK;
+#else /* !PROFILE */
+ fprintf(stderr,"\
+Simulator constructed without profiling support (for performance).\n\
+Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
+ return SIM_RC_FAIL;
+#endif /* !PROFILE */
+
+ case 'x':
+#if defined(PROFILE)
+ profile_nsamples = (unsigned)getnum(optarg);
+#endif /* PROFILE */
+ return SIM_RC_OK;
+
+ case 'y':
+#if defined(PROFILE)
+ sim_set_profile((int)getnum(optarg));
+#endif /* PROFILE */
+ return SIM_RC_OK;
+
+ }
+
+ return SIM_RC_OK;
+}
+
+static const OPTION mips_options[] =
+{
+ { {"log", required_argument, NULL,'l'},
+ 'l', "FILE", "Log file",
+ mips_option_handler },
+ { {"name", required_argument, NULL,'n'},
+ 'n', "MODEL", "Select arch model",
+ mips_option_handler },
+ { {"profile", optional_argument, NULL,'p'},
+ 'p', "on|off", "Enable profiling",
+ mips_option_handler },
+ { {"trace", optional_argument, NULL,'t'},
+ 't', "on|off", "Enable tracing",
+ mips_option_handler },
+ { {"tracefile",required_argument, NULL,'z'},
+ 'z', "FILE", "Write trace to file",
+ mips_option_handler },
+ { {"frequency",required_argument, NULL,'y'},
+ 'y', "FREQ", "Profile frequency",
+ mips_option_handler },
+ { {"samples", required_argument, NULL,'x'},
+ 'y', "SIZE", "Profile sample size",
+ mips_option_handler },
+ { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
+};
+
+
+static void
+interrupt_event (SIM_DESC sd, void *data)
+{
+ SignalException (Interrupt);
+}
+
+
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
-void
-sim_open (args)
- char *args;
+SIM_DESC
+sim_open (kind,cb,argv)
+ SIM_OPEN_KIND kind;
+ host_callback *cb;
+ char **argv;
{
+ SIM_DESC sd = &simulator;
+
+ STATE_OPEN_KIND (sd) = kind;
+ STATE_MAGIC (sd) = SIM_MAGIC_NUMBER;
+ STATE_CALLBACK (sd) = cb;
+ callback = cb;
+ CPU_STATE (STATE_CPU (sd, 0)) = sd;
+
+ /* FIXME: watchpoints code shouldn't need this */
+ STATE_WATCHPOINTS (sd)->pc = &(PC);
+ STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+ STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
+
+ /* memory defaults (unless sim_size was here first) */
+ if (STATE_MEM_SIZE (sd) == 0)
+ STATE_MEM_SIZE (sd) = (2 << 20);
+ STATE_MEM_BASE (sd) = K1BASE;
+
if (callback == NULL) {
fprintf(stderr,"SIM Error: sim_open() called without callbacks attached\n");
- return;
+ return 0;
}
- /* The following ensures that the standard file handles for stdin,
- stdout and stderr are initialised: */
- callback->init(callback);
-
state = 0;
- CHECKSIM();
- if (state & simEXCEPTION) {
- fprintf(stderr,"This simulator is not suitable for this host configuration\n");
- exit(1);
- }
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ return 0;
+ sim_add_option_table (sd, mips_options);
+
+ /* getopt will print the error message so we just have to exit if this fails.
+ FIXME: Hmmm... in the case of gdb we need getopt to call
+ print_filtered. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
- {
- int data = 0x12;
- if (*((char *)&data) != 0x12)
- state |= simHOSTBE; /* big-endian host */
- }
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ /* verify assumptions the simulator made about the host type system.
+ This macro does not return if there is a problem */
+ CHECKSIM();
#if defined(HASFPU)
/* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
and DOUBLE binary formats. This is a bit nasty, requiring that we
trust the explicit manifests held in the source: */
+ /* TODO: We need to cope with the simulated target and the host not
+ having the same endianness. This will require the high and low
+ words of a (double) to be swapped when converting between the
+ host and the simulated target. */
{
- unsigned int s[2];
- s[state & simHOSTBE ? 0 : 1] = 0x40805A5A;
- s[state & simHOSTBE ? 1 : 0] = 0x00000000;
-
- /* TODO: We need to cope with the simulated target and the host
- not having the same endianness. This will require the high and
- low words of a (double) to be swapped when converting between
- the host and the simulated target. */
-
- if (((float)4.01102924346923828125 != *(float *)(s + ((state & simHOSTBE) ? 0 : 1))) || ((double)523.2939453125 != *(double *)s)) {
- fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
- fprintf(stderr,"*(float *)s = %.20f (4.01102924346923828125)\n",*(float *)s);
- fprintf(stderr,"*(double *)s = %.20f (523.2939453125)\n",*(double *)s);
- exit(1);
- }
+ union {
+ unsigned int i[2];
+ double d;
+ float f[2];
+ } s;
+
+ s.d = (double)523.2939453125;
+
+ if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125
+ || s.i[1] != 0x40805A5A))
+ || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125
+ || s.i[0] != 0x40805A5A)))
+ {
+ fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
+ return 0;
+ }
}
#endif /* HASFPU */
}
}
- /* It would be good if we could select particular named MIPS
- architecture simulators. However, having a pre-built, fixed
- engine would mean including multiple engines. If the simulator is
- changed to a run-time conditional version, then the ability to
- select a particular architecture would be straightforward. */
- if (args != NULL) {
- int c;
- char *cline;
- char **argv;
- int argc;
- static struct option cmdline[] = {
- {"help", 0,0,'h'},
- {"log", 1,0,'l'},
- {"name", 1,0,'n'},
- {"profile", 0,0,'p'},
- {"size", 1,0,'s'},
- {"trace", 0,0,'t'},
- {"tracefile",1,0,'z'},
- {"frequency",1,0,'y'},
- {"samples", 1,0,'x'},
- {0, 0,0,0}
- };
-
- /* Unfortunately, getopt_long() is designed to be used with
- vectors, where the first option is normally program name (and
- ignored). We cheat by creating a dummy first argument, so that
- we can use the standard argument processing. */
-#define DUMMYARG "simulator "
- cline = (char *)malloc(strlen(args) + strlen(DUMMYARG) + 1);
- if (cline == NULL) {
- fprintf(stderr,"Failed to allocate memory for command line buffer\n");
- exit(1);
- }
- sprintf(cline,"%s%s",DUMMYARG,args);
- argv = buildargv(cline);
- for (argc = 0; argv[argc]; argc++);
-
- /* Unfortunately, getopt_long() assumes that it is ignoring the
- first argument (normally the program name). This means it
- ignores the first option on our "args" line. */
- optind = 0; /* Force reset of argument processing */
- while (1) {
- int option_index = 0;
-
- c = getopt_long(argc,argv,"hn:s:tp",cmdline,&option_index);
- if (c == -1)
- break;
-
- switch (c) {
- case 'h':
- callback->printf_filtered(callback,"Usage:\n\t\
-target sim [-h] [--log=<file>] [--name=<model>] [--size=<amount>]");
-#if defined(TRACE)
- callback->printf_filtered(callback," [-t [--tracefile=<name>]]");
-#endif /* TRACE */
-#if defined(PROFILE)
- callback->printf_filtered(callback," [-p [--frequency=<count>] [--samples=<count>]]");
-#endif /* PROFILE */
- callback->printf_filtered(callback,"\n");
- break;
-
- case 'l':
- if (optarg != NULL) {
- char *tmp;
- tmp = (char *)malloc(strlen(optarg) + 1);
- if (tmp == NULL)
- callback->printf_filtered(callback,"Failed to allocate buffer for logfile name \"%s\"\n",optarg);
- else {
- strcpy(tmp,optarg);
- logfile = tmp;
- }
- }
- break;
-
- case 'n':
- callback->printf_filtered(callback,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg);
- break;
-
- case 's':
- membank_size = (unsigned)getnum(optarg);
- break;
-
- case 't':
-#if defined(TRACE)
- /* Eventually the simTRACE flag could be treated as a toggle, to
- allow external control of the program points being traced
- (i.e. only from main onwards, excluding the run-time setup,
- etc.). */
- state |= simTRACE;
-#else /* !TRACE */
- fprintf(stderr,"\
-Simulator constructed without tracing support (for performance).\n\
-Re-compile simulator with \"-DTRACE\" to enable this option.\n");
-#endif /* !TRACE */
- break;
-
- case 'z':
-#if defined(TRACE)
- if (optarg != NULL) {
- char *tmp;
- tmp = (char *)malloc(strlen(optarg) + 1);
- if (tmp == NULL)
- callback->printf_filtered(callback,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
- else {
- strcpy(tmp,optarg);
- tracefile = tmp;
- callback->printf_filtered(callback,"Placing trace information into file \"%s\"\n",tracefile);
- }
- }
-#endif /* TRACE */
- break;
-
- case 'p':
-#if defined(PROFILE)
- state |= simPROFILE;
-#else /* !PROFILE */
- fprintf(stderr,"\
-Simulator constructed without profiling support (for performance).\n\
-Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
-#endif /* !PROFILE */
- break;
-
- case 'x':
-#if defined(PROFILE)
- profile_nsamples = (unsigned)getnum(optarg);
-#endif /* PROFILE */
- break;
-
- case 'y':
-#if defined(PROFILE)
- sim_set_profile((int)getnum(optarg));
-#endif /* PROFILE */
- break;
-
- default:
- callback->printf_filtered(callback,"Warning: Simulator getopt returned unrecognised code 0x%08X\n",c);
- case '?':
- break;
- }
- }
-
-#if 0
- if (optind < argc) {
- callback->printf_filtered(callback,"Warning: Ignoring spurious non-option arguments ");
- while (optind < argc)
- callback->printf_filtered(callback,"\"%s\" ",argv[optind++]);
- callback->printf_filtered(callback,"\n");
- }
-#endif
-
- freeargv(argv);
- }
if (logfile != NULL) {
if (strcmp(logfile,"-") == 0)
}
}
+ /* FIXME: In the future both of these malloc's can be replaced by
+ calls to sim-core. */
+
/* If the host has "mmap" available we could use it to provide a
very large virtual address space for the simulator, since memory
would only be allocated within the "mmap" space as it is
accessed. This can also be linked to the architecture specific
support, required to simulate the MMU. */
- sim_size(membank_size);
- /* NOTE: The above will also have enabled any profiling state */
-
- ColdReset();
- /* If we were providing a more complete I/O, co-processor or memory
- simulation, we should perform any "device" initialisation at this
- point. This can include pre-loading memory areas with particular
- patterns (e.g. simulating ROM monitors). */
+ sim_size(STATE_MEM_SIZE (sd));
+ /* NOTE: The above will also have enabled any profiling state! */
- /* We can start writing to the memory, now that the processor has
- been reset: */
+ /* Create the monitor address space as well */
monitor = (unsigned char *)calloc(1,monitor_size);
- if (!monitor) {
- fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size);
- } else {
- unsigned loop;
- /* Entry into the IDT monitor is via fixed address vectors, and
- not using machine instructions. To avoid clashing with use of
- the MIPS TRAP system, we place our own (simulator specific)
- "undefined" instructions into the relevant vector slots. */
- for (loop = 0; (loop < monitor_size); loop += 4) {
- uword64 vaddr = (monitor_base + loop);
- uword64 paddr;
- int cca;
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
- StoreMemory(cca,AccessLength_WORD,(RSVD_INSTRUCTION | ((loop >> 2) & RSVD_INSTRUCTION_AMASK)),paddr,vaddr,isRAW);
- }
- /* The PMON monitor uses the same address space, but rather than
- branching into it the address of a routine is loaded. We can
- cheat for the moment, and direct the PMON routine to IDT style
- instructions within the monitor space. This relies on the IDT
- monitor not using the locations from 0xBFC00500 onwards as its
- entry points.*/
- for (loop = 0; (loop < 24); loop++)
- {
- uword64 vaddr = (monitor_base + 0x500 + (loop * 4));
- uword64 paddr;
- int cca;
- unsigned int value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
- switch (loop)
- {
- case 0: /* read */
- value = 7;
- break;
-
- case 1: /* write */
- value = 8;
- break;
-
- case 2: /* open */
- value = 6;
- break;
-
- case 3: /* close */
- value = 10;
- break;
-
- case 5: /* printf */
- value = ((0x500 - 16) / 8); /* not an IDT reason code */
- break;
-
- case 8: /* cliexit */
- value = 17;
- break;
- }
- /* FIXME - should monitor_base be SIM_ADDR?? */
- value = ((unsigned int)monitor_base + (value * 8));
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
- else
- sim_error("Failed to write to monitor space 0x%08X%08X",WORD64HI(vaddr),WORD64LO(vaddr));
- }
- }
+ if (!monitor)
+ fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n",
+ monitor_size);
#if defined(TRACE)
- if (state & simTRACE) {
- tracefh = fopen(tracefile,"wb+");
- if (tracefh == NULL) {
- sim_warning("Failed to create file \"%s\", writing trace information to stderr.",tracefile);
- tracefh = stderr;
- }
- }
+ if (state & simTRACE)
+ open_trace();
#endif /* TRACE */
- return;
+ return sd;
}
+#if defined(TRACE)
+static void
+open_trace()
+{
+ tracefh = fopen(tracefile,"wb+");
+ if (tracefh == NULL)
+ {
+ sim_warning("Failed to create file \"%s\", writing trace information to stderr.",tracefile);
+ tracefh = stderr;
+ }
+}
+#endif /* TRACE */
+
/* For the profile writing, we write the data in the host
endianness. This unfortunately means we are assuming that the
profile file we create is processed on the same host executing the
char buff[4];
int res = 1;
- if (state & simHOSTBE) {
+ if (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN) {
buff[3] = ((val >> 0) & 0xFF);
buff[2] = ((val >> 8) & 0xFF);
buff[1] = ((val >> 16) & 0xFF);
{
char buff[2];
int res = 1;
- if (state & simHOSTBE) {
+ if (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN) {
buff[1] = ((val >> 0) & 0xFF);
buff[0] = ((val >> 8) & 0xFF);
} else {
}
void
-sim_close (quitting)
+sim_close (sd, quitting)
+ SIM_DESC sd;
int quitting;
{
#ifdef DEBUG
#if defined(PROFILE)
if ((state & simPROFILE) && (profile_hist != NULL)) {
- unsigned short *p = profile_hist;
FILE *pf = fopen("gmon.out","wb");
unsigned loop;
else {
int ok;
#ifdef DEBUG
- printf("DBG: minpc = 0x%08X\n",(unsigned int)profile_minpc);
- printf("DBG: maxpc = 0x%08X\n",(unsigned int)profile_maxpc);
+ printf("DBG: minpc = 0x%s\n",pr_addr(profile_minpc));
+ printf("DBG: maxpc = 0x%s\n",pr_addr(profile_maxpc));
#endif /* DEBUG */
ok = writeout32(pf,(unsigned int)profile_minpc);
if (ok)
fclose(logfh);
logfh = NULL;
- if (membank)
- free(membank); /* cfree not available on all hosts */
- membank = NULL;
+ if (STATE_MEMORY (sd) != NULL)
+ free(STATE_MEMORY (sd)); /* cfree not available on all hosts */
+ STATE_MEMORY (sd) = NULL;
return;
}
-void
-sim_resume (step,signal)
- int step, signal;
-{
-#ifdef DEBUG
- printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step,signal,membank);
-#endif /* DEBUG */
-
- if (step)
- state |= simSTEP; /* execute only a single instruction */
- else
- state &= ~(simSTOP | simSTEP); /* execute until event */
-
- state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */
-
- /* Start executing instructions from the current state (set
- explicitly by register updates, or by sim_create_inferior): */
-
- simulate();
- return;
-}
int
-sim_write (addr,buffer,size)
+sim_write (sd,addr,buffer,size)
+ SIM_DESC sd;
SIM_ADDR addr;
unsigned char *buffer;
int size;
/* Return the number of bytes written, or zero if error. */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_write(0x%08X%08X,buffer,%d);\n",WORD64HI(addr),WORD64LO(addr),size);
+ callback->printf_filtered(callback,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif
/* We provide raw read and write routines, since we do not want to
int cca;
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
uword64 value = ((uword64)(*buffer++));
- StoreMemory(cca,AccessLength_BYTE,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_BYTE,value,0,paddr,vaddr,isRAW);
}
vaddr++;
index &= ~1; /* logical operations usually quicker than arithmetic on RISC systems */
value = ((uword64)(*buffer++) << 0);
value |= ((uword64)(*buffer++) << 8);
}
- StoreMemory(cca,AccessLength_HALFWORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_HALFWORD,value,0,paddr,vaddr,isRAW);
}
vaddr += 2;
index &= ~2;
value |= ((uword64)(*buffer++) << 16);
value |= ((uword64)(*buffer++) << 24);
}
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
}
vaddr += 4;
index &= ~4;
value |= ((uword64)(*buffer++) << 48);
value |= ((uword64)(*buffer++) << 56);
}
- StoreMemory(cca,AccessLength_DOUBLEWORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_DOUBLEWORD,value,0,paddr,vaddr,isRAW);
}
vaddr += 8;
}
}
int
-sim_read (addr,buffer,size)
+sim_read (sd,addr,buffer,size)
+ SIM_DESC sd;
SIM_ADDR addr;
unsigned char *buffer;
int size;
/* Return the number of bytes read, or zero if error. */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_read(0x%08X%08X,buffer,%d);\n",WORD64HI(addr),WORD64LO(addr),size);
+ callback->printf_filtered(callback,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif /* DEBUG */
/* TODO: Perform same optimisation as the sim_write() code
int cca;
vaddr = (uword64)addr + index;
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&cca,isTARGET,isRAW)) {
- value = LoadMemory(cca,AccessLength_BYTE,paddr,vaddr,isDATA,isRAW);
+ LoadMemory(&value,NULL,cca,AccessLength_BYTE,paddr,vaddr,isDATA,isRAW);
buffer[index] = (unsigned char)(value&0xFF);
} else
break;
}
void
-sim_store_register (rn,memory)
+sim_store_register (sd,rn,memory)
+ SIM_DESC sd;
int rn;
unsigned char *memory;
{
+ /* NOTE: gdb (the client) stores registers in target byte order
+ while the simulator uses host byte order */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_store_register(%d,*memory=0x%08X%08X);\n",rn,*((unsigned int *)memory),*((unsigned int *)(memory + 4)));
+ callback->printf_filtered(callback,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
#endif /* DEBUG */
/* Unfortunately this suffers from the same problem as the register
numbering one. We need to know what the width of each logical
register number is for the architecture being simulated. */
+
if (register_widths[rn] == 0)
- sim_warning("Invalid register width for %d (register store ignored)",rn);
- else {
- if (register_widths[rn] == 32)
- registers[rn] = host_read_word(memory);
- else
- registers[rn] = host_read_long(memory);
- }
+ sim_warning("Invalid register width for %d (register store ignored)",rn);
+ else
+ {
+ if (register_widths[rn] == 32)
+ registers[rn] = T2H_4 (*(unsigned int*)memory);
+ else
+ registers[rn] = T2H_8 (*(uword64*)memory);
+ }
return;
}
void
-sim_fetch_register (rn,memory)
+sim_fetch_register (sd,rn,memory)
+ SIM_DESC sd;
int rn;
unsigned char *memory;
{
+ /* NOTE: gdb (the client) stores registers in target byte order
+ while the simulator uses host byte order */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_fetch_register(%d=0x%08X%08X,mem) : place simulator registers into memory\n",rn,WORD64HI(registers[rn]),WORD64LO(registers[rn]));
+ callback->printf_filtered(callback,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
#endif /* DEBUG */
if (register_widths[rn] == 0)
- sim_warning("Invalid register width for %d (register fetch ignored)",rn);
- else {
- if (register_widths[rn] == 32)
- *((unsigned int *)memory) = host_swap_word((unsigned int)(registers[rn] & 0xFFFFFFFF));
- else /* 64bit register */
- *((uword64 *)memory) = host_swap_long(registers[rn]);
- }
- return;
-}
-
-void
-sim_stop_reason (reason,sigrc)
- enum sim_stop *reason;
- int *sigrc;
-{
-/* We can have "*reason = {sim_exited, sim_stopped, sim_signalled}", so
- sim_exited *sigrc = argument to exit()
- sim_stopped *sigrc = exception number
- sim_signalled *sigrc = signal number
-*/
- if (state & simEXCEPTION) {
- /* If "sim_signalled" is used, GDB expects normal SIGNAL numbers,
- and not the MIPS specific exception codes. */
-#if 1
- /* For some reason, sending GDB a sim_signalled reason cause it to
- terminate out. */
- *reason = sim_stopped;
-#else
- *reason = sim_signalled;
-#endif
- switch ((CAUSE >> 2) & 0x1F) {
- case Interrupt:
- *sigrc = SIGINT; /* wrong type of interrupt, but it will do for the moment */
- break;
-
- case TLBModification:
- case TLBLoad:
- case TLBStore:
- case AddressLoad:
- case AddressStore:
- case InstructionFetch:
- case DataReference:
- *sigrc = SIGBUS;
- break;
-
- case ReservedInstruction:
- case CoProcessorUnusable:
- *sigrc = SIGILL;
- break;
-
- case IntegerOverflow:
- case FPE:
- *sigrc = SIGFPE;
- break;
-
- case Trap:
- case Watch:
- case SystemCall:
- case BreakPoint:
- *sigrc = SIGTRAP;
- break;
-
- default : /* Unknown internal exception */
- *sigrc = SIGQUIT;
- break;
+ sim_warning("Invalid register width for %d (register fetch ignored)",rn);
+ else
+ {
+ if (register_widths[rn] == 32)
+ *((unsigned int *)memory) = H2T_4 ((unsigned int)(registers[rn] & 0xFFFFFFFF));
+ else /* 64bit register */
+ *((uword64 *)memory) = H2T_8 (registers[rn]);
}
- } else if (state & simEXIT) {
-#if 0
- printf("DBG: simEXIT (%d)\n",rcexit);
-#endif
- *reason = sim_exited;
- *sigrc = rcexit;
- } else { /* assume single-stepping */
- *reason = sim_stopped;
- *sigrc = SIGTRAP;
- }
- state &= ~(simEXCEPTION | simEXIT);
+
return;
}
+
void
-sim_info (verbose)
+sim_info (sd,verbose)
+ SIM_DESC sd;
int verbose;
{
/* Accessed from the GDB "info files" command: */
callback->printf_filtered(callback,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT ? 64 : 32));
- callback->printf_filtered(callback,"%s endian memory model\n",(BigEndianMem ? "Big" : "Little"));
+ callback->printf_filtered(callback,"%s endian memory model\n",
+ (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
+ ? "Big" : "Little"));
- callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%08X%08X\n",(unsigned int)membank_size,WORD64HI(membank_base),WORD64LO(membank_base));
+ callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%s\n",
+ STATE_MEM_SIZE (sd),
+ pr_addr (STATE_MEM_BASE (sd)));
#if !defined(FASTSIM)
if (instruction_fetch_overflow != 0)
callback->printf_filtered(callback,"Instruction fetches = 0x%08X%08X\n",instruction_fetch_overflow,instruction_fetches);
else
callback->printf_filtered(callback,"Instruction fetches = %d\n",instruction_fetches);
- callback->printf_filtered(callback,"Pipeline ticks = %d\n",pipeline_ticks);
+ callback->printf_filtered(callback,"Pipeline ticks = %ld\n",
+ (long) sim_events_time (sd));
/* It would be a useful feature, if when performing multi-cycle
simulations (rather than single-stepping) we keep the start and
end times of the execution, so that we can give a performance
/* profile minpc */
/* profile maxpc */
- return;
-}
+ return;
+}
+
+SIM_RC
+sim_load (sd,prog,abfd,from_tty)
+ SIM_DESC sd;
+ char *prog;
+ bfd *abfd;
+ int from_tty;
+{
+ bfd *prog_bfd;
+
+ prog_bfd = sim_load_file (sd,
+ STATE_MY_NAME (sd),
+ callback,
+ prog,
+ /* pass NULL for abfd, we always open our own */
+ NULL,
+ STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG);
+ if (prog_bfd == NULL)
+ return SIM_RC_FAIL;
+ sim_analyze_program (sd, prog_bfd);
+
+ /* Configure/verify the target byte order and other runtime
+ configuration options */
+ sim_config (sd, PREFERED_TARGET_BYTE_ORDER(prog_bfd));
+
+ /* (re) Write the monitor trap address handlers into the monitor
+ (eeprom) address space. This can only be done once the target
+ endianness has been determined. */
+ {
+ unsigned loop;
+ /* Entry into the IDT monitor is via fixed address vectors, and
+ not using machine instructions. To avoid clashing with use of
+ the MIPS TRAP system, we place our own (simulator specific)
+ "undefined" instructions into the relevant vector slots. */
+ for (loop = 0; (loop < monitor_size); loop += 4) {
+ uword64 vaddr = (monitor_base + loop);
+ uword64 paddr;
+ int cca;
+ if (AddressTranslation(vaddr, isDATA, isSTORE, &paddr, &cca, isTARGET, isRAW))
+ StoreMemory(cca, AccessLength_WORD,
+ (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT)),
+ 0, paddr, vaddr, isRAW);
+ }
+ /* The PMON monitor uses the same address space, but rather than
+ branching into it the address of a routine is loaded. We can
+ cheat for the moment, and direct the PMON routine to IDT style
+ instructions within the monitor space. This relies on the IDT
+ monitor not using the locations from 0xBFC00500 onwards as its
+ entry points.*/
+ for (loop = 0; (loop < 24); loop++)
+ {
+ uword64 vaddr = (monitor_base + 0x500 + (loop * 4));
+ uword64 paddr;
+ int cca;
+ unsigned int value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
+ switch (loop)
+ {
+ case 0: /* read */
+ value = 7;
+ break;
+
+ case 1: /* write */
+ value = 8;
+ break;
+
+ case 2: /* open */
+ value = 6;
+ break;
+
+ case 3: /* close */
+ value = 10;
+ break;
+
+ case 5: /* printf */
+ value = ((0x500 - 16) / 8); /* not an IDT reason code */
+ break;
+
+ case 8: /* cliexit */
+ value = 17;
+ break;
+
+ case 11: /* flush_cache */
+ value = 28;
+ break;
+ }
+ /* FIXME - should monitor_base be SIM_ADDR?? */
+ value = ((unsigned int)monitor_base + (value * 8));
+ if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
+ else
+ sim_error("Failed to write to monitor space 0x%s",pr_addr(vaddr));
+
+ /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
+ vaddr -= 0x300;
+ if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
+ else
+ sim_error("Failed to write to monitor space 0x%s",pr_addr(vaddr));
+ }
+ }
-int
-sim_load (prog,from_tty)
- char *prog;
- int from_tty;
-{
- /* Return non-zero if the caller should handle the load. Zero if
- we have loaded the image. */
- return(-1);
+ return SIM_RC_OK;
}
-void
-sim_create_inferior (start_address,argv,env)
- SIM_ADDR start_address;
+SIM_RC
+sim_create_inferior (sd, argv,env)
+ SIM_DESC sd;
char **argv;
char **env;
{
+
#ifdef DEBUG
- printf("DBG: sim_create_inferior entered: start_address = 0x%08X\n",start_address);
+ printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
+ pr_addr(PC));
#endif /* DEBUG */
- /* Prepare to execute the program to be simulated */
- /* argv and env are NULL terminated lists of pointers */
+ ColdReset();
+ /* If we were providing a more complete I/O, co-processor or memory
+ simulation, we should perform any "device" initialisation at this
+ point. This can include pre-loading memory areas with particular
+ patterns (e.g. simulating ROM monitors). */
#if 1
- PC = (uword64)start_address;
+ PC = (uword64) STATE_START_ADDR(sd);
#else
/* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */
- PC = SIGNEXTEND(start_address,32);
+ PC = SIGNEXTEND(bfd_get_start_address(prog_bfd),32);
#endif
- /* NOTE: GDB normally sets the PC explicitly. However, this call is
- used by other clients of the simulator. */
+
+ /* Prepare to execute the program to be simulated */
+ /* argv and env are NULL terminated lists of pointers */
if (argv || env) {
#if 0 /* def DEBUG */
true at the moment. */
}
- return;
+ return SIM_RC_OK;
}
void
-sim_kill ()
+sim_kill (sd)
+ SIM_DESC sd;
{
#if 1
/* This routine should be for terminating any existing simulation
not an issue. It should *NOT* be used to terminate the
simulator. */
#else /* do *NOT* call sim_close */
- sim_close(1); /* Do not hang on errors */
+ sim_close(sd, 1); /* Do not hang on errors */
/* This would also be the point where any memory mapped areas used
by the simulator should be released. */
#endif
return;
}
-ut_reg
-sim_get_quit_code ()
-{
- /* The standard MIPS PCS (Procedure Calling Standard) uses V0(r2) as
- the function return value. However, it may be more correct for
- this to return the argument to the exit() function (if
- called). */
- return(V0);
-}
-
-void
-sim_set_callbacks (p)
- host_callback *p;
-{
- callback = p;
- return;
-}
-
typedef enum {e_terminate,e_help,e_setmemsize,e_reset} e_cmds;
static struct t_sim_command {
};
void
-sim_do_command (cmd)
+sim_do_command (sd,cmd)
+ SIM_DESC sd;
char *cmd;
{
struct t_sim_command *cptr;
sim_set_profile_size (n)
int n;
{
+ SIM_DESC sd = &simulator;
#if defined(PROFILE)
if (state & simPROFILE) {
int bsize;
/* Since we KNOW that the memory banks are a power-of-2 in size: */
profile_nsamples = power2(n);
- profile_minpc = membank_base;
- profile_maxpc = (membank_base + membank_size);
+ profile_minpc = STATE_MEM_BASE (sd);
+ profile_maxpc = (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd));
/* Just in-case we are sampling every address: NOTE: The shift
right of 2 is because we only have word-aligned PC addresses. */
- if (profile_nsamples > (membank_size >> 2))
- profile_nsamples = (membank_size >> 2);
+ if (profile_nsamples > (STATE_MEM_SIZE (sd) >> 2))
+ profile_nsamples = (STATE_MEM_SIZE (sd) >> 2);
/* Since we are dealing with power-of-2 values: */
- profile_shift = (((membank_size >> 2) / profile_nsamples) - 1);
+ profile_shift = (((STATE_MEM_SIZE (sd) >> 2) / profile_nsamples) - 1);
bsize = (profile_nsamples * sizeof(unsigned short));
if (profile_hist == NULL)
void
sim_size(newsize)
- unsigned int newsize;
+ int newsize;
{
+ SIM_DESC sd = &simulator;
char *new;
/* Used by "run", and internally, to set the simulated memory size */
if (newsize == 0) {
- callback->printf_filtered(callback,"Zero not valid: Memory size still 0x%08X bytes\n",membank_size);
+ callback->printf_filtered(callback,"Zero not valid: Memory size still 0x%08X bytes\n",STATE_MEM_SIZE (sd));
return;
}
newsize = power2(newsize);
- if (membank == NULL)
- new = (char *)calloc(64,(membank_size / 64));
+ if (STATE_MEMORY (sd) == NULL)
+ new = (char *)calloc(64,(STATE_MEM_SIZE (sd) / 64));
else
- new = (char *)realloc(membank,newsize);
+ new = (char *)realloc(STATE_MEMORY (sd),newsize);
if (new == NULL) {
- if (membank == NULL)
- sim_error("Not enough VM for simulation memory of 0x%08X bytes",membank_size);
+ if (STATE_MEMORY (sd) == NULL)
+ sim_error("Not enough VM for simulation memory of 0x%08X bytes",STATE_MEM_SIZE (sd));
else
- sim_warning("Failed to resize memory (still 0x%08X bytes)",membank_size);
+ sim_warning("Failed to resize memory (still 0x%08X bytes)",STATE_MEM_SIZE (sd));
} else {
- membank_size = (unsigned)newsize;
- membank = new;
+ STATE_MEM_SIZE (sd) = (unsigned)newsize;
+ STATE_MEMORY (sd) = new;
#if defined(PROFILE)
/* Ensure that we sample across the new memory range */
sim_set_profile_size(profile_nsamples);
}
int
-sim_trace()
+sim_trace(sd)
+ SIM_DESC sd;
{
+ sim_io_eprintf (sd, "Sim trace not supported");
+#if 0
/* This routine is called by the "run" program, when detailed
execution information is required. Rather than executing a single
instruction, and looping around externally... we just start
#if defined(TRACE)
/* Ensure tracing is enabled, if available */
- if (tracefh != NULL)
- state |= simTRACE;
+ if (tracefh == NULL)
+ {
+ open_trace();
+ state |= simTRACE;
+ }
#endif /* TRACE */
+#if 0
state &= ~(simSTOP | simSTEP); /* execute until event */
+#endif
state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */
/* Start executing instructions from the current state (set
explicitly by register updates, or by sim_create_inferior): */
simulate();
+#endif
return(1);
}
sim_monitor(reason)
unsigned int reason;
{
+ SIM_DESC sd = &simulator;
+#ifdef DEBUG
+ printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
+#endif /* DEBUG */
+
/* The IDT monitor actually allows two instructions per vector
slot. However, the simulator currently causes a trap on each
individual instruction. We cheat, and lose the bottom bit. */
case 17: /* void _exit() */
sim_warning("sim_monitor(17): _exit(int reason) to be coded");
- state |= (simSTOP | simEXIT); /* stop executing code */
- rcexit = (unsigned int)(A0 & 0xFFFFFFFF);
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited,
+ (unsigned int)(A0 & 0xFFFFFFFF));
+ break;
+
+ case 28 : /* PMON flush_cache */
break;
case 55: /* void get_mem_info(unsigned int *ptr) */
/* Memory size */
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) {
- value = (uword64)membank_size;
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
+ value = (uword64)STATE_MEM_SIZE (sd);
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
/* We re-do the address translations, in-case the block
overlaps a memory boundary: */
value = 0;
vaddr += (AccessLength_WORD + 1);
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) {
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_WORD,0,value,paddr,vaddr,isRAW);
vaddr += (AccessLength_WORD + 1);
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL))
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
+ StoreMemory(cca,AccessLength_WORD,value,0,paddr,vaddr,isRAW);
else
failed = -1;
} else
char tmp[40];
enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
int width = 0, trunc = 0, haddot = 0, longlong = 0;
- int base = 10;
s++;
for (; *s; s++) {
if (strchr ("dobxXulscefg%", *s))
break;
default:
- sim_warning("TODO: sim_monitor(%d) : PC = 0x%08X%08X",reason,WORD64HI(IPC),WORD64LO(IPC));
- sim_warning("(Arguments : A0 = 0x%08X%08X : A1 = 0x%08X%08X : A2 = 0x%08X%08X : A3 = 0x%08X%08X)",WORD64HI(A0),WORD64LO(A0),WORD64HI(A1),WORD64LO(A1),WORD64HI(A2),WORD64LO(A2),WORD64HI(A3),WORD64LO(A3));
+ sim_warning("TODO: sim_monitor(%d) : PC = 0x%s",reason,pr_addr(IPC));
+ sim_warning("(Arguments : A0 = 0x%s : A1 = 0x%s : A2 = 0x%s : A3 = 0x%s)",pr_addr(A0),pr_addr(A1),pr_addr(A2),pr_addr(A3));
break;
}
return;
}
+/* Store a word into memory. */
+
+static void
+store_word (vaddr, val)
+ uword64 vaddr;
+ t_reg val;
+{
+ uword64 paddr;
+ int uncached;
+
+ if ((vaddr & 3) != 0)
+ SignalException (AddressStore);
+ else
+ {
+ if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
+ isTARGET, isREAL))
+ {
+ const uword64 mask = 7;
+ uword64 memval;
+ unsigned int byte;
+
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
+ byte = (vaddr & mask) ^ (BigEndianCPU << 2);
+ memval = ((uword64) val) << (8 * byte);
+ StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
+ isREAL);
+ }
+ }
+}
+
+/* Load a word from memory. */
+
+static t_reg
+load_word (vaddr)
+ uword64 vaddr;
+{
+ if ((vaddr & 3) != 0)
+ SignalException (AddressLoad);
+ else
+ {
+ uword64 paddr;
+ int uncached;
+
+ if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
+ isTARGET, isREAL))
+ {
+ const uword64 mask = 0x7;
+ const unsigned int reverse = ReverseEndian ? 1 : 0;
+ const unsigned int bigend = BigEndianCPU ? 1 : 0;
+ uword64 memval;
+ unsigned int byte;
+
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
+ LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
+ isDATA, isREAL);
+ byte = (vaddr & mask) ^ (bigend << 2);
+ return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
+ }
+ }
+
+ return 0;
+}
+
+/* Simulate the mips16 entry and exit pseudo-instructions. These
+ would normally be handled by the reserved instruction exception
+ code, but for ease of simulation we just handle them directly. */
+
+static void
+mips16_entry (insn)
+ unsigned int insn;
+{
+ int aregs, sregs, rreg;
+
+#ifdef DEBUG
+ printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
+#endif /* DEBUG */
+
+ aregs = (insn & 0x700) >> 8;
+ sregs = (insn & 0x0c0) >> 6;
+ rreg = (insn & 0x020) >> 5;
+
+ /* This should be checked by the caller. */
+ if (sregs == 3)
+ abort ();
+
+ if (aregs < 5)
+ {
+ int i;
+ t_reg tsp;
+
+ /* This is the entry pseudo-instruction. */
+
+ for (i = 0; i < aregs; i++)
+ store_word ((uword64) (SP + 4 * i), registers[i + 4]);
+
+ tsp = SP;
+ SP -= 32;
+
+ if (rreg)
+ {
+ tsp -= 4;
+ store_word ((uword64) tsp, RA);
+ }
+
+ for (i = 0; i < sregs; i++)
+ {
+ tsp -= 4;
+ store_word ((uword64) tsp, registers[16 + i]);
+ }
+ }
+ else
+ {
+ int i;
+ t_reg tsp;
+
+ /* This is the exit pseudo-instruction. */
+
+ tsp = SP + 32;
+
+ if (rreg)
+ {
+ tsp -= 4;
+ RA = load_word ((uword64) tsp);
+ }
+
+ for (i = 0; i < sregs; i++)
+ {
+ tsp -= 4;
+ registers[i + 16] = load_word ((uword64) tsp);
+ }
+
+ SP += 32;
+
+ if (aregs == 5)
+ {
+ FGR[0] = WORD64LO (GPR[4]);
+ fpr_state[0] = fmt_uninterpreted;
+ }
+ else if (aregs == 6)
+ {
+ FGR[0] = WORD64LO (GPR[5]);
+ FGR[1] = WORD64LO (GPR[4]);
+ fpr_state[0] = fmt_uninterpreted;
+ fpr_state[1] = fmt_uninterpreted;
+ }
+
+ PC = RA;
+ }
+}
+
void
-#ifdef _MSC_VER
sim_warning(char *fmt,...)
-#else
-sim_warning(fmt)
- char *fmt;
-#endif
{
+ char buf[256];
va_list ap;
- va_start(ap,fmt);
+
+ va_start (ap,fmt);
+ vsprintf (buf, fmt, ap);
+ va_end (ap);
+
if (logfh != NULL) {
-#if 1
- fprintf(logfh,"SIM Warning: ");
- fprintf(logfh,fmt,ap);
- fprintf(logfh,"\n");
-#else /* we should provide a method of routing log messages to the simulator output stream */
- callback->printf_filtered(callback,"SIM Warning: ");
- callback->printf_filtered(callback,fmt,ap);
-#endif
+ fprintf(logfh,"SIM Warning: %s\n", buf);
+ } else {
+ callback->printf_filtered(callback,"SIM Warning: %s\n", buf);
}
- va_end(ap);
- SignalException(SimulatorFault,"");
+ /* This used to call SignalException with a SimulatorFault, but that causes
+ the simulator to exit, and that is inappropriate for a warning. */
return;
}
void
-#ifdef _MSC_VER
sim_error(char *fmt,...)
-#else
-sim_error(fmt)
- char *fmt;
-#endif
{
+ char buf[256];
va_list ap;
- va_start(ap,fmt);
- callback->printf_filtered(callback,"SIM Error: ");
- callback->printf_filtered(callback,fmt,ap);
- va_end(ap);
- SignalException(SimulatorFault,"");
+
+ va_start (ap,fmt);
+ vsprintf (buf, fmt, ap);
+ va_end (ap);
+
+ callback->printf_filtered(callback,"SIM Error: %s", buf);
+ SignalException (SimulatorFault, buf);
return;
}
static
-#ifdef _MSC_VER
void dotrace(FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
-#else
-void dotrace(tracefh,type,address,width,comment)
- FILE *tracefh;
- int type;
- SIM_ADDR address;
- int width;
- char *comment;
-#endif
{
if (state & simTRACE) {
va_list ap;
- fprintf(tracefh,"%d %08x%08x ; width %d ; ",
- type,(unsigned long)(address>>32),(unsigned long)(address&0xffffffff),width);
+ fprintf(tracefh,"%d %s ; width %d ; ",
+ type,
+ pr_addr(address),
+ width);
va_start(ap,comment);
- fprintf(tracefh,comment,ap);
+ vfprintf(tracefh,comment,ap);
va_end(ap);
fprintf(tracefh,"\n");
}
}
#endif /* TRACE */
-/*---------------------------------------------------------------------------*/
-/*-- host<->target transfers ------------------------------------------------*/
-/*---------------------------------------------------------------------------*/
-/* The following routines allow conditionals to be avoided during the
- simulation, at the cost of increasing the image and source size. */
-
-static unsigned int
-#ifdef _MSC_VER
-xfer_direct_word(unsigned char *memory)
-#else
-xfer_direct_word(memory)
- unsigned char *memory;
-#endif
-{
- return *((unsigned int *)memory);
-}
-
-static uword64
-#ifdef _MSC_VER
-xfer_direct_long(unsigned char *memory)
-#else
-xfer_direct_long(memory)
- unsigned char *memory;
-#endif
-{
- return *((uword64 *)memory);
-}
-
-static unsigned int
-#ifdef _MSC_VER
-swap_direct_word(unsigned int data)
-#else
-swap_direct_word(data)
- unsigned int data;
-#endif
-{
- return data;
-}
-
-static uword64
-#ifdef _MSC_VER
-swap_direct_long(uword64 data)
-#else
-swap_direct_long(data)
- uword64 data;
-#endif
-{
- return data;
-}
-
-static unsigned int
-#ifdef _MSC_VER
-xfer_big_word(unsigned char *memory)
-#else
-xfer_big_word(memory)
- unsigned char *memory;
-#endif
-{
- return ((memory[0] << 24) | (memory[1] << 16) | (memory[2] << 8) | memory[3]);
-}
-
-static uword64
-#ifdef _MSC_VER
-xfer_big_long(unsigned char *memory)
-#else
-xfer_big_long(memory)
- unsigned char *memory;
-#endif
-{
- return (((uword64)memory[0] << 56) | ((uword64)memory[1] << 48)
- | ((uword64)memory[2] << 40) | ((uword64)memory[3] << 32)
- | ((uword64)memory[4] << 24) | ((uword64)memory[5] << 16)
- | ((uword64)memory[6] << 8) | ((uword64)memory[7]));
-}
-
-static unsigned int
-#ifdef _MSC_VER
-xfer_little_word(unsigned char *memory)
-#else
-xfer_little_word(memory)
- unsigned char *memory;
-#endif
-{
- return ((memory[3] << 24) | (memory[2] << 16) | (memory[1] << 8) | memory[0]);
-}
-
-static uword64
-#ifdef _MSC_VER
-xfer_little_long(unsigned char *memory)
-#else
-xfer_little_long(memory)
- unsigned char *memory;
-#endif
-{
- return (((uword64)memory[7] << 56) | ((uword64)memory[6] << 48)
- | ((uword64)memory[5] << 40) | ((uword64)memory[4] << 32)
- | ((uword64)memory[3] << 24) | ((uword64)memory[2] << 16)
- | ((uword64)memory[1] << 8) | (uword64)memory[0]);
-}
-
-static unsigned int
-#ifdef _MSC_VER
-swap_word(unsigned int data)
-#else
-swap_word(data)
- unsigned int data;
-#endif
-{
- unsigned int result;
- result = data ^ ((data << 16) | (data >> 16));
- result &= ~0x00FF0000;
- data = (data << 24) | (data >> 8);
- return data ^ (result >> 8);
-}
-
-static uword64
-#ifdef _MSC_VER
-swap_long(uword64 data)
-#else
-swap_long(data)
- uword64 data;
-#endif
-{
- unsigned int tmphi = WORD64HI(data);
- unsigned int tmplo = WORD64LO(data);
- tmphi = swap_word(tmphi);
- tmplo = swap_word(tmplo);
- /* Now swap the HI and LO parts */
- return SET64LO(tmphi) | SET64HI(tmplo);
-}
-
/*---------------------------------------------------------------------------*/
/*-- simulator engine -------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
SR &= ~(status_SR | status_TS | status_RP);
SR |= (status_ERL | status_BEV);
- /* VR4300 starts in Big-Endian mode */
- CONFIG &= ~(config_EP_mask << config_EP_shift);
- CONFIG |= ((config_EP_D << config_EP_shift) | config_BE);
- /* TODO: The VR4300 CONFIG register is not modelled fully at the moment */
#if defined(HASFPU) && (GPRLEN == (64))
/* Cheat and allow access to the complete register set immediately: */
}
#endif /* HASFPU */
- /* In reality this check should be performed at various points
- within the simulation, since it is possible to change the
- endianness of user programs. However, we perform the check here
- to ensure that the start-of-day values agree: */
- state |= (BigEndianCPU ? simBE : 0);
- if ((target_byte_order == 1234) != !(state & simBE)) {
- fprintf(stderr,"ColdReset: GDB (%s) and simulator (%s) do not agree on target endianness\n",
- target_byte_order == 1234 ? "little" : "big",
- state & simBE ? "big" : "little");
- exit(1);
- }
-
- if (!(state & simHOSTBE) == !(state & simBE)) {
- host_read_word = xfer_direct_word;
- host_read_long = xfer_direct_long;
- host_swap_word = swap_direct_word;
- host_swap_long = swap_direct_long;
- } else if (state & simHOSTBE) {
- host_read_word = xfer_little_word;
- host_read_long = xfer_little_long;
- host_swap_word = swap_word;
- host_swap_long = swap_long;
- } else { /* HOST little-endian */
- host_read_word = xfer_big_word;
- host_read_long = xfer_big_long;
- host_swap_word = swap_word;
- host_swap_long = swap_long;
- }
-
return;
}
int host;
int raw;
{
+ SIM_DESC sd = &simulator;
int res = -1; /* TRUE : Assume good return */
#ifdef DEBUG
- callback->printf_filtered(callback,"AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
+ callback->printf_filtered(callback,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
#endif
/* Check that the address is valid for this memory model */
vAddr &= 0xFFFFFFFF;
/* Treat the kernel memory spaces identically for the moment: */
- if ((membank_base == K1BASE) && (vAddr >= K0BASE) && (vAddr < (K0BASE + K0SIZE)))
+ if ((STATE_MEM_BASE (sd) == K1BASE) && (vAddr >= K0BASE) && (vAddr < (K0BASE + K0SIZE)))
vAddr += (K1BASE - K0BASE);
/* Also assume that the K1BASE memory wraps. This is required to
around the fact that the monitor memory is currently held in the
K1BASE space. */
if (((vAddr < monitor_base) || (vAddr >= (monitor_base + monitor_size))) && (vAddr >= K1BASE && vAddr < (K1BASE + K1SIZE)))
- vAddr = (K1BASE | (vAddr & (membank_size - 1)));
+ vAddr = (K1BASE | (vAddr & (STATE_MEM_SIZE (sd) - 1)));
*pAddr = vAddr; /* default for isTARGET */
*CCA = Uncached; /* not used for isHOST */
/* NOTE: This is a duplicate of the code that appears in the
LoadMemory and StoreMemory functions. They should be merged into
a single function (that can be in-lined if required). */
- if ((vAddr >= membank_base) && (vAddr < (membank_base + membank_size))) {
+ if ((vAddr >= STATE_MEM_BASE (sd)) && (vAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) {
if (host)
- *pAddr = (int)&membank[((unsigned int)(vAddr - membank_base) & (membank_size - 1))];
+ *pAddr = (int)&STATE_MEMORY (sd)[((unsigned int)(vAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1))];
} else if ((vAddr >= monitor_base) && (vAddr < (monitor_base + monitor_size))) {
if (host)
*pAddr = (int)&monitor[((unsigned int)(vAddr - monitor_base) & (monitor_size - 1))];
} else {
-#if 1 /* def DEBUG */
- sim_warning("Failed: AddressTranslation(0x%08X%08X,%s,%s,...) IPC = 0x%08X%08X",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),WORD64HI(IPC),WORD64LO(IPC));
+#ifdef DEBUG
+ sim_warning("Failed: AddressTranslation(0x%s,%s,%s,...) IPC = 0x%s",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),pr_addr(IPC));
#endif /* DEBUG */
res = 0; /* AddressTranslation has failed */
*pAddr = (SIM_ADDR)-1;
if (!raw) /* only generate exceptions on real memory transfers */
SignalException((LorS == isSTORE) ? AddressStore : AddressLoad);
+#ifdef DEBUG
else
- sim_warning("AddressTranslation for %s %s from 0x%08X%08X failed",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),WORD64HI(vAddr),WORD64LO(vAddr));
+ /* This is a normal occurance during gdb operation, for instance trying
+ to print parameters at function start before they have been setup,
+ and hence we should not print a warning except when debugging the
+ simulator. */
+ sim_warning("AddressTranslation for %s %s from 0x%s failed",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),pr_addr(vAddr));
+#endif
}
return(res);
which an implementation specific action is taken. The action taken
may increase performance, but must not change the meaning of the
program, or alter architecturally-visible state. */
-static void
+
+static void UNUSED
Prefetch(CCA,pAddr,vAddr,DATA,hint)
int CCA;
uword64 pAddr;
int hint;
{
#ifdef DEBUG
- callback->printf_filtered(callback,"Prefetch(%d,0x%08X%08X,0x%08X%08X,%d,%d);\n",CCA,WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),DATA,hint);
+ callback->printf_filtered(callback,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
#endif /* DEBUG */
/* For our simple memory model we do nothing */
alignment block of memory is read and loaded into the cache to
satisfy a load reference. At a minimum, the block is the entire
memory element. */
-static uword64
-LoadMemory(CCA,AccessLength,pAddr,vAddr,IorD,raw)
+static void
+LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw)
+ uword64* memvalp;
+ uword64* memval1p;
int CCA;
int AccessLength;
uword64 pAddr;
int IorD;
int raw;
{
- uword64 value;
+ SIM_DESC sd = &simulator;
+ uword64 value = 0;
+ uword64 value1 = 0;
#ifdef DEBUG
- if (membank == NULL)
- callback->printf_filtered(callback,"DBG: LoadMemory(%d,%d,0x%08X%08X,0x%08X%08X,%s,%s)\n",CCA,AccessLength,WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(raw ? "isRAW" : "isREAL"));
+ if (STATE_MEMORY (sd) == NULL)
+ callback->printf_filtered(callback,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(raw ? "isRAW" : "isREAL"));
#endif /* DEBUG */
#if defined(WARN_MEM)
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) {
/* In reality this should be a Bus Error */
- sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%08X%08X\n",AccessLength,(LOADDRMASK + 1)<<2,WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
}
#endif /* WARN_MEM */
/* If instruction fetch then we need to check that the two lo-order
bits are zero, otherwise raise a InstructionFetch exception: */
- if ((IorD == isINSTRUCTION) && ((pAddr & 0x3) != 0))
+ if ((IorD == isINSTRUCTION)
+ && ((pAddr & 0x3) != 0)
+ && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
SignalException(InstructionFetch);
else {
- unsigned int index;
+ unsigned int index = 0;
unsigned char *mem = NULL;
#if defined(TRACE)
/* NOTE: Quicker methods of decoding the address space can be used
when a real memory map is being simulated (i.e. using hi-order
address bits to select device). */
- if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) {
- index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1));
- mem = membank;
+ if ((pAddr >= STATE_MEM_BASE (sd)) && (pAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) {
+ index = ((unsigned int)(pAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1));
+ mem = STATE_MEMORY (sd);
} else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) {
index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1));
mem = monitor;
}
if (mem == NULL)
- sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_error("Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr));
else {
/* If we obtained the endianness of the host, and it is the same
as the target memory system we can optimise the memory
accesses. However, without that information we must perform
slow transfer, and hope that the compiler optimisation will
merge successive loads. */
- value = 0; /* no data loaded yet */
/* In reality we should always be loading a doubleword value (or
word value in 32bit memory worlds). The external code then
slots. */
if (BigEndianMem)
switch (AccessLength) { /* big-endian memory */
+ case AccessLength_QUADWORD :
+ value1 |= ((uword64)mem[index++] << 56);
+ case 14: /* AccessLength is one less than datalen */
+ value1 |= ((uword64)mem[index++] << 48);
+ case 13:
+ value1 |= ((uword64)mem[index++] << 40);
+ case 12:
+ value1 |= ((uword64)mem[index++] << 32);
+ case 11:
+ value1 |= ((unsigned int)mem[index++] << 24);
+ case 10:
+ value1 |= ((unsigned int)mem[index++] << 16);
+ case 9:
+ value1 |= ((unsigned int)mem[index++] << 8);
+ case 8:
+ value1 |= mem[index];
+
case AccessLength_DOUBLEWORD :
value |= ((uword64)mem[index++] << 56);
case AccessLength_SEPTIBYTE :
else {
index += (AccessLength + 1);
switch (AccessLength) { /* little-endian memory */
+ case AccessLength_QUADWORD :
+ value1 |= ((uword64)mem[--index] << 56);
+ case 14: /* AccessLength is one less than datalen */
+ value1 |= ((uword64)mem[--index] << 48);
+ case 13:
+ value1 |= ((uword64)mem[--index] << 40);
+ case 12:
+ value1 |= ((uword64)mem[--index] << 32);
+ case 11:
+ value1 |= ((uword64)mem[--index] << 24);
+ case 10:
+ value1 |= ((uword64)mem[--index] << 16);
+ case 9:
+ value1 |= ((uword64)mem[--index] << 8);
+ case 8:
+ value1 |= ((uword64)mem[--index] << 0);
+
case AccessLength_DOUBLEWORD :
value |= ((uword64)mem[--index] << 56);
case AccessLength_SEPTIBYTE :
}
#ifdef DEBUG
- printf("DBG: LoadMemory() : (offset %d) : value = 0x%08X%08X\n",(int)(pAddr & LOADDRMASK),WORD64HI(value),WORD64LO(value));
+ printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
+ (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
#endif /* DEBUG */
/* TODO: We could try and avoid the shifts when dealing with raw
memory accesses. This would mean updating the LoadMemory and
StoreMemory routines to avoid shifting the data before
returning or using it. */
- if (!raw) { /* do nothing for raw accessess */
- if (BigEndianMem)
- value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
- else /* little-endian only needs to be shifted up to the correct byte offset */
- value <<= ((pAddr & LOADDRMASK) * 8);
+ if (AccessLength <= AccessLength_DOUBLEWORD) {
+ if (!raw) { /* do nothing for raw accessess */
+ if (BigEndianMem)
+ value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
+ else /* little-endian only needs to be shifted up to the correct byte offset */
+ value <<= ((pAddr & LOADDRMASK) * 8);
+ }
}
#ifdef DEBUG
- printf("DBG: LoadMemory() : shifted value = 0x%08X%08X\n",WORD64HI(value),WORD64LO(value));
+ printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
+ pr_uword64(value1),pr_uword64(value));
#endif /* DEBUG */
}
}
- return(value);
+*memvalp = value;
+if (memval1p) *memval1p = value1;
}
-/* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
+
+/* Description from page A-23 of the "MIPS IV Instruction Set" manual
+ (revision 3.1) */
/* Store a value to memory. The specified data is stored into the
physical location pAddr using the memory hierarchy (data caches and
main memory) as specified by the Cache Coherence Algorithm
and the AccessLength field indicates which of the bytes within the
MemElem data should actually be stored; only these bytes in memory
will be changed. */
+
static void
-StoreMemory(CCA,AccessLength,MemElem,pAddr,vAddr,raw)
+StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
int CCA;
int AccessLength;
uword64 MemElem;
+ uword64 MemElem1; /* High order 64 bits */
uword64 pAddr;
uword64 vAddr;
int raw;
{
+ SIM_DESC sd = &simulator;
#ifdef DEBUG
- callback->printf_filtered(callback,"DBG: StoreMemory(%d,%d,0x%08X%08X,0x%08X%08X,0x%08X%08X,%s)\n",CCA,AccessLength,WORD64HI(MemElem),WORD64LO(MemElem),WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),(raw ? "isRAW" : "isREAL"));
+ callback->printf_filtered(callback,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s,%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr),(raw ? "isRAW" : "isREAL"));
#endif /* DEBUG */
#if defined(WARN_MEM)
sim_warning("StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)",CCA);
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
- sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%08X%08X\n",AccessLength,(LOADDRMASK + 1)<<2,WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
#endif /* WARN_MEM */
#if defined(TRACE)
routine. However, this would slow the simulator down with
run-time conditionals. */
{
- unsigned int index;
+ unsigned int index = 0;
unsigned char *mem = NULL;
- if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) {
- index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1));
- mem = membank;
+ if ((pAddr >= STATE_MEM_BASE (sd)) && (pAddr < (STATE_MEM_BASE (sd) + STATE_MEM_SIZE (sd)))) {
+ index = ((unsigned int)(pAddr - STATE_MEM_BASE (sd)) & (STATE_MEM_SIZE (sd) - 1));
+ mem = STATE_MEMORY (sd);
} else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) {
index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1));
mem = monitor;
}
if (mem == NULL)
- sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr),WORD64LO(pAddr));
+ sim_error("Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr));
else {
int shift = 0;
#ifdef DEBUG
- printf("DBG: StoreMemory: offset = %d MemElem = 0x%08X%08X\n",(unsigned int)(pAddr & LOADDRMASK),WORD64HI(MemElem),WORD64LO(MemElem));
+ printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
#endif /* DEBUG */
- if (BigEndianMem) {
- if (raw)
- shift = ((7 - AccessLength) * 8);
- else /* real memory access */
- shift = ((pAddr & LOADDRMASK) * 8);
- MemElem <<= shift;
- } else {
- /* no need to shift raw little-endian data */
- if (!raw)
- MemElem >>= ((pAddr & LOADDRMASK) * 8);
+ if (AccessLength <= AccessLength_DOUBLEWORD) {
+ if (BigEndianMem) {
+ if (raw)
+ shift = ((7 - AccessLength) * 8);
+ else /* real memory access */
+ shift = ((pAddr & LOADDRMASK) * 8);
+ MemElem <<= shift;
+ } else {
+ /* no need to shift raw little-endian data */
+ if (!raw)
+ MemElem >>= ((pAddr & LOADDRMASK) * 8);
+ }
}
#ifdef DEBUG
- printf("DBG: StoreMemory: shift = %d MemElem = 0x%08X%08X\n",shift,WORD64HI(MemElem),WORD64LO(MemElem));
+ printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
#endif /* DEBUG */
if (BigEndianMem) {
switch (AccessLength) { /* big-endian memory */
+ case AccessLength_QUADWORD :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 14 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 13 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 12 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 11 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 10 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 9 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+ MemElem1 <<= 8;
+ case 8 :
+ mem[index++] = (unsigned char)(MemElem1 >> 56);
+
case AccessLength_DOUBLEWORD :
mem[index++] = (unsigned char)(MemElem >> 56);
MemElem <<= 8;
} else {
index += (AccessLength + 1);
switch (AccessLength) { /* little-endian memory */
+ case AccessLength_QUADWORD :
+ mem[--index] = (unsigned char)(MemElem1 >> 56);
+ case 14 :
+ mem[--index] = (unsigned char)(MemElem1 >> 48);
+ case 13 :
+ mem[--index] = (unsigned char)(MemElem1 >> 40);
+ case 12 :
+ mem[--index] = (unsigned char)(MemElem1 >> 32);
+ case 11 :
+ mem[--index] = (unsigned char)(MemElem1 >> 24);
+ case 10 :
+ mem[--index] = (unsigned char)(MemElem1 >> 16);
+ case 9 :
+ mem[--index] = (unsigned char)(MemElem1 >> 8);
+ case 8 :
+ mem[--index] = (unsigned char)(MemElem1 >> 0);
+
case AccessLength_DOUBLEWORD :
mem[--index] = (unsigned char)(MemElem >> 56);
case AccessLength_SEPTIBYTE :
return;
}
+
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* Order loads and stores to synchronise shared memory. Perform the
action necessary to make the effects of groups of synchronizable
/* Signal an exception condition. This will result in an exception
that aborts the instruction. The instruction operation pseudocode
will never see a return from this function call. */
+
static void
-#ifdef _MSC_VER
SignalException (int exception,...)
-#else
-SignalException(exception)
- int exception;
-#endif
{
+ SIM_DESC sd = &simulator;
/* Ensure that any active atomic read/modify/write operation will fail: */
LLBIT = 0;
reality we should either simulate them, or allow the user to
ignore them at run-time. */
case Trap :
- sim_warning("Ignoring instruction TRAP (PC 0x%08X%08X)",WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("Ignoring instruction TRAP (PC 0x%s)",pr_addr(IPC));
break;
case ReservedInstruction :
space with suitable instruction values. For systems were
actual trap instructions are used, we would not need to
perform this magic. */
- if ((instruction & ~RSVD_INSTRUCTION_AMASK) == RSVD_INSTRUCTION) {
- sim_monitor(instruction & RSVD_INSTRUCTION_AMASK);
+ if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) {
+ sim_monitor( ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
PC = RA; /* simulate the return from the vector entry */
/* NOTE: This assumes that a branch-and-link style
instruction was used to enter the vector (which is the
case with the current IDT monitor). */
- break; /* out of the switch statement */
+ sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
+ }
+ /* Look for the mips16 entry and exit instructions, and
+ simulate a handler for them. */
+ else if ((IPC & 1) != 0
+ && (instruction & 0xf81f) == 0xe809
+ && (instruction & 0x0c0) != 0x0c0) {
+ mips16_entry (instruction);
+ sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
} /* else fall through to normal exception processing */
- sim_warning("ReservedInstruction 0x%08X at IPC = 0x%08X%08X",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("ReservedInstruction 0x%08X at IPC = 0x%s",instruction,pr_addr(IPC));
}
default:
#ifdef DEBUG
if (exception != BreakPoint)
- callback->printf_filtered(callback,"DBG: SignalException(%d) IPC = 0x%08X%08X\n",exception,WORD64HI(IPC),WORD64LO(IPC));
+ callback->printf_filtered(callback,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC));
#endif /* DEBUG */
/* Store exception code into current exception id variable (used
by exit code): */
/* TODO: If not simulating exceptions then stop the simulator
execution. At the moment we always stop the simulation. */
- state |= (simSTOP | simEXCEPTION);
+ /* state |= (simSTOP | simEXCEPTION); */
/* Keep a copy of the current A0 in-case this is the program exit
breakpoint: */
va_end(ap);
/* Check for our special terminating BREAK: */
if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
- rcexit = (unsigned int)(A0 & 0xFFFFFFFF);
- state &= ~simEXCEPTION;
- state |= simEXIT;
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
}
}
/* The following is so that the simulator will continue from the
exception address on breakpoint operations. */
PC = EPC;
- break;
+ switch ((CAUSE >> 2) & 0x1F)
+ {
+ case Interrupt:
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGINT);
+
+ case TLBModification:
+ case TLBLoad:
+ case TLBStore:
+ case AddressLoad:
+ case AddressStore:
+ case InstructionFetch:
+ case DataReference:
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGBUS);
+
+ case ReservedInstruction:
+ case CoProcessorUnusable:
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGILL);
+
+ case IntegerOverflow:
+ case FPE:
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGFPE);
+
+ case Trap:
+ case Watch:
+ case SystemCall:
+ case BreakPoint:
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGTRAP);
+
+ default : /* Unknown internal exception */
+ sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
+ sim_stopped, SIGQUIT);
+
+ }
case SimulatorFault:
{
char *msg;
va_start(ap,exception);
msg = va_arg(ap,char *);
- fprintf(stderr,"FATAL: Simulator error \"%s\"\n",msg);
va_end(ap);
+ sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
+ "FATAL: Simulator error \"%s\"\n",msg);
}
- exit(1);
}
return;
static void
UndefinedResult()
{
- sim_warning("UndefinedResult: IPC = 0x%08X%08X",WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("UndefinedResult: IPC = 0x%s",pr_addr(IPC));
#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
state |= simSTOP;
#endif
}
#endif /* WARN_RESULT */
-static void
+static void UNUSED
CacheOp(op,pAddr,vAddr,instruction)
int op;
uword64 pAddr;
enable bit in the Status Register is clear - a coprocessor
unusable exception is taken. */
#if 0
- callback->printf_filtered(callback,"TODO: Cache availability checking (PC = 0x%08X%08X)\n",WORD64HI(IPC),WORD64LO(IPC));
+ callback->printf_filtered(callback,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC));
#endif
switch (op & 0x3) {
int fpr;
FP_formats fmt;
{
- uword64 value;
+ uword64 value = 0;
int err = 0;
/* Treat unused register values, as fixed-point 64bit values: */
#endif /* DEBUG */
}
if (fmt != fpr_state[fpr]) {
- sim_warning("FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%08X%08X)",fpr,DOFMT(fpr_state[fpr]),DOFMT(fmt),WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)",fpr,DOFMT(fpr_state[fpr]),DOFMT(fmt),pr_addr(IPC));
fpr_state[fpr] = fmt_unknown;
}
err = -1;
break;
}
- } else if ((fpr & 1) == 0) { /* even registers only */
+ } else {
switch (fmt) {
case fmt_single:
case fmt_word:
case fmt_uninterpreted:
case fmt_double:
case fmt_long:
- value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
+ if ((fpr & 1) == 0) { /* even registers only */
+ value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
+ } else {
+ SignalException (ReservedInstruction, 0);
+ }
break;
default :
SignalException(SimulatorFault,"Unrecognised FP format in ValueFPR()");
#ifdef DEBUG
- printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr,DOFMT(fmt),WORD64HI(value),WORD64LO(value),WORD64HI(IPC),WORD64LO(IPC),SizeFGR());
+ printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR());
#endif /* DEBUG */
return(value);
int err = 0;
#ifdef DEBUG
- printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr,DOFMT(fmt),WORD64HI(value),WORD64LO(value),WORD64HI(IPC),WORD64LO(IPC),SizeFGR());
+ printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR());
#endif /* DEBUG */
if (SizeFGR() == 64) {
err = -1;
break;
}
- } else if ((fpr & 1) == 0) { /* even register number only */
+ } else {
switch (fmt) {
case fmt_single :
case fmt_word :
- FGR[fpr+1] = 0xDEADC0DE;
FGR[fpr] = (value & 0xFFFFFFFF);
- fpr_state[fpr + 1] = fmt;
fpr_state[fpr] = fmt;
break;
case fmt_uninterpreted:
case fmt_double :
case fmt_long :
- FGR[fpr+1] = (value >> 32);
- FGR[fpr] = (value & 0xFFFFFFFF);
- fpr_state[fpr + 1] = fmt;
- fpr_state[fpr] = fmt;
+ if ((fpr & 1) == 0) { /* even register number only */
+ FGR[fpr+1] = (value >> 32);
+ FGR[fpr] = (value & 0xFFFFFFFF);
+ fpr_state[fpr + 1] = fmt;
+ fpr_state[fpr] = fmt;
+ } else {
+ fpr_state[fpr] = fmt_unknown;
+ fpr_state[fpr + 1] = fmt_unknown;
+ SignalException (ReservedInstruction, 0);
+ }
break;
default :
SignalException(SimulatorFault,"Unrecognised FP format in StoreFPR()");
#ifdef DEBUG
- printf("DBG: StoreFPR: fpr[%d] = 0x%08X%08X (format %s)\n",fpr,WORD64HI(FGR[fpr]),WORD64LO(FGR[fpr]),DOFMT(fmt));
+ printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
#endif /* DEBUG */
return;
case fmt_long:
boolean = (op == FPQNaN_LONG);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
-printf("DBG: NaN: returning %d for 0x%08X%08X (format = %s)\n",boolean,WORD64HI(op),WORD64LO(op),DOFMT(fmt));
+printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
#endif /* DEBUG */
return(boolean);
int boolean = 0;
#ifdef DEBUG
- printf("DBG: Infinity: format %s 0x%08X%08X (PC = 0x%08X%08X)\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op),WORD64HI(IPC),WORD64LO(IPC));
+ printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt),pr_addr(op),pr_addr(IPC));
#endif /* DEBUG */
/* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
}
#ifdef DEBUG
- printf("DBG: Infinity: returning %d for 0x%08X%08X (format = %s)\n",boolean,WORD64HI(op),WORD64LO(op),DOFMT(fmt));
+ printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
#endif /* DEBUG */
return(boolean);
/* Argument checking already performed by the FPCOMPARE code */
#ifdef DEBUG
- printf("DBG: Less: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The format type should already have been checked: */
case fmt_double:
boolean = (*(double *)&op1 < *(double *)&op2);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
/* Argument checking already performed by the FPCOMPARE code */
#ifdef DEBUG
- printf("DBG: Equal: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The format type should already have been checked: */
case fmt_double:
boolean = (op1 == op2);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: AbsoluteValue: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The format type should already have been checked: */
double tmp = (fabs(*(double *)&op));
result = *(uword64 *)&tmp;
}
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
return(result);
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Negate: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The format type should already have been checked: */
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
return(result);
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Add: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Add: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Sub: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Sub: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Multiply: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Multiply: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Divide: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Divide: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+static uword64 UNUSED
Recip(op,fmt)
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Recip: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
result = *(uword64 *)&tmp;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Recip: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: SquareRoot: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
#endif
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: SquareRoot: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
FP_formats from;
FP_formats to;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Convert: mode %s : op 0x%08X%08X : from %s : to %s : (PC = 0x%08X%08X)\n",RMMODE(rm),WORD64HI(op),WORD64LO(op),DOFMT(from),DOFMT(to),WORD64HI(IPC),WORD64LO(IPC));
+ printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
#endif /* DEBUG */
/* The value "op" is converted to the destination format, rounding
case fmt_long:
tmp = (float)((word64)op);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#if 0
case fmt_long:
tmp = (double)((word64)op);
break;
+
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#if 0
SignalException(FPE);
} else {
if (to == fmt_word) {
- int tmp;
+ int tmp = 0;
switch (from) {
case fmt_single:
{
case fmt_double:
tmp = (int)*((double *)&op);
#ifdef DEBUG
- printf("DBG: from double %.30f (0x%08X%08X) to word: 0x%08X\n",*((double *)&op),WORD64HI(op),WORD64LO(op),tmp);
+ printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op),pr_addr(op),tmp);
#endif /* DEBUG */
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
result = (uword64)tmp;
} else { /* fmt_long */
- word64 tmp;
+ word64 tmp = 0;
switch (from) {
case fmt_single:
{
case fmt_double:
tmp = (word64)*((double *)&op);
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
result = (uword64)tmp;
}
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Convert: returning 0x%08X%08X (to format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(to));
+ printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result),DOFMT(to));
#endif /* DEBUG */
return(result);
#if defined(HASFPU)
case 1:
#ifdef DEBUG
- printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%08X%08X\n",memword,WORD64HI(memword),WORD64LO(memword));
+ printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
#endif
- StoreFPR(coproc_reg,fmt_uninterpreted,(uword64)memword);
+ StoreFPR(coproc_reg,fmt_word,(uword64)memword);
+ fpr_state[coproc_reg] = fmt_uninterpreted;
break;
#endif /* HASFPU */
default:
#if 0 /* this should be controlled by a configuration option */
- callback->printf_filtered(callback,"COP_LW(%d,%d,0x%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,WORD64HI(IPC),WORD64LO(IPC));
+ callback->printf_filtered(callback,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(IPC));
#endif
break;
}
default:
#if 0 /* this message should be controlled by a configuration option */
- callback->printf_filtered(callback,"COP_LD(%d,%d,0x%08X%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(memword),WORD64LO(memword),WORD64HI(IPC),WORD64LO(IPC));
+ callback->printf_filtered(callback,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(IPC));
#endif
break;
}
int coproc_num, coproc_reg;
{
unsigned int value = 0;
+ FP_formats hold;
+
switch (coproc_num) {
#if defined(HASFPU)
case 1:
#if 1
+ hold = fpr_state[coproc_reg];
+ fpr_state[coproc_reg] = fmt_word;
value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
+ fpr_state[coproc_reg] = hold;
#else
#if 1
value = (unsigned int)ValueFPR(coproc_reg,fpr_state[coproc_reg]);
default:
#if 0 /* should be controlled by configuration option */
- callback->printf_filtered(callback,"COP_SW(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC));
+ callback->printf_filtered(callback,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC));
#endif
break;
}
default:
#if 0 /* should be controlled by configuration option */
- callback->printf_filtered(callback,"COP_SD(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC));
+ callback->printf_filtered(callback,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC));
#endif
break;
}
*/
if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) {
int rt = ((instruction >> 16) & 0x1F);
+#if 0
int rd = ((instruction >> 11) & 0x1F);
+#endif
if (code == 0x00) { /* MF : move from */
#if 0 /* message should be controlled by configuration option */
callback->printf_filtered(callback,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
#endif
}
} else
- sim_warning("Unrecognised COP0 instruction 0x%08X at IPC = 0x%08X%08X : No handler present",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present",instruction,pr_addr(IPC));
/* TODO: When executing an ERET or RFE instruction we should
clear LLBIT, to ensure that any out-standing atomic
read/modify/write sequence fails. */
break;
case 2: /* undefined co-processor */
- sim_warning("COP2 instruction 0x%08X at IPC = 0x%08X%08X : No handler present",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("COP2 instruction 0x%08X at IPC = 0x%s : No handler present",instruction,pr_addr(IPC));
break;
case 1: /* should not occur (FPU co-processor) */
/*-- instruction simulation -------------------------------------------------*/
-static void
-simulate ()
+void
+sim_engine_run (sd, next_cpu_nr, siggnal)
+ SIM_DESC sd;
+ int next_cpu_nr; /* ignore */
+ int siggnal; /* ignore */
{
+#if !defined(FASTSIM)
unsigned int pipeline_count = 1;
+#endif
#ifdef DEBUG
- if (membank == NULL) {
+ if (STATE_MEMORY (sd) == NULL) {
printf("DBG: simulate() entered with no memory\n");
exit(1);
}
#endif
/* main controlling loop */
- do {
+ while (1) {
/* Fetch the next instruction from the simulator memory: */
uword64 vaddr = (uword64)PC;
uword64 paddr;
int cca;
- unsigned int instruction;
+ unsigned int instruction; /* uword64? what's this used for? FIXME! */
int dsstate = (state & simDELAYSLOT);
#ifdef DEBUG
if (state & simHALTEX) printf(" simHALTEX");
if (state & simHALTIN) printf(" simHALTIN");
if (state & simBE) printf(" simBE");
+ printf("\n");
}
#endif /* DEBUG */
#ifdef DEBUG
if (dsstate)
- callback->printf_filtered(callback,"DBG: DSPC = 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
+ callback->printf_filtered(callback,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
#endif /* DEBUG */
- if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { /* Copy the action of the LW instruction */
- unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
- unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
- uword64 value;
- unsigned int byte;
- paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
- value = LoadMemory(cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
- byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
+ if ((vaddr & 1) == 0) {
+ /* Copy the action of the LW instruction */
+ unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
+ unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
+ uword64 value;
+ unsigned int byte;
+ paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
+ LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
+ byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
+ instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ } else {
+ /* Copy the action of the LH instruction */
+ unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
+ unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
+ uword64 value;
+ unsigned int byte;
+ paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
+ | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
+ LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
+ paddr & ~ (uword64) 1,
+ vaddr, isINSTRUCTION, isREAL);
+ byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
+ instruction = ((value >> (8 * byte)) & 0xFFFF);
+ }
} else {
- fprintf(stderr,"Cannot translate address for PC = 0x%08X%08X failed\n",WORD64HI(PC),WORD64LO(PC));
+ fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
exit(1);
}
#ifdef DEBUG
- callback->printf_filtered(callback,"DBG: fetched 0x%08X from PC = 0x%08X%08X\n",instruction,WORD64HI(PC),WORD64LO(PC));
+ callback->printf_filtered(callback,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
#endif /* DEBUG */
#if !defined(FASTSIM) || defined(PROFILE)
/* This is required by exception processing, to ensure that we can
cope with exceptions in the delay slots of branches that may
already have changed the PC. */
- PC += 4; /* increment ready for the next fetch */
+ if ((vaddr & 1) == 0)
+ PC += 4; /* increment ready for the next fetch */
+ else
+ PC += 2;
/* NOTE: If we perform a delay slot change to the PC, this
increment is not requuired. However, it would make the
simulator more complicated to try and avoid this small hit. */
treated as using a single cycle. NOTE: A standard system is not
provided by the default simulator because different MIPS
architectures have different cycle counts for the same
- instructions. */
+ instructions.
+
+ [NOTE: pipeline_count has been replaced the event queue] */
#if defined(HASFPU)
/* Set previous flag, depending on current: */
HIACCESS--;
if (LOACCESS > 0)
LOACCESS--;
+ if (HI1ACCESS > 0)
+ HI1ACCESS--;
+ if (LO1ACCESS > 0)
+ LO1ACCESS--;
#endif /* WARN_LOHI */
#if defined(WARN_ZERO)
than within the simulator, since it will help keep the simulator
small. */
if (ZERO != 0) {
- sim_warning("The ZERO register has been updated with 0x%08X%08X (PC = 0x%08X%08X) (reset back to zero)",WORD64HI(ZERO),WORD64LO(ZERO),WORD64HI(IPC),WORD64LO(IPC));
+ sim_warning("The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)",pr_addr(ZERO),pr_addr(IPC));
ZERO = 0; /* reset back to zero before next instruction */
}
#endif /* WARN_ZERO */
executed, then update the PC to its new value: */
if (dsstate) {
#ifdef DEBUG
- printf("DBG: dsstate set before instruction execution - updating PC to 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
+ printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
#endif /* DEBUG */
PC = DSPC;
- state &= ~simDELAYSLOT;
+ state &= ~(simDELAYSLOT | simJALDELAYSLOT);
}
if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
if (--(pending_slot_count[index]) == 0) {
#ifdef DEBUG
printf("pending_slot_reg[%d] = %d\n",index,pending_slot_reg[index]);
- printf("pending_slot_value[%d] = 0x%08X%08X\n",index,WORD64HI(pending_slot_value[index]),WORD64LO(pending_slot_value[index]));
+ printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(pending_slot_value[index]));
#endif /* DEBUG */
if (pending_slot_reg[index] == COCIDX) {
SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
registers, is when performing binary transfers. This
means we should update the register type field. */
if ((pending_slot_reg[index] >= FGRIDX) && (pending_slot_reg[index] < (FGRIDX + 32)))
- fpr_state[pending_slot_reg[index]] = fmt_uninterpreted;
+ fpr_state[pending_slot_reg[index] - FGRIDX] = fmt_uninterpreted;
#endif /* HASFPU */
}
#ifdef DEBUG
- printf("registers[%d] = 0x%08X%08X\n",pending_slot_reg[index],WORD64HI(registers[pending_slot_reg[index]]),WORD64LO(registers[pending_slot_reg[index]]));
+ printf("registers[%d] = 0x%s\n",pending_slot_reg[index],pr_addr(registers[pending_slot_reg[index]]));
#endif /* DEBUG */
pending_slot_reg[index] = (LAST_EMBED_REGNUM + 1);
pending_out++;
}
#if !defined(FASTSIM)
- pipeline_ticks += pipeline_count;
+ if (sim_events_tickn (sd, pipeline_count))
+ {
+ /* cpu->cia = cia; */
+ sim_events_process (sd);
+ }
+#else
+ if (sim_events_tick (sd))
+ {
+ /* cpu->cia = cia; */
+ sim_events_process (sd);
+ }
#endif /* FASTSIM */
+ }
+}
- if (state & simSTEP)
- state |= simSTOP;
- } while (!(state & simSTOP));
+/* This code copied from gdb's utils.c. Would like to share this code,
+ but don't know of a common place where both could get to it. */
-#ifdef DEBUG
- if (membank == NULL) {
- printf("DBG: simulate() LEAVING with no memory\n");
- exit(1);
- }
-#endif /* DEBUG */
+/* Temporary storage using circular buffer */
+#define NUMCELLS 16
+#define CELLSIZE 32
+static char*
+get_cell()
+{
+ static char buf[NUMCELLS][CELLSIZE];
+ static int cell=0;
+ if (++cell>=NUMCELLS) cell=0;
+ return buf[cell];
+}
- return;
+/* Print routines to handle variable size regs, etc */
+
+/* Eliminate warning from compiler on 32-bit systems */
+static int thirty_two = 32;
+
+char*
+pr_addr(addr)
+ SIM_ADDR addr;
+{
+ char *paddr_str=get_cell();
+ switch (sizeof(addr))
+ {
+ case 8:
+ sprintf(paddr_str,"%08lx%08lx",
+ (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
+ break;
+ case 4:
+ sprintf(paddr_str,"%08lx",(unsigned long)addr);
+ break;
+ case 2:
+ sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
+ break;
+ default:
+ sprintf(paddr_str,"%x",addr);
+ }
+ return paddr_str;
}
+char*
+pr_uword64(addr)
+ uword64 addr;
+{
+ char *paddr_str=get_cell();
+ sprintf(paddr_str,"%08lx%08lx",
+ (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
+ return paddr_str;
+}
+
+
/*---------------------------------------------------------------------------*/
/*> EOF interp.c <*/
projects / deliverable / binutils-gdb.git / blobdiff