Debug tx19 built from igen sources.

[deliverable/binutils-gdb.git] / sim / mips / interp.c

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 7368695a40c2fd7e529ae69f188d73330f7dedd5..f1210b7637b5d3ff7c478279ee5a134be6030e85 100644 (file)
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1551,29 +1551,6 @@ ColdReset (SIM_DESC sd)
     }
 }
 
-unsigned16
-ifetch16 (SIM_DESC sd,
-         sim_cpu *cpu,
-         address_word cia,
-         address_word vaddr)
-{
-  /* Copy the action of the LW instruction */
-  address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
-  address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
-  unsigned64 value;
-  address_word paddr;
-  unsigned16 instruction;
-  unsigned byte;
-  int cca;
-  AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
-  paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
-  LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
-  byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
-  instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
-  return instruction;
-}
-
-
 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
 /* Signal an exception condition. This will result in an exception
    that aborts the instruction. The instruction operation pseudocode
@@ -1677,7 +1654,7 @@ signal_exception (SIM_DESC sd,
           sim_engine_restart (sd, NULL, NULL, NULL_CIA);
         }
        /* else fall through to normal exception processing */
-       sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
+       sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
      }
 
     case BreakPoint:
@@ -3375,7 +3352,9 @@ decode_coproc (SIM_DESC sd,
              vu0_issue(sd);
 
            /* write to reserved CIA register to get VU0 moving */
-           write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
+           write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
+
+           ASSERT(vu0_busy());
          }
        else if(i_5_0 == 0x39) /* VCALLMSR */
          {
@@ -3384,9 +3363,11 @@ decode_coproc (SIM_DESC sd,
            while(vu0_busy())
              vu0_issue(sd);
 
-           read_vu_misc_reg(&(vu0_device.regs), VU_REG_CMSAR0, & data);
+           read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
            /* write to reserved CIA register to get VU0 moving */
-           write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
+           write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
+
+           ASSERT(vu0_busy());
          }
        /* handle all remaining UPPER VU instructions in one block */
        else if((i_5_0 <  0x30) || /* VADDx .. VMINI */
@@ -3394,7 +3375,7 @@ decode_coproc (SIM_DESC sd,
          {
            unsigned_4 vu_upper, vu_lower;
            vu_upper =
-             0x40000000 | /* bits 31 .. 25 */
+             0x00000000 | /* bits 31 .. 25 */
              (instruction & 0x01ffffff); /* bits 24 .. 0 */
            vu_lower = 0x8000033c; /* NOP */
 
@@ -3413,9 +3394,9 @@ decode_coproc (SIM_DESC sd,
                (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
          {                            /* N.B.: VWAITQ already covered by prior case */
            unsigned_4 vu_upper, vu_lower;
-           vu_upper = 0x400002ff; /* END/NOP */
+           vu_upper = 0x000002ff; /* NOP/NOP */
            vu_lower =
-             0x10000000 | /* bits 31 .. 25 */
+             0x80000000 | /* bits 31 .. 25 */
              (instruction & 0x01ffffff); /* bits 24 .. 0 */
 
            /* POLICY: never busy in macro mode */