+// -*- C -*-
+//
//
// MIPS Architecture:
//
// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
-// FIXME: Instead of having the code for mips16 instructions here.
-// these instructions should instead call the corresponding 32bit
-// instruction (or a function implementing that instructions code).
+// The MIPS16 codes registers in a special way, map from one to the other.
+// :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
+:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
+:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
+:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
+:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
+
+:compute:::int:SHAMT:SHAMT_4_0,S5:(LSINSERTED (S5, 5, 5) | SHAMT_4_0)
+
+:compute:::address_word:IMMEDIATE:IMM_25_21,IMM_20_16,IMMED_15_0:(LSINSERTED (IMM_25_21, 25, 21) | LSINSERTED (IMM_20_16, 20, 16) | LSINSERTED (IMMED_15_0, 15, 0))
+:compute:::int:R32:R32L,R32H:((R32H << 3) | R32L)
+
+:compute:::address_word:IMMEDIATE:IMM_10_5,IMM_15_11,IMM_4_0:(LSINSERTED (IMM_10_5, 10, 5) | LSINSERTED (IMM_15_11, 15, 11) | LSINSERTED (IMM_4_0, 4, 0))
+
+:compute:::address_word:IMMEDIATE:IMM_10_4,IMM_14_11,IMM_3_0:(LSINSERTED (IMM_10_4, 10, 4) | LSINSERTED (IMM_14_11, 14, 11) | LSINSERTED (IMM_3_0, 3, 0))
// Load and Store Instructions
-10000,xxx,ddd,55555:RRI:16::LB
+10000,3.RX,3.RY,5.IMMED:RRI:16::LB
+"lb r<TRY>, <IMMED> (r<TRX>)"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
- }
- }
- }
+ GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 10000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LB
+"lb r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
}
-10100,xxx,ddd,55555:RRI:16::LBU
+
+10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
+"lbu r<TRY>, <IMMED> (r<TRX>)"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
- }
- }
- }
+ GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 10100,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LBU
+"lbu r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
}
-10001,xxx,ddd,HHHHH:RRI:16::LH
+
+10001,3.RX,3.RY,5.IMMED:RRI:16::LH
+"lh r<TRY>, <IMMED> (r<TRX>)"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 1;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
- }
- }
- }
-}
-
-
-10101,xxx,ddd,HHHHH:RRI:16::LHU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 1;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
- }
- }
- }
-}
-
-
-10011,xxx,ddd,WWWWW:RRI:16::LW
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
- }
- }
- }
-}
-
-
-10110,ddd,VVVVVVVV,P:RI:16::LWPC
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
- }
- }
- }
-}
-
-
-10010,ddd,VVVVVVVV,s:RI:16::LWSP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
- }
- }
- }
-}
-
-
-10111,xxx,ddd,WWWWW:RRI:16::LWU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
-}
-
-
-00111,xxx,ddd,DDDDD:RRI:16::LD
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 4;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
- }
- }
- }
-}
-
-
-11111100,ddd,5.RD,P:RI64:16::LDPC
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 4;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
- }
- }
- }
-}
-
-
-11111000,ddd,5.RD,s:RI64:16::LDSP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- signed_word op1 = 29;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 4;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
- }
- }
- }
-}
-
-
-11000,xxx,yyy,55555:RRI:16::SB
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 10001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LH
+"lh r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
}
-11001,xxx,yyy,HHHHH:RRI:16::SH
+
+10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
+"lhu r<TRY>, <IMMED> (r<TRX>)"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 1;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-11011,xxx,yyy,WWWWW:RRI:16::SW
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-11010,yyy,VVVVVVVV,s:RI:16::SWSP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op2 = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-01100010,VVVVVVVV,Q,s:I8:16::SWRASP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0xff;
- signed_word op2 = 31;
- signed_word op1 = 29;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 2;
- }
- op2 = GPR[op2];
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-01111,xxx,yyy,DDDDD:RRI:16::SD
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = op2;
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-11111001,yyy,5.RD,s:RI64:16::SDSP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op2 = (instruction >> 5) & 0x7;
- int offset = (instruction >> 0) & 0x1f;
- signed_word op1 = 29;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = op2;
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-11111010,CCCCCCCC,s,Q:I64:16::SDRASP
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- signed_word op2 = 31;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- offset <<= 3;
- }
- op1 = GPR[op1];
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = op2;
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 10101,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LHU
+"lhu r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
+}
+
+
+
+10011,3.RX,3.RY,5.IMMED:RRI:16::LW
+"lw r<TRY>, <IMMED> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 10011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LW
+"lw r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
+}
+
+
+
+10110,3.RX,8.IMMED:RI:16::LWPC
+"lw r<TRX>, <IMMED> (PC)"
+*mips16:
+*vr4100:
+{
+ GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
+ basepc (SD_) & ~3, IMMED << 2));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 10110,3.RX,000,5.IMM_4_0:EXT-RI:16::LWPC
+"lw r<TRX>, <IMMEDIATE> (PC)"
+*mips16:
+*vr4100:
+{
+ GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, basepc (SD_) & ~3, EXTEND16 (IMMEDIATE)));
+}
+
+
+
+10010,3.RX,8.IMMED:RI:16::LWSP
+"lw r<TRX>, <IMMED> (SP)"
+*mips16:
+*vr4100:
+{
+ GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 10010,3.RX,000,5.IMM_4_0:EXT-RI:16::LWSP
+"lw r<TRX>, <IMMEDIATE> (SP)"
+*mips16:
+*vr4100:
+{
+ GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE)));
+}
+
+
+
+10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
+"lwu r<TRY>, <IMMED> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 10111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LWU
+"lwu r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE));
+}
+
+
+
+00111,3.RX,3.RY,5.IMMED:RRI:16::LD
+"ld r<TRY>, <IMMED> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 00111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LD
+"ld r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
+}
+
+
+
+11111,100,3.RY,5.IMMED:RI64:16::LDPC
+"ld r<TRY>, <IMMED> (PC)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
+ basepc (SD_) & ~7, IMMED << 3);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11111,100,3.RY,5.IMM_4_0:EXT-RI64:16::LDPC
+"ld r<TRY>, <IMMEDIATE> (PC)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, basepc (SD_) & ~7, EXTEND16 (IMMEDIATE));
+}
+
+
+
+11111,000,3.RY,5.IMMED:RI64:16::LDSP
+"ld r<TRY>, <IMMED> (SP)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11111,000,3.RY,5.IMM_4_0:EXT-RI64:16::LDSP
+"ld r<TRY>, <IMMEDIATE> (SP)"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE));
+}
+
+
+
+11000,3.RX,3.RY,5.IMMED:RRI:16::SB
+"sb r<TRY>, <IMMED> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SB
+"sb r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
+}
+
+
+
+11001,3.RX,3.RY,5.IMMED:RRI:16::SH
+"sh r<TRY>, <IMMED> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SH
+"sh r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
+}
+
+
+
+11011,3.RX,3.RY,5.IMMED:RRI:16::SW
+"sw r<TRY>, <IMMED> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SW
+"sw r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
+}
+
+
+
+11010,3.RX,8.IMMED:RI:16::SWSP
+"sw r<TRX>, <IMMED> (SP)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11010,3.RX,000,5.IMM_4_0:EXT-RI:16::SWSP
+"sw r<TRX>, <IMMEDIATE> (SP)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), GPR[TRX]);
+}
+
+
+
+01100,010,8.IMMED:I8:16::SWRASP
+"sw r<RAIDX>, <IMMED> (SP)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 01100,010,000,5.IMM_4_0:EXT-I8:16::SWRASP
+"sw r<RAIDX>, <IMMEDIATE> (SP)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), RA);
+}
+
+
+
+01111,3.RX,3.RY,5.IMMED:RRI:16::SD
+"sd r<TRY>, <IMMED> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 01111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SD
+"sd r<TRY>, <IMMEDIATE> (r<TRX>)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
+}
+
+
+
+11111,001,3.RY,5.IMMED:RI64:16::SDSP
+"sd r<TRY>, <IMMED> (SP)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11111,001,3.RY,5.IMM_4_0:EXT-RI64:16::SDSP
+"sd r<TRY>, <IMMEDIATE> (SP)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), GPR[TRY]);
+}
+
+
+
+11111,010,8.IMMED:I64:16::SDRASP
+"sd r<RAIDX>, <IMMED> (SP)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11111,010,000,5.IMM_4_0:EXT-I64:16::SDRASP
+"sd r<RAIDX>, <IMMEDIATE> (SP)"
+*mips16:
+*vr4100:
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), RA);
+}
+
+
+
+// ALU Immediate Instructions
+
+
+01101,3.RX,8.IMMED:RI:16::LI
+"li r<TRX>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_ori (SD_, 0, TRX, IMMED);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 01101,3.RX,000,5.IMM_4_0:EXT-RI:16::LI
+"li r<TRX>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_ori (SD_, 0, TRX, IMMEDIATE);
+}
+
+
+
+01000,3.RX,3.RY,0,4.IMMED:RRI-A:16::ADDIU
+"addiu r<TRY>, r<TRX>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
+}
+
+11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,0,4.IMM_3_0:EXT-RRI-A:16::ADDIU
+"addiu r<TRY>, r<TRX>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_addiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
+}
+
+
+
+01001,3.RX,8.IMMED:RI:16::ADDIU8
+"addiu r<TRX>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 01001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIU8
+"addiu r<TRX>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_addiu (SD_, TRX, TRX, EXTEND16 (IMMEDIATE));
+}
+
+
+
+01100,011,8.IMMED:I8:16::ADJSP
+"addiu SP, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 01100,011,000,5.IMM_4_0:EXT-I8:16::ADJSP
+"addiu SP, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_addiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
+}
+
+
+
+00001,3.RX,8.IMMED:RI:16::ADDIUPC
+"addiu r<TRX>, PC, <IMMED>"
+*mips16:
+*vr4100:
+{
+ unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2);
+ GPR[TRX] = EXTEND32 (temp);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 00001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUPC
+"addiu r<TRX>, PC, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
+ GPR[TRX] = EXTEND32 (temp);
+}
+
+
+
+00000,3.RX,8.IMMED:RI:16::ADDIUSP
+"addiu r<TRX>, SP, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_addiu (SD_, SPIDX, TRX, IMMED << 2);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 00000,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUSP
+"addiu r<TRX>, SP, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_addiu (SD_, SPIDX, TRX, EXTEND16 (IMMEDIATE));
+}
+
+
+
+01000,3.RX,3.RY,1,4.IMMED:RRI-A:16::DADDIU
+"daddiu r<TRY>, r<TRX>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
+}
+
+11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,1,4.IMM_3_0:EXT-RRI-A:16::DADDIU
+"daddiu r<TRY>, r<TRX>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_daddiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
+}
+
+
+
+11111,101,3.RY,5.IMMED:RI64:16::DADDIU5
+"daddiu r<TRY>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11111,101,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIU5
+"daddiu r<TRY>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_daddiu (SD_, TRY, TRY, EXTEND16 (IMMEDIATE));
+}
+
+
+
+11111,011,8.IMMED:I64:16::DADJSP
+"daddiu SP, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11111,011,000,5.IMM_4_0:EXT-I64:16::DADJSP
+"daddiu SP, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_daddiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
+}
+
+
+
+11111,110,3.RY,5.IMMED:RI64:16::DADDIUPC
+"daddiu r<TRY>, PC, <IMMED>"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = (basepc (SD_) & ~3) + (IMMED << 2);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11111,110,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUPC
+"daddiu r<TRY>, PC, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ GPR[TRY] = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
+}
+
+
+
+11111,111,3.RY,5.IMMED:RI64:16::DADDIUSP
+"daddiu r<TRY>, SP, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_daddiu (SD_, SPIDX, TRY, IMMED << 2);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 11111,111,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUSP
+"daddiu r<TRY>, SP, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_daddiu (SD_, SPIDX, TRY, EXTEND16 (IMMEDIATE));
+}
+
+
+
+01010,3.RX,8.IMMED:RI:16::SLTI
+"slti r<TRX>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_slti (SD_, TRX, T8IDX, IMMED);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 01010,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTI
+"slti r<TRX>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_slti (SD_, TRX, T8IDX, IMMEDIATE);
+}
+
+
+
+01011,3.RX,8.IMMED:RI:16::SLTIU
+"sltiu r<TRX>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_sltiu (SD_, TRX, T8IDX, IMMED);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 01011,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTIU
+"sltiu r<TRX>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_sltiu (SD_, TRX, T8IDX, IMMEDIATE);
+}
+
+
+
+11101,3.RX,3.RY,01010:RR:16::CMP
+"cmp r<TRX>, r<TRY>"
+*mips16:
+*vr4100:
+{
+ do_xor (SD_, TRX, TRY, T8IDX);
+}
+
+
+01110,3.RX,8.IMMED:RI:16::CMPI
+"cmpi r<TRX>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ do_xori (SD_, TRX, T8IDX, IMMED);
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 01110,3.RX,000,5.IMM_4_0:EXT-RI:16::CMPI
+"sltiu r<TRX>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ do_xori (SD_, TRX, T8IDX, IMMEDIATE);
+}
+
+
+
+// Two/Three Operand, Register-Type
+
+
+
+11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
+"addu r<TRZ>, r<TRX>, r<TRY>"
+*mips16:
+*vr4100:
+{
+ do_addu (SD_, TRX, TRY, TRZ);
+}
+
+
+
+11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
+"subu r<TRZ>, r<TRX>, r<TRY>"
+*mips16:
+*vr4100:
+{
+ do_subu (SD_, TRX, TRY, TRZ);
+}
+
+11100,3.RX,3.RY,3.RZ,00:RRR:16::DADDU
+"daddu r<TRZ>, r<TRX>, r<TRY>"
+*mips16:
+*vr4100:
+{
+ do_daddu (SD_, TRX, TRY, TRZ);
+}
+
+
+
+11100,3.RX,3.RY,3.RZ,10:RRR:16::DSUBU
+"dsubu r<TRZ>, r<TRX>, r<TRY>"
+*mips16:
+*vr4100:
+{
+ do_dsubu (SD_, TRX, TRY, TRZ);
}
-// ALU Immediate Instructions
-
-01101,ddd,UUUUUUUU,Z:RI:16::LI
+11101,3.RX,3.RY,00010:RR:16::SLT
+"slt r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = 0;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = (op1 | op2);
- }
+ do_slt (SD_, TRX, TRY, T8IDX);
}
-01000,xxx,ddd,04444:RRI_A:16::ADDIU
+
+11101,3.RX,3.RY,00011:RR:16::SLTU
+"sltu r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int op2 = (instruction >> 0) & 0xf;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
- if (op2 >= 0x4000)
- op2 -= 0x8000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x8)
- op2 -= 0x10;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
+ do_sltu (SD_, TRX, TRY, T8IDX);
}
-01001,www,kkkkkkkk:RI:16::ADDIU8
+
+11101,3.RX,3.RY,01011:RR:16::NEG
+"neg r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg;
- int op2 = (instruction >> 0) & 0xff;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x80)
- op2 -= 0x100;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
+ do_subu (SD_, 0, TRY, TRX);
}
-01100011,KKKKKKKK,S:I8:16::ADJSP
+
+11101,3.RX,3.RY,01100:RR:16::AND
+"and r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- int destreg;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x80)
- op2 -= 0x100;
- op2 <<= 3;
- }
- destreg = op1;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
+ do_and (SD_, TRX, TRY, TRX);
}
-00001,ddd,AAAAAAAA,P:RI:16::ADDIUPC
+
+11101,3.RX,3.RY,01101:RR:16::OR
+"or r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- op2 <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
+ do_or (SD_, TRX, TRY, TRX);
}
-00000,ddd,AAAAAAAA,s:RI:16::ADDIUSP
+
+11101,3.RX,3.RY,01110:RR:16::XOR
+"xor r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- op2 <<= 2;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
-}
-
-
-01000,xxx,ddd,14444:RRI_A:16::DADDIU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = (instruction >> 5) & 0x7;
- int op2 = (instruction >> 0) & 0xf;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
- if (op2 >= 0x4000)
- op2 -= 0x8000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x8)
- op2 -= 0x10;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ do_xor (SD_, TRX, TRY, TRX);
}
-11111101,www,jjjjj:RI64:16::DADDIU5
+
+11101,3.RX,3.RY,01111:RR:16::NOT
+"not r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 5) & 0x7;
- int destreg;
- int op2 = (instruction >> 0) & 0x1f;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x10)
- op2 -= 0x20;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ do_nor (SD_, 0, TRY, TRX);
}
-11111011,KKKKKKKK,S:I64:16::DADJSP
+
+01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
+"move r<TRY>, r<R32>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int op2 = (instruction >> 0) & 0xff;
- signed_word op1 = 29;
- int destreg;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (op2 >= 0x80)
- op2 -= 0x100;
- op2 <<= 3;
- }
- destreg = op1;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ do_or (SD_, R32, 0, TRY);
}
-11111110,ddd,EEEEE,P:RI64:16::DADDIUPC
+
+01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
+"move r<R32>, r<TRZ>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- int op2 = (instruction >> 0) & 0x1f;
- signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- op2 <<= 2;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ do_or (SD_, TRZ, 0, R32);
}
-11111111,ddd,EEEEE,s:RI64:16::DADDIUSP
+
+00110,3.RX,3.RY,3.SHAMT,00:SHIFT:16::SLL
+"sll r<TRX>, r<TRY>, <SHIFT>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- int op2 = (instruction >> 0) & 0x1f;
- signed_word op1 = 29;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- op2 <<= 2;
- }
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
+ do_sll (SD_, TRY, TRX, SHIFT);
}
-
-01010,xxx,88888888,T:RI:16::SLTI
+11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,00:EXT-SHIFT:16::SLL
+"sll r<TRX>, r<TRY>, <SHIFT>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if ((word64)op1 < (word64)op2)
- GPR[destreg] = 1;
- else
- GPR[destreg] = 0;
- }
+ do_sll (SD_, TRY, TRX, SHAMT);
}
-01011,xxx,88888888,T:RI:16::SLTIU
+
+00110,3.RX,3.RY,3.SHAMT,10:SHIFT:16::SRL
+"srl r<TRX>, r<TRY>, <SHIFT>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (op2 >= 0x8000)
- op2 -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if ((unsigned64)op1 < (unsigned64)op2)
- GPR[destreg] = 1;
- else
- GPR[destreg] = 0;
- }
+ do_srl (SD_, TRY, TRX, SHIFT);
}
-
-11101,xxx,yyy,01010,T:RR:16::CMP
+11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,10:EXT-SHIFT:16::SRL
+"srl r<TRX>, r<TRY>, <SHIFT>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (op1 ^ op2);
- }
+ do_srl (SD_, TRY, TRX, SHAMT);
}
-01110,xxx,UUUUUUUU,T:RI:16::CMPI
+
+00110,3.RX,3.RY,3.SHAMT,11:SHIFT:16::SRA
+"sra r<TRX>, r<TRY>, <SHIFT>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int op2 = (instruction >> 0) & 0xff;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- {
- op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- have_extendval = 0;
- }
- else
- {
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (op1 ^ op2);
- }
+ do_sra (SD_, TRY, TRX, SHIFT);
}
+11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,11:EXT-SHIFT:16::SRA
+"sra r<TRX>, r<TRY>, <SHIFT>"
+*mips16:
+*vr4100:
+{
+ do_sra (SD_, TRY, TRX, SHAMT);
+}
-// Two/Three Operand, Register-Type
-11100,xxx,yyy,ddd,01:RRR:16::ADDU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = (instruction >> 2) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 + op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
-}
-
-
-11100,xxx,yyy,ddd,11:RRR:16::SUBU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = (instruction >> 2) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 - op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
-}
-
-
-11100,xxx,yyy,ddd,00:RRR:16::DADDU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = (instruction >> 2) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 + op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
-}
-
-
-11100,xxx,yyy,ddd,10:RRR:16::DSUBU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = (instruction >> 2) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 temp = (unsigned64)(op1 - op2);
- word64 tempS = (word64)temp;
- GPR[destreg] = (unsigned64)temp;
- }
-}
-
-
-11101,xxx,yyy,00010,T:RR:16::SLT
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if ((word64)op1 < (word64)op2)
- GPR[destreg] = 1;
- else
- GPR[destreg] = 0;
- }
-}
-
-
-11101,xxx,yyy,00011,T:RR:16::SLTU
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg = 24;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if ((unsigned64)op1 < (unsigned64)op2)
- GPR[destreg] = 1;
- else
- GPR[destreg] = 0;
- }
-}
-
-
-11101,ddd,yyy,01011,Z:RR:16::NEG
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- signed_word op1 = 0;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int temp = (unsigned int)(op1 - op2);
- signed int tempS = (signed int)temp;
- GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
- }
-}
-
-
-11101,www,yyy,01100:RR:16::AND
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (op1 & op2);
- }
-}
-
-
-11101,www,yyy,01101:RR:16::OR
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = (op1 | op2);
- }
-}
-
-
-11101,www,yyy,01110:RR:16::XOR
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- destreg = op1;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (op1 ^ op2);
- }
-}
-
-
-11101,ddd,yyy,01111,Z:RR:16::NOT
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- signed_word op1 = 0;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = ~(op1 | op2);
- }
-}
-
-
-01100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 5) & 0x7;
- signed_word op1 = (instruction >> 0) & 0x1f;
- signed_word op2 = 0;
- if (destreg < 2)
- destreg += 16;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = (op1 | op2);
- }
-}
-
-
-01100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 3) & 0x1f;
- signed_word op1 = (instruction >> 0) & 0x7;
- signed_word op2 = 0;
- destreg = (destreg >> 2) | ((destreg & 3) << 3);
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- if (destreg != 0)
- GPR[destreg] = (op1 | op2);
- }
-}
-
-
-00110,ddd,yyy,sss,00:ISHIFT:16::SLL
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int op1 = (instruction >> 2) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- op1 = (extendval >> 6) & 0x1f;
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = ((unsigned64)op2 << op1);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
+11101,3.RX,3.RY,00100:RR:16::SLLV
+"sllv r<TRY>, r<TRX>"
+*mips16:
+*vr4100:
+{
+ do_sllv (SD_, TRX, TRY, TRY);
}
-00110,ddd,yyy,sss,10:ISHIFT:16::SRL
+11101,3.RX,3.RY,00110:RR:16::SRLV
+"srlv r<TRY>, r<TRX>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int op1 = (instruction >> 2) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- op1 = (extendval >> 6) & 0x1f;
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
+ do_srlv (SD_, TRX, TRY, TRY);
}
-00110,ddd,yyy,sss,11:ISHIFT:16::SRA
+11101,3.RX,3.RY,00111:RR:16::SRAV
+"srav r<TRY>, r<TRX>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int op1 = (instruction >> 2) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- op1 = (extendval >> 6) & 0x1f;
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int highbit = (unsigned int)1 << 31;
- GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
- GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
-}
-
-
-11101,xxx,vvv,00100:RR:16::SLLV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- op1 &= 0x1F;
- GPR[destreg] = ((unsigned64)op2 << op1);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
-}
-
-
-11101,xxx,vvv,00110:RR:16::SRLV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- op1 &= 0x1F;
- GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
-}
-
-
-11101,xxx,vvv,00111:RR:16::SRAV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned int highbit = (unsigned int)1 << 31;
- op1 &= 0x1F;
- GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
- GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
-}
-
-
-00110,ddd,yyy,[[[,01:ISHIFT:16::DSLL
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int op1 = (instruction >> 2) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- {
- op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = ((unsigned64)op2 << op1);
- }
+ do_srav (SD_, TRX, TRY, TRY);
}
+
+
+00110,3.RX,3.RY,3.SHAMT,01:SHIFT:16::DSLL
+"dsll r<TRY>, r<TRX>, <SHIFT>"
+*mips16:
+*vr4100:
+{
+ do_dsll (SD_, TRY, TRX, SHIFT);
+}
+
+11110,5.SHAMT_4_0,1.S5,00000 + 00110,3.RX,3.RY,000,01:EXT-SHIFT:16::DSLL
+"dsll r<TRY>, r<TRX>, <SHAMT>"
+*mips16:
+*vr4100:
+{
+ do_dsll (SD_, TRY, TRX, SHAMT);
+}
+
-11101,XXX,vvv,01000:RR:16::DSRL
+11101,3.SHAMT,3.RY,01000:SHIFT64:16::DSRL
+"dsrl r<TRY>, <SHIFT>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (have_extendval)
- {
- op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = ((unsigned64)(op2) >> op1);
- }
+ do_dsrl (SD_, TRY, TRY, SHIFT);
+}
+
+11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,01000:EXT-SHIFT64:16::DSRL
+"dsrl r<TRY>, <SHAMT>"
+*mips16:
+*vr4100:
+{
+ do_dsrl (SD_, TRY, TRY, SHAMT);
}
-11101,xxx,vvv,10011:RR:16::DSRA
+
+11101,3.SHAMT,3.RY,10011:SHIFT64:16::DSRA
+"dsra r<TRY>, <SHIFT>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (have_extendval)
- {
- op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
- have_extendval = 0;
- }
- else
- {
- if (op1 == 0)
- op1 = 8;
- }
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 highbit = (unsigned64)1 << 63;
- GPR[destreg] = ((unsigned64)(op2) >> op1);
- GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
- }
-}
-
-
-11101,xxx,vvv,10100:RR:16::DSLLV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- op1 &= 0x3F;
- GPR[destreg] = ((unsigned64)op2 << op1);
- }
-}
-
-
-11101,xxx,vvv,10110:RR:16::DSRLV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- op1 &= 0x3F;
- GPR[destreg] = ((unsigned64)(op2) >> op1);
- }
-}
-
-
-11101,xxx,vvv,10111:RR:16::DSRAV
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- int destreg;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- destreg = op2;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- unsigned64 highbit = (unsigned64)1 << 63;
- op1 &= 0x3F;
- GPR[destreg] = ((unsigned64)(op2) >> op1);
- GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
- }
+ do_dsra (SD_, TRY, TRY, SHIFT);
+}
+
+11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,10011:EXT-SHIFT64:16::DSRA
+"dsra r<TRY>, <SHAMT>"
+*mips16:
+*vr4100:
+{
+ do_dsra (SD_, TRY, TRY, SHAMT);
+}
+
+
+
+11101,3.RX,3.RY,10100:RR:16::DSLLV
+"dsllv r<TRY>, r<TRX>"
+*mips16:
+*vr4100:
+{
+ do_dsllv (SD_, TRX, TRY, TRY);
+}
+
+
+11101,3.RX,3.RY,10110:RR:16::DSRLV
+"dsrlv r<TRY>, r<TRX>"
+*mips16:
+*vr4100:
+{
+ do_dsrlv (SD_, TRX, TRY, TRY);
+}
+
+
+11101,3.RX,3.RY,10111:RR:16::DSRAV
+"dsrav r<TRY>, r<TRX>"
+*mips16:
+*vr4100:
+{
+ do_dsrav (SD_, TRX, TRY, TRY);
}
// Multiply /Divide Instructions
-11101,xxx,yyy,11000:RR:16::MULT
+11101,3.RX,3.RY,11000:RR:16::MULT
+"mult r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Multiplication");
- {
- unsigned64 temp = ((word64) op1 * (word64) op2);
- LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
- HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
- }
- }
+ do_mult (SD_, TRX, TRY, 0);
}
-11101,xxx,yyy,11001:RR:16::MULTU
+11101,3.RX,3.RY,11001:RR:16::MULTU
+"multu r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Multiplication");
- {
- unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
- LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
- HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
- }
- }
+ do_multu (SD_, TRX, TRY, 0);
}
-11101,xxx,yyy,11010:RR:16::DIV
+11101,3.RX,3.RY,11010:RR:16::DIV
+"div r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Division");
- {
- int d1 = op1;
- int d2 = op2;
- if (d2 == 0)
- {
- LO = SIGNEXTEND(0x80000000,32);
- HI = SIGNEXTEND(0,32);
- }
- else if (d2 == -1 && d1 == 0x80000000)
- {
- LO = SIGNEXTEND(0x80000000,32);
- HI = SIGNEXTEND(0,32);
- }
- else
- {
- LO = SIGNEXTEND((d1 / d2),32);
- HI = SIGNEXTEND((d1 % d2),32);
- }
- }
- }
+ do_div (SD_, TRX, TRY);
}
-11101,xxx,yyy,11011:RR:16::DIVU
+11101,3.RX,3.RY,11011:RR:16::DIVU
+"divu r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Division");
- {
- unsigned int d1 = op1;
- unsigned int d2 = op2;
- if (d2 == 0)
- {
- LO = SIGNEXTEND(0x80000000,32);
- HI = SIGNEXTEND(0,32);
- }
- else if (d2 == -1 && d1 == 0x80000000)
- {
- LO = SIGNEXTEND(0x80000000,32);
- HI = SIGNEXTEND(0,32);
- }
- else
- {
- LO = SIGNEXTEND((d1 / d2),32);
- HI = SIGNEXTEND((d1 % d2),32);
- }
- }
- }
+ do_divu (SD_, TRX, TRY);
}
-11101,ddd,00010000:RR:16::MFHI
+11101,3.RX,000,10000:RR:16::MFHI
+"mfhi r<TRX>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = HI;
- HIACCESS = 3; /* 3rd instruction will be safe */
- }
+ do_mfhi (SD_, TRX);
}
-11101,ddd,00010010:RR:16::MFLO
+11101,3.RX,000,10010:RR:16::MFLO
+"mflo r<TRX>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int destreg = (instruction >> 8) & 0x7;
- if (destreg < 2)
- destreg += 16;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = LO;
- LOACCESS = 3; /* 3rd instruction will be safe */
- }
+ do_mflo (SD_, TRX);
}
-11101,xxx,yyy,11100:RR:16::DMULT
+11101,3.RX,3.RY,11100:RR:16::DMULT
+"dmult r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Multiplication");
- {
- unsigned64 mid;
- unsigned64 midhi;
- unsigned64 temp;
- int sign = 0;
- if (op1 < 0) { op1 = - op1; ++sign; }
- if (op2 < 0) { op2 = - op2; ++sign; }
- LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
- HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
- mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
- midhi = SET64HI(VL4_8(mid));
- temp = (LO + midhi);
- if ((temp == midhi) ? (LO != 0) : (temp < midhi))
- HI += 1;
- HI += VH4_8(mid);
- mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
- midhi = SET64HI(VL4_8(mid));
- LO = (temp + midhi);
- if ((LO == midhi) ? (temp != 0) : (LO < midhi))
- HI += 1;
- HI += VH4_8(mid);
- if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; }
- }
- }
+ do_dmult (SD_, TRX, TRY, 0);
}
-11101,xxx,yyy,11101:RR:16::DMULTU
+11101,3.RX,3.RY,11101:RR:16::DMULTU
+"dmultu r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Multiplication");
- {
- unsigned64 mid;
- unsigned64 midhi;
- unsigned64 temp;
- LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
- HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
- mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
- midhi = SET64HI(VL4_8(mid));
- temp = (LO + midhi);
- if ((temp == midhi) ? (LO != 0) : (temp < midhi))
- HI += 1;
- HI += VH4_8(mid);
- mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
- midhi = SET64HI(VL4_8(mid));
- LO = (temp + midhi);
- if ((LO == midhi) ? (temp != 0) : (LO < midhi))
- HI += 1;
- HI += VH4_8(mid);
- }
- }
+ do_dmultu (SD_, TRX, TRY, 0);
}
-11101,xxx,yyy,11110:RR:16::DDIV
+11101,3.RX,3.RY,11110:RR:16::DDIV
+"ddiv r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Division");
- {
- word64 d1 = op1;
- word64 d2 = op2;
- if (d2 == 0)
- {
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
- }
- else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
- {
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
- }
- else
- {
- LO = (d1 / d2);
- HI = (d1 % d2);
- }
- }
- }
+ do_ddiv (SD_, TRX, TRY);
}
-11101,xxx,yyy,11111:RR:16::DDIVU
+11101,3.RX,3.RY,11111:RR:16::DDIVU
+"ddivu r<TRX>, r<TRY>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- signed_word op2 = (instruction >> 5) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (op2 < 2)
- op2 += 16;
- op2 = GPR[op2];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- CHECKHILO("Division");
- {
- unsigned64 d1 = op1;
- unsigned64 d2 = op2;
- if (d2 == 0)
- {
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
- }
- else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
- {
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
- }
- else
- {
- LO = (d1 / d2);
- HI = (d1 % d2);
- }
- }
- }
+ do_ddivu (SD_, TRX, TRY);
}
// Jump and Branch Instructions
-// JALX
-// JAL
-00011,aaaaaaaaaaa:I:16::JAL
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- unsigned_word op1 = (instruction >> 0) & 0x7ff;
- {
- address_word paddr;
- int uncached;
- if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL))
- {
- unsigned64 memval;
- unsigned int reverse = (ReverseEndian ? 3 : 0);
- unsigned int bigend = (BigEndianCPU ? 3 : 0);
- unsigned int byte;
- paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1)));
- LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL);
- byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1));
- memval = (memval >> (8 * byte)) & 0xffff;
- op1 = (((op1 & 0x1f) << 23)
- | ((op1 & 0x3e0) << 13)
- | (memval << 2));
- if ((instruction & 0x400) == 0)
- op1 |= 1;
- PC += 2;
- }
- }
- op1 |= PC & ~ (unsigned64) 0x0fffffff;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int destreg = 31;
- GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
- /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
- so we just truncate it to 32 bits here. */
- op1 = VL4_8(op1);
- /* NOTE: The jump occurs AFTER the next instruction has been executed */
- DELAY_SLOT op1;
- JALDELAYSLOT();
- }
-}
-
-
-11101,xxx,00000000:RR:16::JR
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
- so we just truncate it to 32 bits here. */
- op1 = VL4_8(op1);
- /* NOTE: The jump occurs AFTER the next instruction has been executed */
- DELAY_SLOT op1;
- DELAYSLOT();
- }
-}
-
-
-1110100000100000,r:RR:16::JRRA
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = 31;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
- so we just truncate it to 32 bits here. */
- op1 = VL4_8(op1);
- /* NOTE: The jump occurs AFTER the next instruction has been executed */
- DELAY_SLOT op1;
- DELAYSLOT();
- }
-}
-
-
-11101,xxx,01000000,R:RR:16::JALR
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int destreg = 31;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
- /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
- so we just truncate it to 32 bits here. */
- op1 = VL4_8(op1);
- /* NOTE: The jump occurs AFTER the next instruction has been executed */
- DELAY_SLOT op1;
- DELAYSLOT();
- }
-}
-
-
-00100,xxx,pppppppp,z:RI:16::BEQZ
-*mips16:
-{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op2 = 0;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
+
+// Issue instruction in delay slot of branch
+:function:::address_word:delayslot16:address_word nia, address_word target
+{
+ instruction_word delay_insn;
+ sim_events_slip (SD, 1);
+ DSPC = CIA; /* save current PC somewhere */
+ STATE |= simDELAYSLOT;
+ delay_insn = IMEM16 (nia); /* NOTE: mips16 */
+ idecode_issue (CPU_, delay_insn, (nia));
+ STATE &= ~simDELAYSLOT;
+ return target;
+}
+
+// compute basepc dependant on us being in a delay slot
+:function:::address_word:basepc:
+{
+ if (STATE & simDELAYSLOT)
{
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
+ return DSPC; /* return saved address of preceeding jmp */
}
else
{
- if (offset >= 0x80)
- offset -= 0x100;
+ return CIA;
}
- offset *= 2;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 == op2);
- if (condition)
- PC = PC + offset;
- }
}
-00101,xxx,pppppppp,z:RI:16::BNEZ
+// JAL
+00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JAL:16::JAL
+"jal <IMMEDIATE>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- signed_word op1 = (instruction >> 8) & 0x7;
- int offset = (instruction >> 0) & 0xff;
- signed_word op2 = 0;
- if (op1 < 2)
- op1 += 16;
- op1 = GPR[op1];
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (offset >= 0x80)
- offset -= 0x100;
- }
- offset *= 2;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 != op2);
- if (condition)
- PC = PC + offset;
- }
+ address_word region = (NIA & MASK (63, 28));
+ RA = NIA + 2; /* skip 16 bit delayslot insn */
+ NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2))) | 1;
}
-01100000,pppppppp,t,z:I8:16::BTEQZ
+
+// JALX - 32 and 16 bit versions.
+
+011101,26.IMMED:JALX:32::JALX32
+"jalx <IMMED>"
+*mips32:
+*mips64:
+*mips32r2:
+*mips64r2:
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 24;
- signed_word op2 = 0;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (offset >= 0x80)
- offset -= 0x100;
- }
- offset *= 2;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 == op2);
- if (condition)
- PC = PC + offset;
- }
+ address_word region = (NIA & MASK (63, 28));
+ RA = NIA + 4; /* skip 32 bit delayslot insn */
+ NIA = delayslot32 (SD_, (region | (IMMED << 2)) | 1);
+}
+
+00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JALX:16::JALX16
+"jalx <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ address_word region = (NIA & MASK (63, 28));
+ RA = NIA + 2; /* 16 bit INSN */
+ NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2)) & ~1);
}
-01100001,pppppppp,t,z:I8:16::BTNEZ
+
+11101,3.RX,000,00000:RR:16::JR
+"jr r<TRX>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0xff;
- signed_word op1 = 24;
- signed_word op2 = 0;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (offset >= 0x80)
- offset -= 0x100;
- }
- offset *= 2;
- op1 = GPR[op1];
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 != op2);
- if (condition)
- PC = PC + offset;
- }
+ NIA = delayslot16 (SD_, NIA, GPR[TRX]);
}
-00010,qqqqqqqqqqq,z,Z:I:16::B
+11101,000,001,00000:RR:16::JRRA
+"jrra"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int offset = (instruction >> 0) & 0x7ff;
- signed_word op2 = 0;
- signed_word op1 = 0;
- if (have_extendval)
- {
- offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
- if (offset >= 0x8000)
- offset -= 0x10000;
- have_extendval = 0;
- }
- else
- {
- if (offset >= 0x400)
- offset -= 0x800;
- }
- offset *= 2;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- int condition = (op1 == op2);
- if (condition)
- PC = PC + offset;
- }
+ NIA = delayslot16 (SD_, NIA, RA);
+}
+
+
+
+11101,3.RX,010,00000:RR:16::JALR
+"jalr r<TRX>"
+*mips16:
+*vr4100:
+{
+ RA = NIA + 2;
+ NIA = delayslot16 (SD_, NIA, GPR[TRX]);
+}
+
+
+
+00100,3.RX,8.IMMED:RI:16::BEQZ
+"beqz r<TRX>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ if (GPR[TRX] == 0)
+ NIA = (NIA + (EXTEND8 (IMMED) << 1));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 00100,3.RX,000,5.IMM_4_0:EXT-RI:16::BEQZ
+"beqz r<TRX>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ if (GPR[TRX] == 0)
+ NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
+}
+
+
+
+00101,3.RX,8.IMMED:RI:16::BNEZ
+"bnez r<TRX>, <IMMED>"
+*mips16:
+*vr4100:
+{
+ if (GPR[TRX] != 0)
+ NIA = (NIA + (EXTEND8 (IMMED) << 1));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 00101,3.RX,000,5.IMM_4_0:EXT-RI:16::BNEZ
+"bnez r<TRX>, <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ if (GPR[TRX] != 0)
+ NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
+}
+
+
+
+01100,000,8.IMMED:I8:16::BTEQZ
+"bteqz <IMMED>"
+*mips16:
+*vr4100:
+{
+ if (T8 == 0)
+ NIA = (NIA + (EXTEND8 (IMMED) << 1));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 01100,000,000,5.IMM_4_0:EXT-I8:16::BTEQZ
+"bteqz <IMMEDIATE>"
+*mips16:
+*vr4100:
+{
+ if (T8 == 0)
+ NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
}
-// Special Instructions
+01100,001,8.IMMED:I8:16::BTNEZ
+"btnez <IMMED>"
+*mips16:
+*vr4100:
+{
+ if (T8 != 0)
+ NIA = (NIA + (EXTEND8 (IMMED) << 1));
+}
-// See the front of the mips16 doc
-11110,eeeeeeeeeee:I:16::EXTEND
+11110,6.IMM_10_5,5.IMM_15_11 + 01100,001,000,5.IMM_4_0:EXT-I8:16::BTNEZ
+"btnez <IMMEDIATE>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- int ext = (instruction >> 0) & 0x7ff;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- extendval = ext;
- have_extendval = 1;
- }
+ if (T8 != 0)
+ NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
}
-01100,******,00101:RR:16::BREAK
+
+00010,11.IMMED:I:16::B
+"b <IMMED>"
+*mips16:
+*vr4100:
+{
+ NIA = (NIA + (EXTEND11 (IMMED) << 1));
+}
+
+11110,6.IMM_10_5,5.IMM_15_11 + 00010,6.0,5.IMM_4_0:EXT-I:16::B
+"b <IMMEDIATE>"
*mips16:
+*vr4100:
{
- unsigned32 instruction = instruction_0;
- if (have_extendval)
- SignalException (ReservedInstruction, instruction);
- {
- SignalException(BreakPoint,instruction);
- }
+ NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
}
+
+
+11101,3.RX,3.RY,00101:RR:16::BREAK
+"break"
+*mips16:
+*vr4100:
+{
+ do_break16 (SD_, instruction_0);
+}
projects / deliverable / binutils-gdb.git / blobdiff