// Simulator definition for the micromips ASE.
-// Copyright (C) 2005-2015 Free Software Foundation, Inc.
+// Copyright (C) 2005-2020 Free Software Foundation, Inc.
// Contributed by Imagination Technologies, Ltd.
// Written by Andrew Bennett <andrew.bennett@imgtec.com>
//
:compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
:function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
+*micromipsdsp:
{
instruction_word delay_insn;
sim_events_slip (SD, 1);
}
:function:::address_word:process_isa_mode:address_word target
+*micromips32:
+*micromips64:
{
SD->isa_mode = target & 0x1;
return (target & (-(1 << 1)));
}
:function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
{
GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
return (process_isa_mode (SD_,
}
:function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
+*micromips32:
+*micromips64:
{
RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
:function:::unsigned32:compute_movep_src_reg:int reg
+*micromips32:
+*micromips64:
{
switch(reg)
{
}
:function:::unsigned32:compute_andi16_imm:int encoded_imm
+*micromips32:
+*micromips64:
{
switch (encoded_imm)
{
}
:function:::FP_formats:convert_fmt_micromips:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
}
:function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
:function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
:%s::::FMT_MICROMIPS:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
:%s::::FMT_MICROMIPS_CVT_D:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{
:%s::::FMT_MICROMIPS_CVT_S:int fmt
+*micromips32:
+*micromips64:
{
switch (fmt)
{