+// -*- C -*-
+//
+// In mips.igen, the semantics for many of the instructions were created
+// using code generated by gencode. Those semantic segments could be
+// greatly simplified.
+//
// <insn> ::=
// <insn-word> { "+" <insn-word> }
// ":" <format-name>
// IGEN config - mips16
-:option:16::insn-bit-size:16
-:option:16::hi-bit-nr:15
+// :option:16::insn-bit-size:16
+// :option:16::hi-bit-nr:15
:option:16::insn-specifying-widths:true
:option:16::gen-delayed-branch:false
// IGEN config - mips32/64..
-:option:32::insn-bit-size:32
-:option:32::hi-bit-nr:31
+// :option:32::insn-bit-size:32
+// :option:32::hi-bit-nr:31
:option:32::insn-specifying-widths:true
:option:32::gen-delayed-branch:false
// :option:::multi-sim:true
-// Models known by this simulator
-:model:::mipsI:mipsI:
-:model:::mipsII:mipsII:
-:model:::mipsIII:mipsIII:
-:model:::mipsIV:mipsIV:
-:model:::mips16:mips16:
-// start-sanitize-r5900
-:model:::r5900:r5900:
-// end-sanitize-r5900
-:model:::r3900:r3900:
-// start-sanitize-tx19
-:model:::tx19:tx19:
-// end-sanitize-tx19
-// start-sanitize-vr5400
-:model:::vr5400:vr5400:
-// end-sanitize-vr5400
+// Models known by this simulator are defined below.
+//
+// When placing models in the instruction descriptions, please place
+// them one per line, in the order given here.
+// MIPS ISAs:
+//
+// Instructions and related functions for these models are included in
+// this file.
+:model:::mipsI:mips3000:
+:model:::mipsII:mips6000:
+:model:::mipsIII:mips4000:
+:model:::mipsIV:mips8000:
+:model:::mipsV:mipsisaV:
+
+// Vendor ISAs:
+//
+// Standard MIPS ISA instructions used for these models are listed here,
+// as are functions needed by those standard instructions. Instructions
+// which are model-dependent and which are not in the standard MIPS ISAs
+// (or which pre-date or use different encodings than the standard
+// instructions) are (for the most part) in separate .igen files.
+:model:::vr4100:mips4100: // vr.igen
+:model:::vr5000:mips5000:
+:model:::r3900:mips3900: // tx.igen
+
+// MIPS Application Specific Extensions (ASEs)
+//
+// Instructions for the ASEs are in separate .igen files.
+:model:::mips16:mips16: // m16.igen (and m16.dc)
// Pseudo instructions known by IGEN
:internal::::illegal:
{
- /* FIXME: This ifetch causes a double count of a fetch at CIA */
- SignalException (ReservedInstruction, IMEM (CIA));
+ SignalException (ReservedInstruction, 0);
+}
+
+
+// Pseudo instructions known by interp.c
+// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
+000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
+"rsvd <OP>"
+{
+ SignalException (ReservedInstruction, instruction_0);
+}
+
+
+
+// Helper:
+//
+// Simulate a 32 bit delayslot instruction
+//
+
+:function:::address_word:delayslot32:address_word target
+{
+ instruction_word delay_insn;
+ sim_events_slip (SD, 1);
+ DSPC = CIA;
+ CIA = CIA + 4; /* NOTE not mips16 */
+ STATE |= simDELAYSLOT;
+ delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
+ ENGINE_ISSUE_PREFIX_HOOK();
+ idecode_issue (CPU_, delay_insn, (CIA));
+ STATE &= ~simDELAYSLOT;
+ return target;
+}
+
+:function:::address_word:nullify_next_insn32:
+{
+ sim_events_slip (SD, 1);
+ dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
+ return CIA + 8;
+}
+
+// Helper:
+//
+// Check that an access to a HI/LO register meets timing requirements
+//
+// The following requirements exist:
+//
+// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
+// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
+// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
+// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
+//
+
+:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
+{
+ if (history->mf.timestamp + 3 > time)
+ {
+ sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
+ itable[MY_INDEX].name,
+ new, (long) CIA,
+ (long) history->mf.cia);
+ return 0;
+ }
+ return 1;
+}
+
+:function:::int:check_mt_hilo:hilo_history *history
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = check_mf_cycles (SD_, history, time, "MT");
+ history->mt.timestamp = time;
+ history->mt.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_mt_hilo:hilo_history *history
+*r3900:
+{
+ signed64 time = sim_events_time (SD);
+ history->mt.timestamp = time;
+ history->mt.cia = CIA;
+ return 1;
+}
+
+
+:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = 1;
+ if (peer != NULL
+ && peer->mt.timestamp > history->op.timestamp
+ && history->mt.timestamp < history->op.timestamp
+ && ! (history->mf.timestamp > history->op.timestamp
+ && history->mf.timestamp < peer->mt.timestamp)
+ && ! (peer->mf.timestamp > history->op.timestamp
+ && peer->mf.timestamp < peer->mt.timestamp))
+ {
+ /* The peer has been written to since the last OP yet we have
+ not */
+ sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
+ itable[MY_INDEX].name,
+ (long) CIA,
+ (long) history->op.cia,
+ (long) peer->mt.cia);
+ ok = 0;
+ }
+ history->mf.timestamp = time;
+ history->mf.cia = CIA;
+ return ok;
+}
+
+
+
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP"));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+// The r3900 mult and multu insns _can_ be exectuted immediatly after
+// a mf{hi,lo}
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*r3900:
+{
+ /* FIXME: could record the fact that a stall occured if we want */
+ signed64 time = sim_events_time (SD);
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return 1;
+}
+
+
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP"));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
}
+
//
-// Mips Architecture:
+// MIPS Architecture:
//
-// CPU Instruction Set (mipsI - mipsIV)
+// CPU Instruction Set (mipsI - mipsV)
//
+
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- ALU32_BEGIN (GPR[RS]);
- ALU32_ADD (GPR[RT]);
- ALU32_END (GPR[RD]);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ {
+ ALU32_BEGIN (GPR[RS]);
+ ALU32_ADD (GPR[RT]);
+ ALU32_END (GPR[RD]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[RD]);
}
+
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
-"addi r<RT>, r<RS>, IMMEDIATE"
+"addi r<RT>, r<RS>, <IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- ALU32_BEGIN (GPR[RS]);
- ALU32_ADD (EXTEND16 (IMMEDIATE));
- ALU32_END (GPR[RT]);
+ TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
+ {
+ ALU32_BEGIN (GPR[RS]);
+ ALU32_ADD (EXTEND16 (IMMEDIATE));
+ ALU32_END (GPR[RT]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[RT]);
}
+
+:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
-"add r<RT>, r<RS>, <IMMEDIATE>"
+"addiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
- GPR[RT] = EXTEND32 (temp);
+ do_addiu (SD_, RS, RT, IMMEDIATE);
}
+
+:function:::void:do_addu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
+"addu r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- signed32 temp = GPR[RS] + GPR[RT];
- GPR[RD] = EXTEND32 (temp);
+ do_addu (SD_, RS, RT, RD);
}
+
+:function:::void:do_and:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = GPR[rs] & GPR[rt];
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] & GPR[RT];
+ do_and (SD_, RS, RT, RD);
}
+
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
-"and r<RT>, r<RS>, IMMEDIATE"
+"and r<RT>, r<RS>, <IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
+ TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
GPR[RT] = GPR[RS] & IMMEDIATE;
+ TRACE_ALU_RESULT (GPR[RT]);
}
+
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
- if (GPR[RS] == GPR[RT])
- DELAY_SLOT (CIA + offset);
+ check_branch_bug ();
+ if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
"beql r<RS>, r<RT>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
- if (GPR[RS] == GPR[RT])
- DELAY_SLOT (CIA + offset);
+ check_branch_bug ();
+ if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
- if (GPR[RS] >= 0)
- DELAY_SLOT (CIA + offset);
+ check_branch_bug ();
+ if ((signed_word) GPR[RS] >= 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
RA = (CIA + 8);
- if (GPR[RS] >= 0)
- DELAY_SLOT (CIA + offset);
+ if ((signed_word) GPR[RS] >= 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
"bgezall r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
RA = (CIA + 8);
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
- if (GPR[RS] >= 0)
- DELAY_SLOT (CIA + offset);
+ if ((signed_word) GPR[RS] >= 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
- if (GPR[RS] >= 0)
- DELAY_SLOT (CIA + offset);
+ check_branch_bug ();
+ if ((signed_word) GPR[RS] >= 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
- if (GPR[RS] > 0)
- DELAY_SLOT (CIA + offset);
+ check_branch_bug ();
+ if ((signed_word) GPR[RS] > 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
"bgtzl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
- if (GPR[RS] > 0)
- DELAY_SLOT (CIA + offset);
+ if ((signed_word) GPR[RS] > 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
- if (GPR[RS] <= 0)
- DELAY_SLOT (CIA + offset);
+ if ((signed_word) GPR[RS] <= 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
"bgezl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
- if (GPR[RS] <= 0)
- DELAY_SLOT (CIA + offset);
+ check_branch_bug ();
+ if ((signed_word) GPR[RS] <= 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
- if (GPR[RS] < 0)
- DELAY_SLOT (CIA + offset);
+ check_branch_bug ();
+ if ((signed_word) GPR[RS] < 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
RA = (CIA + 8);
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
- if (GPR[RS] < 0)
- DELAY_SLOT (CIA + offset);
+ if ((signed_word) GPR[RS] < 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
"bltzall r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
RA = (CIA + 8);
- if (GPR[RS] < 0)
- DELAY_SLOT (CIA + offset);
+ if ((signed_word) GPR[RS] < 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
"bltzl r<RS>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
+ check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
- if (GPR[RS] < 0)
- DELAY_SLOT (CIA + offset);
+ if ((signed_word) GPR[RS] < 0)
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
- if (GPR[RS] != GPR[RT])
- DELAY_SLOT (CIA + offset);
+ check_branch_bug ();
+ if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
}
+
010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
"bnel r<RS>, r<RT>, <OFFSET>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word offset = EXTEND16 (OFFSET) << 2;
- if (GPR[RS] != GPR[RT])
- DELAY_SLOT (CIA + offset);
+ check_branch_bug ();
+ if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
+ {
+ mark_branch_bug (NIA+offset);
+ DELAY_SLOT (NIA + offset);
+ }
else
NULLIFY_NEXT_INSTRUCTION ();
}
+
000000,20.CODE,001101:SPECIAL:32::BREAK
-"break"
+"break <CODE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- SignalException(BreakPoint, instruction_0);
-}
-
+ /* Check for some break instruction which are reserved for use by the simulator. */
+ unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
+ if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
+ break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+ {
+ sim_engine_halt (SD, CPU, NULL, cia,
+ sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
+ }
+ else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
+ break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+ {
+ if (STATE & simDELAYSLOT)
+ PC = cia - 4; /* reference the branch instruction */
+ else
+ PC = cia;
+ SignalException(BreakPoint, instruction_0);
+ }
-0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
-"cop<ZZ> <COP_FUN>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
- DecodeCoproc (instruction_0);
+ else
+ {
+ /* If we get this far, we're not an instruction reserved by the sim. Raise
+ the exception. */
+ SignalException(BreakPoint, instruction_0);
+ }
}
+
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
"dadd r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- ALU64_BEGIN (GPR[RS]);
- ALU64_ADD (GPR[RT]);
- ALU64_END (GPR[RT]);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ {
+ ALU64_BEGIN (GPR[RS]);
+ ALU64_ADD (GPR[RT]);
+ ALU64_END (GPR[RD]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[RD]);
}
+
011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
"daddi r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- ALU64_BEGIN (GPR[RS]);
- ALU64_ADD (EXTEND16 (IMMEDIATE));
- ALU64_END (GPR[RT]);
+ TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
+ {
+ ALU64_BEGIN (GPR[RS]);
+ ALU64_ADD (EXTEND16 (IMMEDIATE));
+ ALU64_END (GPR[RT]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[RT]);
}
+
+:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ GPR[rt] = GPR[rs] + EXTEND16 (immediate);
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
-"daddu r<RT>, r<RS>, <IMMEDIATE>"
+"daddiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
+ do_daddiu (SD_, RS, RT, IMMEDIATE);
}
+
+:function:::void:do_daddu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = GPR[rs] + GPR[rt];
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
"daddu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- GPR[RD] = GPR[RS] + GPR[RT];
+ do_daddu (SD_, RS, RT, RD);
}
-000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
-"ddiv r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+
+:function:::void:do_ddiv:int rs, int rt
{
- CHECKHILO ("Division");
+ check_div_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- signed64 n = GPR[RS];
- signed64 d = GPR[RT];
+ signed64 n = GPR[rs];
+ signed64 d = GPR[rt];
+ signed64 hi;
+ signed64 lo;
if (d == 0)
{
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
+ lo = SIGNED64 (0x8000000000000000);
+ hi = 0;
}
else if (d == -1 && n == SIGNED64 (0x8000000000000000))
{
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
+ lo = SIGNED64 (0x8000000000000000);
+ hi = 0;
}
else
{
- LO = (n / d);
- HI = (n % d);
+ lo = (n / d);
+ hi = (n % d);
}
+ HI = hi;
+ LO = lo;
}
+ TRACE_ALU_RESULT2 (HI, LO);
}
-
-
-000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
-"ddivu r<RS>, r<RT>"
+000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
+"ddiv r<RS>, r<RT>"
*mipsIII:
*mipsIV:
-*r3900:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
- CHECKHILO ("Division");
+*mipsV:
+*vr4100:
+*vr5000:
+{
+ do_ddiv (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_ddivu:int rs, int rt
+{
+ check_div_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- unsigned64 n = GPR[RS];
- unsigned64 d = GPR[RT];
+ unsigned64 n = GPR[rs];
+ unsigned64 d = GPR[rt];
+ unsigned64 hi;
+ unsigned64 lo;
if (d == 0)
{
- LO = SIGNED64 (0x8000000000000000);
- HI = 0;
+ lo = SIGNED64 (0x8000000000000000);
+ hi = 0;
}
else
{
- LO = (n / d);
- HI = (n % d);
+ lo = (n / d);
+ hi = (n % d);
}
+ HI = hi;
+ LO = lo;
}
+ TRACE_ALU_RESULT2 (HI, LO);
}
-
-000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
-"div r<RS>, r<RT>"
-*mipsI:
-*mipsII:
+000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
+"ddivu r<RS>, r<RT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
+{
+ do_ddivu (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_div:int rs, int rt
{
- CHECKHILO("Division");
+ check_div_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- signed32 n = GPR[RS];
- signed32 d = GPR[RT];
+ signed32 n = GPR[rs];
+ signed32 d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
- else if (d == -1 && d == 0x80000000)
+ else if (n == SIGNED32 (0x80000000) && d == -1)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
HI = EXTEND32 (n % d);
}
}
+ TRACE_ALU_RESULT2 (HI, LO);
}
-
-000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
-"divu r<RS>, r<RT>"
+000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
+"div r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- CHECKHILO ("Division");
+ do_div (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_divu:int rs, int rt
+{
+ check_div_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- unsigned32 n = GPR[RS];
- unsigned32 d = GPR[RT];
+ unsigned32 n = GPR[rs];
+ unsigned32 d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (n % d);
}
}
+ TRACE_ALU_RESULT2 (HI, LO);
}
-
-000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
-"dmult r<RS>, r<RT>"
+000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
+"divu r<RS>, r<RT>"
+*mipsI:
+*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- CHECKHILO ("Multiplication");
- {
- signed64 op1 = GPR[RS];
- signed64 op2 = GPR[RT];
- unsigned64 lo;
- unsigned64 hi;
- unsigned64 m00;
- unsigned64 m01;
- unsigned64 m10;
- unsigned64 m11;
- unsigned64 mid;
- int sign = 0;
- /* make it unsigned */
- if (op1 < 0)
- {
- op1 = - op1;
- ++sign;
- }
- if (op2 < 0)
- {
- op2 = - op2;
- ++sign;
- }
- /* multuply out the 4 sub products */
- m00 = (VL4_8 (op1) * VL4_8 (op2));
- m10 = (VH4_8 (op1) * VL4_8 (op2));
- m01 = (VL4_8 (op1) * VH4_8 (op2));
- m11 = (VH4_8 (op1) * VH4_8 (op2));
- /* add the products */
- mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
- lo = U8_4 (mid, m00);
- hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
- /* save the result */
- if (sign & 1)
- {
- LO = -lo;
- if (lo == 0)
- HI = -hi;
- else
- HI = -hi - 1;
- }
- else
- {
- LO = lo;
- HI = hi;
- }
- }
+ do_divu (SD_, RS, RT);
}
-000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
-"dmultu r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
- CHECKHILO ("Multiplication");
- {
- signed64 op1 = GPR[RS];
- signed64 op2 = GPR[RT];
- unsigned64 lo;
- unsigned64 hi;
- unsigned64 m00;
- unsigned64 m01;
- unsigned64 m10;
- unsigned64 m11;
- unsigned64 mid;
- /* multuply out the 4 sub products */
- m00 = (VL4_8 (op1) * VL4_8 (op2));
- m10 = (VH4_8 (op1) * VL4_8 (op2));
- m01 = (VL4_8 (op1) * VH4_8 (op2));
- m11 = (VH4_8 (op1) * VH4_8 (op2));
- /* add the products */
- mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
- lo = U8_4 (mid, m00);
- hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
- /* save the result */
- LO = lo;
- HI = hi;
- }
-}
-
-00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
-"dsll r<RD>, r<RT>, <SHIFT>"
-*mipsIII:
-*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
- int s = SHIFT;
- GPR[RD] = GPR[RT] << s;
+ unsigned64 lo;
+ unsigned64 hi;
+ unsigned64 m00;
+ unsigned64 m01;
+ unsigned64 m10;
+ unsigned64 m11;
+ unsigned64 mid;
+ int sign;
+ unsigned64 op1 = GPR[rs];
+ unsigned64 op2 = GPR[rt];
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ /* make signed multiply unsigned */
+ sign = 0;
+ if (signed_p)
+ {
+ if (op1 < 0)
+ {
+ op1 = - op1;
+ ++sign;
+ }
+ if (op2 < 0)
+ {
+ op2 = - op2;
+ ++sign;
+ }
+ }
+ /* multiply out the 4 sub products */
+ m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
+ m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
+ m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
+ m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
+ /* add the products */
+ mid = ((unsigned64) VH4_8 (m00)
+ + (unsigned64) VL4_8 (m10)
+ + (unsigned64) VL4_8 (m01));
+ lo = U8_4 (mid, m00);
+ hi = (m11
+ + (unsigned64) VH4_8 (mid)
+ + (unsigned64) VH4_8 (m01)
+ + (unsigned64) VH4_8 (m10));
+ /* fix the sign */
+ if (sign & 1)
+ {
+ lo = -lo;
+ if (lo == 0)
+ hi = -hi;
+ else
+ hi = -hi - 1;
+ }
+ /* save the result HI/LO (and a gpr) */
+ LO = lo;
+ HI = hi;
+ if (rd != 0)
+ GPR[rd] = lo;
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_dmult:int rs, int rt, int rd
+{
+ do_dmultx (SD_, rs, rt, rd, 1);
+}
+
+000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
+"dmult r<RS>, r<RT>"
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+{
+ do_dmult (SD_, RS, RT, 0);
+}
+
+000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
+"dmult r<RS>, r<RT>":RD == 0
+"dmult r<RD>, r<RS>, r<RT>"
+*vr5000:
+{
+ do_dmult (SD_, RS, RT, RD);
+}
+
+
+
+:function:::void:do_dmultu:int rs, int rt, int rd
+{
+ do_dmultx (SD_, rs, rt, rd, 0);
+}
+
+000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
+"dmultu r<RS>, r<RT>"
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+{
+ do_dmultu (SD_, RS, RT, 0);
+}
+
+000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
+"dmultu r<RD>, r<RS>, r<RT>":RD == 0
+"dmultu r<RS>, r<RT>"
+*vr5000:
+{
+ do_dmultu (SD_, RS, RT, RD);
+}
+
+:function:::void:do_dsll:int rt, int rd, int shift
+{
+ GPR[rd] = GPR[rt] << shift;
+}
+
+:function:::void:do_dsllv:int rs, int rt, int rd
+{
+ int s = MASKED64 (GPR[rs], 5, 0);
+ GPR[rd] = GPR[rt] << s;
+}
+
+
+000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
+"dsll r<RD>, r<RT>, <SHIFT>"
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+{
+ do_dsll (SD_, RT, RD, SHIFT);
}
-00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
+000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
"dsll32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
int s = 32 + SHIFT;
GPR[RD] = GPR[RT] << s;
}
-
-000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
+000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- int s = MASKED64 (GPR[RS], 5, 0);
- GPR[RD] = GPR[RT] << s;
+ do_dsllv (SD_, RS, RT, RD);
+}
+
+:function:::void:do_dsra:int rt, int rd, int shift
+{
+ GPR[rd] = ((signed64) GPR[rt]) >> shift;
}
-00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
+000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- int s = SHIFT;
- GPR[RD] = ((signed64) GPR[RT]) >> s;
+ do_dsra (SD_, RT, RD, SHIFT);
}
-00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
+000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
"dsra32 r<RT>, r<RD>, <SHIFT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
int s = 32 + SHIFT;
GPR[RD] = ((signed64) GPR[RT]) >> s;
}
-000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
-"dsra32 r<RT>, r<RD>, r<RS>"
+:function:::void:do_dsrav:int rs, int rt, int rd
+{
+ int s = MASKED64 (GPR[rs], 5, 0);
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = ((signed64) GPR[rt]) >> s;
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
+"dsrav r<RT>, r<RD>, r<RS>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- int s = MASKED64 (GPR[RS], 5, 0);
- GPR[RD] = ((signed64) GPR[RT]) >> s;
+ do_dsrav (SD_, RS, RT, RD);
+}
+
+:function:::void:do_dsrl:int rt, int rd, int shift
+{
+ GPR[rd] = (unsigned64) GPR[rt] >> shift;
}
-00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
-"dsrav r<RD>, r<RT>, <SHIFT>"
+000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
+"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- int s = SHIFT;
- GPR[RD] = (unsigned64) GPR[RT] >> s;
+ do_dsrl (SD_, RT, RD, SHIFT);
}
-00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
+000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
"dsrl32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
int s = 32 + SHIFT;
GPR[RD] = (unsigned64) GPR[RT] >> s;
}
-000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
-"dsrl32 r<RD>, r<RT>, r<RS>"
+:function:::void:do_dsrlv:int rs, int rt, int rd
+{
+ int s = MASKED64 (GPR[rs], 5, 0);
+ GPR[rd] = (unsigned64) GPR[rt] >> s;
+}
+
+
+
+000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
+"dsrlv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- int s = MASKED64 (GPR[RS], 5, 0);
- GPR[RD] = (unsigned64) GPR[RT] >> s;
+ do_dsrlv (SD_, RS, RT, RD);
}
-000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
+000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
"dsub r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- ALU64_BEGIN (GPR[RS]);
- ALU64_SUB (GPR[RT]);
- ALU64_END (GPR[RD]);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ {
+ ALU64_BEGIN (GPR[RS]);
+ ALU64_SUB (GPR[RT]);
+ ALU64_END (GPR[RD]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[RD]);
}
-000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
+:function:::void:do_dsubu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = GPR[rs] - GPR[rt];
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- GPR[RD] = GPR[RS] - GPR[RT];
+ do_dsubu (SD_, RS, RT, RD);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
/* NOTE: The region used is that of the delay slot NIA and NOT the
current instruction */
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
/* NOTE: The region used is that of the delay slot and NOT the
current instruction */
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
-
-000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
+000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
address_word temp = GPR[RS];
GPR[RD] = CIA + 8;
}
-000000,5.RS,000000000000000001000:SPECIAL:32::JR
+000000,5.RS,000000000000000,001000:SPECIAL:32::JR
"jr r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
DELAY_SLOT (GPR[RS]);
}
+:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ if ((vaddr & access) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
+ }
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ return (memval >> (8 * byte));
+}
+
+
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((uword64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- uword64 memval = 0;
- uword64 memval1 = 0;
- uword64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
- }
- }
- }
+ GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
- }
- }
- }
+ GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
}
"ld r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
- }
- }
- }
+ GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
- }
- }
- }
+ COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
+
+
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
"ldl r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
- }
- }
- }
+ GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
"ldr r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
- {
- unsigned64 srcmask;
- if (byte == 0)
- srcmask = 0;
- else
- srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
- GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
- }
- }
- }
- }
+ GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
- }
- }
- }
+ GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
- }
- }
- }
+ GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
"lld r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
address_word paddr;
int uncached;
if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
+ TRACE_ALU_INPUT1 (IMMEDIATE);
GPR[RT] = EXTEND32 (IMMEDIATE << 16);
+ TRACE_ALU_RESULT (GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
- }
- }
- }
+ GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ unsigned int word;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+ int nr_lhs_bits;
+ int nr_rhs_bits;
+ unsigned_word lhs_mask;
+ unsigned_word temp;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem == 0)
+ paddr = paddr & ~access;
+
+ /* compute where within the word/mem we are */
+ byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+ word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+ nr_lhs_bits = 8 * byte + 8;
+ nr_rhs_bits = 8 * access - 8 * byte;
+ /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+
+ /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+ (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+ (long) ((unsigned64) paddr >> 32), (long) paddr,
+ word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+ LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
+ if (word == 0)
+ {
+ /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
+ temp = (memval << nr_rhs_bits);
+ }
+ else
+ {
+ /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
+ temp = (memval >> nr_lhs_bits);
+ }
+ lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
+ rt = (rt & ~lhs_mask) | (temp & lhs_mask);
+
+ /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
+ (long) ((unsigned64) memval >> 32), (long) memval,
+ (long) ((unsigned64) temp >> 32), (long) temp,
+ (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
+ (long) (rt >> 32), (long) rt); */
+ return rt;
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
+}
+
+
+:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem != 0)
+ paddr = paddr & ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
+ LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
+ /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
+ (long) paddr, byte, (long) paddr, (long) memval); */
{
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval >>= 32;
- }
- GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
- }
+ unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
+ rt &= ~screen;
+ rt |= (memval >> (8 * byte)) & screen;
}
+ return rt;
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval >>= 32;
- }
- {
- unsigned64 srcmask;
- if (byte == 0)
- srcmask = 0;
- else
- srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
- GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
- }
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
- }
- }
+ GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
}
"lwu r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
}
+:function:::void:do_mfhi:int rd
+{
+ check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT1 (HI);
+ GPR[rd] = HI;
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = HI;
- HIACCESS = 3;
+ do_mfhi (SD_, RD);
}
+
+:function:::void:do_mflo:int rd
+{
+ check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
+ TRACE_ALU_INPUT1 (LO);
+ GPR[rd] = LO;
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = LO;
- LOACCESS = 3; /* 3rd instruction will be safe */
+ do_mflo (SD_, RD);
}
-000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
+
+000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
if (GPR[RT] != 0)
GPR[RD] = GPR[RS];
}
-000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
+
+000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
if (GPR[RT] == 0)
GPR[RD] = GPR[RS];
}
+
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- if (HIACCESS != 0)
- sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
+ check_mt_hilo (SD_, HIHISTORY);
HI = GPR[RS];
- HIACCESS = 3; /* 3rd instruction will be safe */
}
-000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
+
+000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- if (LOACCESS != 0)
- sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
+ check_mt_hilo (SD_, LOHISTORY);
LO = GPR[RS];
- LOACCESS = 3; /* 3rd instruction will be safe */
}
-000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
+
+:function:::void:do_mult:int rs, int rt, int rd
+{
+ signed64 prod;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = (((signed64)(signed32) GPR[rs])
+ * ((signed64)(signed32) GPR[rt]));
+ LO = EXTEND32 (VL4_8 (prod));
+ HI = EXTEND32 (VH4_8 (prod));
+ if (rd != 0)
+ GPR[rd] = LO;
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+{
+ do_mult (SD_, RS, RT, 0);
+}
+
+
+000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
+"mult r<RS>, r<RT>":RD == 0
+"mult r<RD>, r<RS>, r<RT>"
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- signed64 prod;
- CHECKHILO ("Multiplication");
- prod = (((signed64)(signed32) GPR[RS])
- * ((signed64)(signed32) GPR[RT]));
+ do_mult (SD_, RS, RT, RD);
+}
+
+
+:function:::void:do_multu:int rs, int rt, int rd
+{
+ unsigned64 prod;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = (((unsigned64)(unsigned32) GPR[rs])
+ * ((unsigned64)(unsigned32) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
+ if (rd != 0)
+ GPR[rd] = LO;
+ TRACE_ALU_RESULT2 (HI, LO);
}
-
-000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
+000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+{
+ do_multu (SD_, RS, RT, 0);
+}
+
+000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
+"multu r<RS>, r<RT>":RD == 0
+"multu r<RD>, r<RS>, r<RT>"
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned64 prod;
- CHECKHILO ("Multiplication");
- prod = (((unsigned64)(unsigned32) GPR[RS])
- * ((unsigned64)(unsigned32) GPR[RT]));
- LO = EXTEND32 (VL4_8 (prod));
- HI = EXTEND32 (VH4_8 (prod));
+ do_multu (SD_, RS, RT, RD);
}
+:function:::void:do_nor:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = ~ (GPR[rs] | GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = ~ (GPR[RS] | GPR[RT]);
+ do_nor (SD_, RS, RT, RD);
}
+:function:::void:do_or:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = (GPR[rs] | GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = (GPR[RS] | GPR[RT]);
+ do_or (SD_, RS, RT, RD);
}
+
+:function:::void:do_ori:int rs, int rt, unsigned immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], immediate);
+ GPR[rt] = (GPR[rs] | immediate);
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
"ori r<RT>, r<RS>, <IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RT] = (GPR[RS] | IMMEDIATE);
+ do_ori (SD_, RS, RT, IMMEDIATE);
}
110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
}
}
+:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ if ((vaddr & access) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ memval = (word << (8 * byte));
+ StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
+}
+
+
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
"scd r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
address_word paddr;
int uncached;
if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
"sd r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = op2;
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
}
101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
"sdl r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- memval = (op2 >> (8 * (7 - byte)));
- StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+{
+ do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
"sdr r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- memval = ((unsigned64) op2 << (byte * 8));
- StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
+ do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
-00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+:function:::void:do_sll:int rt, int rd, int shift
+{
+ unsigned32 temp = (GPR[rt] << shift);
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+"nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = SHIFT;
- unsigned32 temp = (GPR[RT] << s);
- GPR[RD] = EXTEND32 (temp);
+ /* Skip shift for NOP, so that there won't be lots of extraneous
+ trace output. */
+ if (RD != 0 || RT != 0 || SHIFT != 0)
+ do_sll (SD_, RT, RD, SHIFT);
}
-000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
+:function:::void:do_sllv:int rs, int rt, int rd
+{
+ int s = MASKED (GPR[rs], 4, 0);
+ unsigned32 temp = (GPR[rt] << s);
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = MASKED (GPR[RS], 4, 0);
- unsigned32 temp = (GPR[RT] << s);
- GPR[RD] = EXTEND32 (temp);
+ do_sllv (SD_, RS, RT, RD);
}
-000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
+:function:::void:do_slt:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = (GPR[RS] < GPR[RT]);
+ do_slt (SD_, RS, RT, RD);
}
+:function:::void:do_slti:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
"slti r<RT>, r<RS>, <IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE));
+ do_slti (SD_, RS, RT, IMMEDIATE);
}
+:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
+ do_sltiu (SD_, RS, RT, IMMEDIATE);
+}
+
+
+
+:function:::void:do_sltu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
+000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
+ do_sltu (SD_, RS, RT, RD);
}
+:function:::void:do_sra:int rt, int rd, int shift
+{
+ signed32 temp = (signed32) GPR[rt] >> shift;
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
"sra r<RD>, r<RT>, <SHIFT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = SHIFT;
- signed32 temp = (signed32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_sra (SD_, RT, RD, SHIFT);
}
-000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
+
+:function:::void:do_srav:int rs, int rt, int rd
+{
+ int s = MASKED (GPR[rs], 4, 0);
+ signed32 temp = (signed32) GPR[rt] >> s;
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = MASKED (GPR[RS], 4, 0);
- signed32 temp = (signed32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_srav (SD_, RS, RT, RD);
}
+
+:function:::void:do_srl:int rt, int rd, int shift
+{
+ unsigned32 temp = (unsigned32) GPR[rt] >> shift;
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
"srl r<RD>, r<RT>, <SHIFT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = SHIFT;
- unsigned32 temp = (unsigned32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_srl (SD_, RT, RD, SHIFT);
}
-000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
+:function:::void:do_srlv:int rs, int rt, int rd
+{
+ int s = MASKED (GPR[rs], 4, 0);
+ unsigned32 temp = (unsigned32) GPR[rt] >> s;
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = EXTEND32 (temp);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- int s = MASKED (GPR[RS], 4, 0);
- unsigned32 temp = (unsigned32) GPR[RT] >> s;
- GPR[RD] = EXTEND32 (temp);
+ do_srlv (SD_, RS, RT, RD);
}
-000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
+000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- ALU32_BEGIN (GPR[RS]);
- ALU32_SUB (GPR[RT]);
- ALU32_END (GPR[RD]);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ {
+ ALU32_BEGIN (GPR[RS]);
+ ALU32_SUB (GPR[RT]);
+ ALU32_END (GPR[RD]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[RD]);
}
-000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
+:function:::void:do_subu:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
+ do_subu (SD_, RS, RT, RD);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
+}
+
+
+
+:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ unsigned int word;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+ int nr_lhs_bits;
+ int nr_rhs_bits;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem == 0)
+ paddr = paddr & ~access;
+
+ /* compute where within the word/mem we are */
+ byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+ word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+ nr_lhs_bits = 8 * byte + 8;
+ nr_rhs_bits = 8 * access - 8 * byte;
+ /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+ /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+ (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+ (long) ((unsigned64) paddr >> 32), (long) paddr,
+ word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+ if (word == 0)
+ {
+ memval = (rt >> nr_rhs_bits);
+ }
+ else
+ {
+ memval = (rt << nr_lhs_bits);
+ }
+ /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
+ (long) ((unsigned64) rt >> 32), (long) rt,
+ (long) ((unsigned64) memval >> 32), (long) memval); */
+ StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- memval = (op2 >> (8 * (3 - byte)));
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval <<= 32;
- }
- StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
+ do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
+:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem != 0)
+ paddr &= ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ memval = (rt << (byte * 8));
+ StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
+}
+
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
"swr r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- memval = ((unsigned64) op2 << (byte * 8));
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval <<= 32;
- }
- StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
+ do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
-000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
+000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
"sync":STYPE == 0
"sync <STYPE>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
SyncOperation (STYPE);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
SignalException(SystemCall, instruction_0);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- if (GPR[RS] == GPR[RT])
+ if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- if (GPR[RS] == EXTEND16 (IMMEDIATE))
+ if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- if (GPR[RS] >= GPR[RT])
+ if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- if (GPR[RS] >= EXTEND16 (IMMEDIATE))
+ if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- if (GPR[RS] < GPR[RT])
+ if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- if (GPR[RS] < EXTEND16 (IMMEDIATE))
+ if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
SignalException(Trap, instruction_0);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- if (GPR[RS] != GPR[RT])
+ if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
SignalException(Trap, instruction_0);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*mipsV:
+*vr4100:
+*vr5000:
{
- if (GPR[RS] != EXTEND16 (IMMEDIATE))
+ if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
SignalException(Trap, instruction_0);
}
-000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
+:function:::void:do_xor:int rs, int rt, int rd
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ GPR[rd] = GPR[rs] ^ GPR[rt];
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RD] = GPR[RS] ^ GPR[RT];
+ do_xor (SD_, RS, RT, RD);
}
+:function:::void:do_xori:int rs, int rt, unsigned16 immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], immediate);
+ GPR[rt] = GPR[rs] ^ immediate;
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
"xori r<RT>, r<RS>, <IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- GPR[RT] = GPR[RS] ^ IMMEDIATE;
+ do_xori (SD_, RS, RT, IMMEDIATE);
}
\f
}
}
+:%s::::X:int x
+{
+ switch (x)
+ {
+ case 0: return "f";
+ case 1: return "t";
+ default: return "?";
+ }
+}
+
:%s::::TF:int tf
{
if (tf)
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
-
-010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
+010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
}
-//
-// FIXME: This does not correctly resolve mipsI-mipsIV differences.
-//
+
// BC1F
// BC1FL
// BC1T
// BC1TL
-010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
-"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
-"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
+
+010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
+"bc1%s<TF>%s<ND> <OFFSET>"
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
- int boolean = ((instruction >> 16) & 0x00000001);
- int likely = ((instruction >> 17) & 0x00000001);
- int condition_code = ((instruction >> 18) & 0x00000007);
- {
- if (condition_code != 0)
- SignalException(ReservedInstruction,instruction);
- else {
- int condition = (PREVCOC1() == boolean);
- /* NOTE: The branch occurs AFTER the next instruction has been executed */
- if (condition) {
- DELAY_SLOT (CIA + offset);
- }
- else if (likely) {
- NULLIFY_NEXT_INSTRUCTION ();
- }
+ check_branch_bug ();
+ TRACE_BRANCH_INPUT (PREVCOC1());
+ if (PREVCOC1() == TF)
+ {
+ address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
+ TRACE_BRANCH_RESULT (dest);
+ mark_branch_bug (dest);
+ DELAY_SLOT (dest);
+ }
+ else if (ND)
+ {
+ TRACE_BRANCH_RESULT (0);
+ NULLIFY_NEXT_INSTRUCTION ();
+ }
+ else
+ {
+ TRACE_BRANCH_RESULT (NIA);
}
- }
}
-
-//
-// FIXME: This does not correctly differentiate between mips*
-//
-010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
-"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
-"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
+010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
+"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
+"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+#*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int cmpflags = ((instruction >> 0) & 0x0000000F);
- int condition_code = ((instruction >> 8) & 0x00000007);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- if (condition_code != 0)
+ check_branch_bug ();
+ if (GETFCC(CC) == TF)
{
- SignalException(ReservedInstruction,instruction);
+ address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
+ mark_branch_bug (dest);
+ DELAY_SLOT (dest);
+ }
+ else if (ND)
+ {
+ NULLIFY_NEXT_INSTRUCTION ();
}
+}
+
+
+
+
+
+
+// C.EQ.S
+// C.EQ.D
+// ...
+
+:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
+{
+ if ((fmt != fmt_single) && (fmt != fmt_double))
+ SignalException (ReservedInstruction, insn);
else
{
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else {
- if (condition_code != 0)
- SignalException(ReservedInstruction,instruction);
- else
- {
- int ignore = 0;
- int less = 0;
- int equal = 0;
- int unordered = 1;
- unsigned64 ofs = ValueFPR(fs,format);
- unsigned64 oft = ValueFPR(ft,format);
- if (NaN(ofs,format) || NaN(oft,format)) {
- if (FCSR & FP_ENABLE(IO)) {
- FCSR |= FP_CAUSE(IO);
- SignalExceptionFPE();
- ignore = 1;
- }
- } else {
- less = Less(ofs,oft,format);
- equal = Equal(ofs,oft,format);
- unordered = 0;
- }
- if (!ignore) {
- int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
- SETFCC(condition_code,condition);
+ int less;
+ int equal;
+ int unordered;
+ int condition;
+ unsigned64 ofs = ValueFPR (fs, fmt);
+ unsigned64 oft = ValueFPR (ft, fmt);
+ if (NaN (ofs, fmt) || NaN (oft, fmt))
+ {
+ if (FCSR & FP_ENABLE (IO))
+ {
+ FCSR |= FP_CAUSE (IO);
+ SignalExceptionFPE ();
}
- }
- }
+ less = 0;
+ equal = 0;
+ unordered = 1;
+ }
+ else
+ {
+ less = Less (ofs, oft, fmt);
+ equal = Equal (ofs, oft, fmt);
+ unordered = 0;
+ }
+ condition = (((cond & (1 << 2)) && less)
+ || ((cond & (1 << 1)) && equal)
+ || ((cond & (1 << 0)) && unordered));
+ SETFCC (cc, condition);
}
}
+010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
+"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+ do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
+}
+
+010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
+"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
+"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
+}
+
010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
"ceil.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
// CFC1
// CTC1
-01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1
+010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
+"c%s<X>c1 r<RT>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
+{
+ if (X)
+ {
+ if (FS == 0)
+ PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
+ else if (FS == 31)
+ PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
+ /* else NOP */
+ PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
+ }
+ else
+ { /* control from */
+ if (FS == 0)
+ PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
+ else if (FS == 31)
+ PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
+ /* else NOP */
+ }
+}
+010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
+"c%s<X>c1 r<RT>, f<FS>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int to = ((instruction >> 23) & 0x00000001);
- {
- if (to) {
- if (fs == 0) {
- PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft]));
- } else if (fs == 31) {
- PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft]));
- } /* else NOP */
- PENDING_FILL(COCIDX,0); /* special case */
- } else { /* control from */
- if (fs == 0) {
- PENDING_FILL(ft,SIGNEXTEND(FCR0,32));
- } else if (fs == 31) {
- PENDING_FILL(ft,SIGNEXTEND(FCR31,32));
- } /* else NOP */
+ if (X)
+ {
+ /* control to */
+ TRACE_ALU_INPUT1 (GPR[RT]);
+ if (FS == 0)
+ {
+ FCR0 = VL4_8(GPR[RT]);
+ TRACE_ALU_RESULT (FCR0);
+ }
+ else if (FS == 31)
+ {
+ FCR31 = VL4_8(GPR[RT]);
+ SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
+ TRACE_ALU_RESULT (FCR31);
+ }
+ else
+ {
+ TRACE_ALU_RESULT0 ();
+ }
+ /* else NOP */
+ }
+ else
+ { /* control from */
+ if (FS == 0)
+ {
+ TRACE_ALU_INPUT1 (FCR0);
+ GPR[RT] = SIGNEXTEND (FCR0, 32);
+ }
+ else if (FS == 31)
+ {
+ TRACE_ALU_INPUT1 (FCR31);
+ GPR[RT] = SIGNEXTEND (FCR31, 32);
+ }
+ TRACE_ALU_RESULT (GPR[RT]);
+ /* else NOP */
}
- }
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"cvt.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
// DMFC1
// DMTC1
-01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1
+010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
+"dm%s<X>c1 r<RT>, f<FS>"
*mipsIII:
+{
+ if (X)
+ {
+ if (SizeFGR() == 64)
+ PENDING_FILL((FS + FGRIDX),GPR[RT]);
+ else if ((FS & 0x1) == 0)
+ {
+ PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
+ PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
+ }
+ }
+ else
+ {
+ if (SizeFGR() == 64)
+ PENDING_FILL(RT,FGR[FS]);
+ else if ((FS & 0x1) == 0)
+ PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
+ else
+ {
+ if (STATE_VERBOSE_P(SD))
+ sim_io_eprintf (SD,
+ "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
+ (long) CIA);
+ PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
+ }
+ }
+}
+010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
+"dm%s<X>c1 r<RT>, f<FS>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int to = ((instruction >> 23) & 0x00000001);
- {
- if (to) {
- if (SizeFGR() == 64) {
- PENDING_FILL((fs + FGRIDX),GPR[ft]);
- } else
- if ((fs & 0x1) == 0)
- {
- PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft]));
- PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft]));
- }
- } else {
- if (SizeFGR() == 64) {
- PENDING_FILL(ft,FGR[fs]);
- } else
- if ((fs & 0x1) == 0) {
- PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs]));
- } else {
- PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
+ if (X)
+ {
+ if (SizeFGR() == 64)
+ StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+ else if ((FS & 0x1) == 0)
+ StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
+ }
+ else
+ {
+ if (SizeFGR() == 64)
+ GPR[RT] = FGR[FS];
+ else if ((FS & 0x1) == 0)
+ GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
+ else
+ {
+ if (STATE_VERBOSE_P(SD))
+ sim_io_eprintf (SD,
+ "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
+ (long) CIA);
+ GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
}
}
- }
}
"floor.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
}
-// LDC1
-110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1
+110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
+"ldc1 f<FT>, <OFFSET>(r<BASE>)"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
+}
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + op2);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- COP_LD(1,destreg,memval);;
- }
- }
- }
+ COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
}
-// LWC1
-110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
+
+110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
+"lwc1 f<FT>, <OFFSET>(r<BASE>)"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
+}
010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + op2);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
}
//
// FIXME: Not correct for mips*
//
-010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
+010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
}
-010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
+010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
// MFC1
-010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
-"m<X>c1 r<RT>, f<FS>"
+// MTC1
+010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
+"m%s<X>c1 r<RT>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
+{
+ if (X)
+ { /*MTC1*/
+ if (SizeFGR() == 64)
+ {
+ if (STATE_VERBOSE_P(SD))
+ sim_io_eprintf (SD,
+ "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
+ (long) CIA);
+ PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
+ }
+ else
+ PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
+ }
+ else /*MFC1*/
+ PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
+}
+010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
+"m%s<X>c1 r<RT>, f<FS>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int to = ((instruction >> 23) & 0x00000001);
- {
- if (to) {
- if (SizeFGR() == 64) {
- PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft])));
- } else {
- PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft]));
- }
- } else {
- PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32));
- }
- }
+ int fs = FS;
+ if (X)
+ /*MTC1*/
+ StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
+ else /*MFC1*/
+ GPR[RT] = SIGNEXTEND(FGR[FS],32);
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
// MOVF
-000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
+// MOVT
+000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32::MOVtf
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
if (GETFCC(CC) == TF)
GPR[RD] = GPR[RS];
// MOVF.fmt
+// MOVT.fmt
010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int format = ((instruction >> 21) & 0x00000007);
010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
+"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- {
- StoreFPR(destreg,format,ValueFPR(fs,format));
- }
+ if (GPR[RT] != 0)
+ StoreFPR (FD, FMT, ValueFPR (FS, FMT));
+ else
+ StoreFPR (FD, FMT, ValueFPR (FD, FMT));
}
010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- {
- StoreFPR(destreg,format,ValueFPR(fs,format));
- }
+ if (GPR[RT] == 0)
+ StoreFPR (FD, FMT, ValueFPR (FS, FMT));
+ else
+ StoreFPR (FD, FMT, ValueFPR (FD, FMT));
}
010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
{
- StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
+ StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
}
}
010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
{
- StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
+ StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
}
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
}
010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
-*mipsIV:
"recip.%s<FMT> f<FD>, f<FS>"
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*mipsIV:
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
"round.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
*mipsIV:
+*mipsV:
"rsqrt.%s<FMT> f<FD>, f<FS>"
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
}
-// SDC1
+111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
+"sdc1 f<FT>, <OFFSET>(r<BASE>)"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
+}
-010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
+010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
+"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
- unsigned32 instruction = instruction_0;
- int fs = ((instruction >> 11) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + op2);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = (unsigned64)COP_SD(1,fs);
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
}
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
}
-// SWC1
+
+111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
+"swc1 f<FT>, <OFFSET>(r<BASE>)"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ unsigned32 instruction = instruction_0;
+ signed_word offset = EXTEND16 (OFFSET);
+ int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
+ signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
+ {
+ address_word vaddr = ((uword64)op1 + offset);
+ address_word paddr;
+ int uncached;
+ if ((vaddr & 3) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
+ else
+ {
+ if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
+ {
+ uword64 memval = 0;
+ uword64 memval1 = 0;
+ uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
+ address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
+ unsigned int byte;
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
+ StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
+ }
+ }
+ }
+}
010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
+ }
else
{
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
"trunc.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
+
+010000,01000,00000,16.OFFSET:COP0:32::BC0F
+"bc0f <OFFSET>"
+// stub needed for eCos as tx39 hardware bug workaround
+*r3900:
+{
+ /* do nothing */
+}
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
010000,01000,00001,16.OFFSET:COP0:32::BC0T
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-
+*mipsV:
+*vr4100:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
}
-010000,10000,000000000000000,111001:COP0:32::DI
+010000,1,0000000000000000000,111001:COP0:32::DI
"di"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
+
+
+010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
+"dmfc0 r<RT>, r<RD>"
+*mipsIII:
+*mipsIV:
+*mipsV:
+{
+ DecodeCoproc (instruction_0);
+}
+
+
+010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
+"dmtc0 r<RT>, r<RD>"
+*mipsIII:
+*mipsIV:
+*mipsV:
+{
+ DecodeCoproc (instruction_0);
+}
-010000,10000,000000000000000,111000:COP0:32::EI
+010000,1,0000000000000000000,111000:COP0:32::EI
"ei"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
-010000,10000,000000000000000,011000:COP0:32::ERET
+010000,1,0000000000000000000,011000:COP0:32::ERET
"eret"
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
+{
+ if (SR & status_ERL)
+ {
+ /* Oops, not yet available */
+ sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
+ NIA = EPC;
+ SR &= ~status_ERL;
+ }
+ else
+ {
+ NIA = EPC;
+ SR &= ~status_EXL;
+ }
+}
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ TRACE_ALU_INPUT0 ();
+ DecodeCoproc (instruction_0);
+ TRACE_ALU_RESULT (GPR[RT]);
+}
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ DecodeCoproc (instruction_0);
+}
+
+
+010000,1,0000000000000000000,010000:COP0:32::RFE
+"rfe"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ DecodeCoproc (instruction_0);
+}
+
+
+0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
+"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*r3900:
+{
+ DecodeCoproc (instruction_0);
+}
+
-010000,10000,000000000000000,001000:COP0:32::TLBP
+010000,1,0000000000000000000,001000:COP0:32::TLBP
"tlbp"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
-010000,10000,000000000000000,000001:COP0:32::TLBR
+010000,1,0000000000000000000,000001:COP0:32::TLBR
"tlbr"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
-010000,10000,000000000000000,000010:COP0:32::TLBWI
+010000,1,0000000000000000000,000010:COP0:32::TLBWI
"tlbwi"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
-010000,10000,000000000000000,000110:COP0:32::TLBWR
+010000,1,0000000000000000000,000110:COP0:32::TLBWR
"tlbwr"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+*mipsV:
+*vr4100:
+*vr5000:
\f
:include:::m16.igen
-// start-sanitize-vr5400
-:include::vr5400:vr5400.igen
-// end-sanitize-vr5400
-// start-sanitize-r5900
-:include::r5900:r5900.igen
-// end-sanitize-r5900
+:include:::tx.igen
+:include:::vr.igen
\f
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME What is this instruction?
-// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
-// *mipsI:
-// *mipsII:
-// *mipsIII:
-// *mipsIV:
-// // start-sanitize-r5900
-// *r5900:
-// // end-sanitize-r5900
-// *r3900:
-// // start-sanitize-tx19
-// *tx19:
-// // end-sanitize-tx19
-// {
-// unsigned32 instruction = instruction_0;
-// signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-// {
-// if (CoProcPresent(3))
-// SignalException(CoProcessorUnusable);
-// else
-// SignalException(ReservedInstruction,instruction);
-// }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME What is this?
-// 11100,******,00001:RR:16::SDBBP
-// *mips16:
-// {
-// unsigned32 instruction = instruction_0;
-// if (have_extendval)
-// SignalException (ReservedInstruction, instruction);
-// {
-// SignalException(DebugBreakPoint,instruction);
-// }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME What is this?
-// 000000,********************,001110:SPECIAL:32::SDBBP
-// *r3900:
-// {
-// unsigned32 instruction = instruction_0;
-// {
-// SignalException(DebugBreakPoint,instruction);
-// }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
-// // isn't yet reconized by this simulator.
-// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
-// *vr4100:
-// {
-// unsigned32 instruction = instruction_0;
-// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-// {
-// CHECKHILO("Multiply-Add");
-// {
-// unsigned64 temp = (op1 * op2);
-// temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
-// LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
-// HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
-// }
-// }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
-// // isn't yet reconized by this simulator.
-// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
-// *vr4100:
-// {
-// unsigned32 instruction = instruction_0;
-// signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-// signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-// {
-// CHECKHILO("Multiply-Add");
-// {
-// unsigned64 temp = (op1 * op2);
-// LO = LO + temp;
-// }
-// }
-// }
-
-// start-sanitize-cygnus-never
projects / deliverable / binutils-gdb.git / blobdiff