// Models known by this simulator
-:model:::mipsI:mipsI:
-:model:::mipsII:mipsII:
-:model:::mipsIII:mipsIII:
-:model:::mipsIV:mipsIV:
+:model:::mipsI:mips3000:
+:model:::mipsII:mips6000:
+:model:::mipsIII:mips4000:
+:model:::mipsIV:mips8000:
:model:::mips16:mips16:
// start-sanitize-r5900
:model:::r5900:mips5900:
// start-sanitize-tx19
:model:::tx19:tx19:
// end-sanitize-tx19
+// start-sanitize-vr4320
+:model:::vr4320:mips4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
:model:::vr5400:mips5400:
:model:::mdmx:mdmx:
"add r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"addi r<RT>, r<RS>, IMMEDIATE"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"add r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"and r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"and r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"beq r<RS>, r<RT>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bgez r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bgezal r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bgtz r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"blez r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bltz r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bltzal r<RS>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bne r<RS>, r<RT>, <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"break"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIV:
*r3900:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"div r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"divu r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
{
do_dmult (SD_, RS, RT, 0, 1);
}
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
{
do_dmult (SD_, RS, RT, 0, 0);
}
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"j <INSTR_INDEX>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"jal <INSTR_INDEX>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"jalr r<RD>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"jr r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lb r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lbu r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
// start-sanitize-tx19
*tx19:
}
+// start-sanitize-sky
+110110,5.BASE,5.RT,16.OFFSET:NORMAL:64::LQC2
+"lqc2 r<RT>, <OFFSET>(r<BASE>)"
+*r5900:
+{
+ unsigned32 instruction = instruction_0;
+ signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
+ int destreg = ((instruction >> 16) & 0x0000001F);
+ signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ {
+ address_word vaddr = ((unsigned64)op1 + offset);
+ address_word paddr;
+ int uncached;
+ if ((vaddr & 0x0f) != 0)
+ SignalExceptionAddressLoad();
+ else
+ {
+ if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
+ {
+ unsigned64 memval = 0;
+ unsigned64 memval1 = 0;
+ unsigned128 qw = U16_8(memval, memval1); /* XXX: check order */
+ /* XXX: block on VU0 pipeline if necessary */
+ LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
+ COP_LQ(((instruction >> 26) & 0x3),destreg,qw);;
+ }
+ }
+ }
+}
+// end-sanitize-sky
+
+
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
"ldl r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lh r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lhu r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lui r<RT>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lw r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lwl r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lwr r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mfhi r<RD>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mflo r<RD>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mthi r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mtlo r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
{
signed64 prod;
CHECKHILO ("Multiplication");
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
}
+
+
000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
"mult r<RD>, r<RS>, r<RT>"
*vr5000:
000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
{
unsigned64 prod;
CHECKHILO ("Multiplication");
"nor r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"or r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"ori r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sb r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
}
+// start-sanitize-sky
+111010,5.BASE,5.RT,16.OFFSET:NORMAL:64::SQC2
+"sqc2 r<RT>, <OFFSET>(r<BASE>)"
+*r5900:
+{
+ unsigned32 instruction = instruction_0;
+ signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
+ int destreg = ((instruction >> 16) & 0x0000001F);
+ signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ {
+ address_word vaddr = ((unsigned64)op1 + offset);
+ address_word paddr;
+ int uncached;
+ if ((vaddr & 0x0f) != 0)
+ SignalExceptionAddressStore();
+ else
+ {
+ if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
+ {
+ unsigned128 qw;
+ unsigned64 memval0 = 0;
+ unsigned64 memval1 = 0;
+ qw = COP_SQ(((instruction >> 26) & 0x3),destreg);
+ memval0 = *A8_16(& qw, 0);
+ memval1 = *A8_16(& qw, 1);
+ {
+ StoreMemory(uncached,AccessLength_WORD,memval0,memval1,paddr,vaddr,isREAL);
+ }
+ }
+ }
+ }
+}
+// end-sanitize-sky
+
+
+
101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
"sdl r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sh r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sllv r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"slt r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"slti r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sltu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sra r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"srav r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"srl r<RD>, r<RT>, <SHIFT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"srlv r<RD>, r<RT>, r<RS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sub r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"subu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sw r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
*r3900:
// start-sanitize-tx19
*tx19:
"swl r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"swr r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"syscall <CODE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"xor r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"xori r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"abs.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"c%s<X>c1 r<RT>, f<FS>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"cvt.d.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"cvt.s.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"cvt.w.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"dm%s<X>c1 r<RT>, f<FS>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"m%s<X>c1 r<RT>, f<FS>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mov.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"neg.%s<FMT> f<FD>, f<FS>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIV:
"recip.%s<FMT> f<FD>, f<FS>"
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIV:
"rsqrt.%s<FMT> f<FD>, f<FS>"
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
}
-
010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"swc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bc0f <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bc0fl <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"bc0tl <OFFSET>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"di"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"ei"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
*mipsIII:
*mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mfc0 r<RT>, r<RD> # <REGX>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"mtc0 r<RT>, r<RD> # <REGX>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"tlbp"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"tlbr"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"tlbwi"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
"tlbwr"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
\f
:include:16::m16.igen
+// start-sanitize-vr4320
+:include::vr4320:vr4320.igen
+// end-sanitize-vr4320
// start-sanitize-vr5400
:include::vr5400:vr5400.igen
:include:64,f::mdmx.igen