// :option:::multi-sim:true
-// Models known by this simulator
+// Models known by this simulator are defined below.
+//
+// When placing models in the instruction descriptions, please place
+// them one per line, in the order given here.
+
+// MIPS ISAs:
+//
+// Instructions and related functions for these models are included in
+// this file.
:model:::mipsI:mips3000:
:model:::mipsII:mips6000:
:model:::mipsIII:mips4000:
:model:::mipsIV:mips8000:
-:model:::mips16:mips16:
-:model:::r3900:mips3900:
-:model:::vr4100:mips4100:
+:model:::mipsV:mipsisaV:
+
+// Vendor ISAs:
+//
+// Standard MIPS ISA instructions used for these models are listed here,
+// as are functions needed by those standard instructions. Instructions
+// which are model-dependent and which are not in the standard MIPS ISAs
+// (or which pre-date or use different encodings than the standard
+// instructions) are (for the most part) in separate .igen files.
+:model:::vr4100:mips4100: // vr.igen
:model:::vr5000:mips5000:
+:model:::r3900:mips3900: // tx.igen
+// MIPS Application Specific Extensions (ASEs)
+//
+// Instructions for the ASEs are in separate .igen files.
+:model:::mips16:mips16: // m16.igen (and m16.dc)
// Pseudo instructions known by IGEN
}
:function:::int:check_mt_hilo:hilo_history *history
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
+// Helper:
+//
+// Check that the 64-bit instruction can currently be used, and signal
+// an ReservedInstruction exception if not.
+//
+
+:function:::void:check_u64:instruction_word insn
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+{
+ // On mips64, if UserMode check SR:PX & SR:UX bits.
+ // The check should be similar to mips64 for any with PX/UX bit equivalents.
+}
//
-// Mips Architecture:
+// MIPS Architecture:
//
-// CPU Instruction Set (mipsI - mipsIV)
+// CPU Instruction Set (mipsI - mipsV)
//
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
ALU32_BEGIN (GPR[RS]);
ALU32_ADD (GPR[RT]);
- ALU32_END (GPR[RD]);
+ ALU32_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
"addi r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
ALU32_BEGIN (GPR[RS]);
ALU32_ADD (EXTEND16 (IMMEDIATE));
- ALU32_END (GPR[RT]);
+ ALU32_END (GPR[RT]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RT]);
}
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
"addiu r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
"addu r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
"and r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
"and r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
"beq r<RS>, r<RT>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
"bgez r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
"bgezal r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
"bgtz r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
"blez r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
"bltz r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
"bltzal r<RS>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
"bne r<RS>, r<RT>, <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000000,20.CODE,001101:SPECIAL:32::BREAK
"break <CODE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
"dadd r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
- /* this check's for overflow */
+ check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU64_BEGIN (GPR[RS]);
ALU64_ADD (GPR[RT]);
- ALU64_END (GPR[RD]);
+ ALU64_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
"daddi r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
{
ALU64_BEGIN (GPR[RS]);
ALU64_ADD (EXTEND16 (IMMEDIATE));
- ALU64_END (GPR[RT]);
+ ALU64_END (GPR[RT]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RT]);
}
"daddiu r<RT>, r<RS>, <IMMEDIATE>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_daddiu (SD_, RS, RT, IMMEDIATE);
}
"daddu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_daddu (SD_, RS, RT, RD);
}
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
+000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
"ddiv r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_ddiv (SD_, RS, RT);
}
"ddivu r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_ddivu (SD_, RS, RT);
}
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
+000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
+000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
do_dmultx (SD_, rs, rt, rd, 1);
}
-000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
+000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
-*mipsIII,mipsIV:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
{
+ check_u64 (SD_, instruction_0);
do_dmult (SD_, RS, RT, 0);
}
-000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
+000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>":RD == 0
"dmult r<RD>, r<RS>, r<RT>"
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dmult (SD_, RS, RT, RD);
}
do_dmultx (SD_, rs, rt, rd, 0);
}
-000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
+000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
-*mipsIII,mipsIV:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
{
+ check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, 0);
}
-000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
+000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
"dmultu r<RD>, r<RS>, r<RT>":RD == 0
"dmultu r<RS>, r<RT>"
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, RD);
}
}
-00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
+000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsll (SD_, RT, RD, SHIFT);
}
-00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
+000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
"dsll32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
int s = 32 + SHIFT;
+ check_u64 (SD_, instruction_0);
GPR[RD] = GPR[RT] << s;
}
-000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
+000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsllv (SD_, RS, RT, RD);
}
}
-00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
+000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsra (SD_, RT, RD, SHIFT);
}
-00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
+000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
"dsra32 r<RT>, r<RD>, <SHIFT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
int s = 32 + SHIFT;
+ check_u64 (SD_, instruction_0);
GPR[RD] = ((signed64) GPR[RT]) >> s;
}
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
+000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
"dsrav r<RT>, r<RD>, r<RS>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsrav (SD_, RS, RT, RD);
}
}
-00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
+000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsrl (SD_, RT, RD, SHIFT);
}
-00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
+000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
"dsrl32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
int s = 32 + SHIFT;
+ check_u64 (SD_, instruction_0);
GPR[RD] = (unsigned64) GPR[RT] >> s;
}
-000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
+000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
"dsrlv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsrlv (SD_, RS, RT, RD);
}
-000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
+000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
"dsub r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU64_BEGIN (GPR[RS]);
ALU64_SUB (GPR[RT]);
- ALU64_END (GPR[RD]);
+ ALU64_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
+000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsubu (SD_, RS, RT, RD);
}
000010,26.INSTR_INDEX:NORMAL:32::J
"j <INSTR_INDEX>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000011,26.INSTR_INDEX:NORMAL:32::JAL
"jal <INSTR_INDEX>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
-000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
+000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
-000000,5.RS,000000000000000001000:SPECIAL:32::JR
+000000,5.RS,000000000000000,001000:SPECIAL:32::JR
"jr r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
return (memval >> (8 * byte));
}
+:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ unsigned int word;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+ int nr_lhs_bits;
+ int nr_rhs_bits;
+ unsigned_word lhs_mask;
+ unsigned_word temp;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem == 0)
+ paddr = paddr & ~access;
+
+ /* compute where within the word/mem we are */
+ byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+ word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+ nr_lhs_bits = 8 * byte + 8;
+ nr_rhs_bits = 8 * access - 8 * byte;
+ /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+
+ /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+ (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+ (long) ((unsigned64) paddr >> 32), (long) paddr,
+ word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+ LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
+ if (word == 0)
+ {
+ /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
+ temp = (memval << nr_rhs_bits);
+ }
+ else
+ {
+ /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
+ temp = (memval >> nr_lhs_bits);
+ }
+ lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
+ rt = (rt & ~lhs_mask) | (temp & lhs_mask);
+
+ /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
+ (long) ((unsigned64) memval >> 32), (long) memval,
+ (long) ((unsigned64) temp >> 32), (long) temp,
+ (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
+ (long) (rt >> 32), (long) rt); */
+ return rt;
+}
+
+:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem != 0)
+ paddr = paddr & ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
+ LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
+ /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
+ (long) paddr, byte, (long) paddr, (long) memval); */
+ {
+ unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
+ rt &= ~screen;
+ rt |= (memval >> (8 * byte)) & screen;
+ }
+ return rt;
+}
+
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
"lbu r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
"ld r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
"ldl r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
"ldr r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
"lh r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
"lhu r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
"lld r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
int destreg = ((instruction >> 16) & 0x0000001F);
signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ check_u64 (SD_, instruction_0);
{
address_word vaddr = ((unsigned64)op1 + offset);
address_word paddr;
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
"lui r<RT>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
"lw r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
-:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
-{
- address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
- address_word reverseendian = (ReverseEndian ? -1 : 0);
- address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
- unsigned int byte;
- unsigned int word;
- address_word paddr;
- int uncached;
- unsigned64 memval;
- address_word vaddr;
- int nr_lhs_bits;
- int nr_rhs_bits;
- unsigned_word lhs_mask;
- unsigned_word temp;
-
- vaddr = base + offset;
- AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
- paddr = (paddr ^ (reverseendian & mask));
- if (BigEndianMem == 0)
- paddr = paddr & ~access;
-
- /* compute where within the word/mem we are */
- byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
- word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
- nr_lhs_bits = 8 * byte + 8;
- nr_rhs_bits = 8 * access - 8 * byte;
- /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
-
- /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
- (long) ((unsigned64) vaddr >> 32), (long) vaddr,
- (long) ((unsigned64) paddr >> 32), (long) paddr,
- word, byte, nr_lhs_bits, nr_rhs_bits); */
-
- LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
- if (word == 0)
- {
- /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
- temp = (memval << nr_rhs_bits);
- }
- else
- {
- /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
- temp = (memval >> nr_lhs_bits);
- }
- lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
- rt = (rt & ~lhs_mask) | (temp & lhs_mask);
-
- /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
- (long) ((unsigned64) memval >> 32), (long) memval,
- (long) ((unsigned64) temp >> 32), (long) temp,
- (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
- (long) (rt >> 32), (long) rt); */
- return rt;
-}
-
-
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
"lwl r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
-:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
-{
- address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
- address_word reverseendian = (ReverseEndian ? -1 : 0);
- address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
- unsigned int byte;
- address_word paddr;
- int uncached;
- unsigned64 memval;
- address_word vaddr;
-
- vaddr = base + offset;
- AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
- /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
- paddr = (paddr ^ (reverseendian & mask));
- if (BigEndianMem != 0)
- paddr = paddr & ~access;
- byte = ((vaddr & mask) ^ (bigendiancpu & mask));
- /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
- LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
- /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
- (long) paddr, byte, (long) paddr, (long) memval); */
- {
- unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
- rt &= ~screen;
- rt |= (memval >> (8 * byte)) & screen;
- }
- return rt;
-}
-
-
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
"lwr r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
"lwu r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
}
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
"mfhi r<RD>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
"mflo r<RD>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
-000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
+000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
+*mipsV:
*vr5000:
{
if (GPR[RT] != 0)
-000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
+000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
+*mipsV:
*vr5000:
{
if (GPR[RT] == 0)
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
-000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
+000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
+000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
}
-000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
+000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":RD == 0
"mult r<RD>, r<RS>, r<RT>"
*vr5000:
TRACE_ALU_RESULT2 (HI, LO);
}
-000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
+000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
}
-000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
+000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":RD == 0
"multu r<RD>, r<RS>, r<RT>"
*vr5000:
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
"nor r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
"or r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
"ori r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
}
}
+
:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
{
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
}
+:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ unsigned int word;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+ int nr_lhs_bits;
+ int nr_rhs_bits;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem == 0)
+ paddr = paddr & ~access;
+
+ /* compute where within the word/mem we are */
+ byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+ word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+ nr_lhs_bits = 8 * byte + 8;
+ nr_rhs_bits = 8 * access - 8 * byte;
+ /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+ /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+ (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+ (long) ((unsigned64) paddr >> 32), (long) paddr,
+ word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+ if (word == 0)
+ {
+ memval = (rt >> nr_rhs_bits);
+ }
+ else
+ {
+ memval = (rt << nr_lhs_bits);
+ }
+ /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
+ (long) ((unsigned64) rt >> 32), (long) rt,
+ (long) ((unsigned64) memval >> 32), (long) memval); */
+ StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
+}
+
+:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem != 0)
+ paddr &= ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ memval = (rt << (byte * 8));
+ StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
+}
+
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
"scd r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ check_u64 (SD_, instruction_0);
{
address_word vaddr = ((unsigned64)op1 + offset);
address_word paddr;
"sd r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
"sdl r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
"sdr r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT (GPR[rd]);
}
-00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
+000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
+000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
"slti r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
+000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
"sra r<RD>, r<RT>, <SHIFT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
+000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
"srl r<RD>, r<RT>, <SHIFT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
+000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
-000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
+000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
ALU32_BEGIN (GPR[RS]);
ALU32_SUB (GPR[RT]);
- ALU32_END (GPR[RD]);
+ ALU32_END (GPR[RD]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[RD]);
}
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
+000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
"sw r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*r3900:
*vr5000:
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
-
-:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
-{
- address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
- address_word reverseendian = (ReverseEndian ? -1 : 0);
- address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
- unsigned int byte;
- unsigned int word;
- address_word paddr;
- int uncached;
- unsigned64 memval;
- address_word vaddr;
- int nr_lhs_bits;
- int nr_rhs_bits;
-
- vaddr = base + offset;
- AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
- paddr = (paddr ^ (reverseendian & mask));
- if (BigEndianMem == 0)
- paddr = paddr & ~access;
-
- /* compute where within the word/mem we are */
- byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
- word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
- nr_lhs_bits = 8 * byte + 8;
- nr_rhs_bits = 8 * access - 8 * byte;
- /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
- /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
- (long) ((unsigned64) vaddr >> 32), (long) vaddr,
- (long) ((unsigned64) paddr >> 32), (long) paddr,
- word, byte, nr_lhs_bits, nr_rhs_bits); */
-
- if (word == 0)
- {
- memval = (rt >> nr_rhs_bits);
- }
- else
- {
- memval = (rt << nr_lhs_bits);
- }
- /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
- (long) ((unsigned64) rt >> 32), (long) rt,
- (long) ((unsigned64) memval >> 32), (long) memval); */
- StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
-}
-
-
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
"swl r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
-:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
-{
- address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
- address_word reverseendian = (ReverseEndian ? -1 : 0);
- address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
- unsigned int byte;
- address_word paddr;
- int uncached;
- unsigned64 memval;
- address_word vaddr;
-
- vaddr = base + offset;
- AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
- paddr = (paddr ^ (reverseendian & mask));
- if (BigEndianMem != 0)
- paddr &= ~access;
- byte = ((vaddr & mask) ^ (bigendiancpu & mask));
- memval = (rt << (byte * 8));
- StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
-}
-
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
"swr r<RT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
-000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
+000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
"sync":STYPE == 0
"sync <STYPE>"
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
000000,20.CODE,001100:SPECIAL:32::SYSCALL
"syscall <CODE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
+000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
"xori r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
}
+// Helper:
+//
+// Check that the FPU is currently usable, and signal a CoProcessorUnusable
+// exception if not.
+//
+
+:function:::void:check_fpu:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+#if 0 /* XXX FIXME: For now, never treat the FPU as disabled. */
+ if (! COP_Usable (1))
+ SignalExceptionCoProcessorUnusable (1);
+#endif
+}
+
010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
"abs.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction, instruction);
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
"bc1%s<TF>%s<ND> <OFFSET>"
-*mipsI,mipsII,mipsIII:
+*mipsI:
+*mipsII:
+*mipsIII:
{
+ check_fpu(SD_);
check_branch_bug ();
TRACE_BRANCH_INPUT (PREVCOC1());
if (PREVCOC1() == TF)
"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV:
-*vr5000:
+*mipsV:
#*vr4100:
+*vr5000:
*r3900:
{
+ check_fpu(SD_);
check_branch_bug ();
if (GETFCC(CC) == TF)
{
010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII:
+*mipsI:
+*mipsII:
+*mipsIII:
{
+ check_fpu(SD_);
do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
}
"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
+ check_fpu(SD_);
do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
}
"ceil.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
*mipsII:
*mipsIII:
{
+ check_fpu(SD_);
if (X)
{
if (FS == 0)
010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
"c%s<X>c1 r<RT>, f<FS>"
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
+ check_fpu(SD_);
if (X)
{
/* control to */
//
010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format == fmt_double) | 0)
SignalException(ReservedInstruction,instruction);
"cvt.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
SignalException(ReservedInstruction,instruction);
//
010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
"cvt.s.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format == fmt_single) | 0)
SignalException(ReservedInstruction,instruction);
010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
"cvt.w.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
SignalException(ReservedInstruction,instruction);
010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
"dm%s<X>c1 r<RT>, f<FS>"
*mipsIII:
{
+ check_fpu(SD_);
+ check_u64 (SD_, instruction_0);
if (X)
{
if (SizeFGR() == 64)
010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
"dm%s<X>c1 r<RT>, f<FS>"
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
+ check_fpu(SD_);
+ check_u64 (SD_, instruction_0);
if (X)
{
if (SizeFGR() == 64)
"floor.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
+ check_fpu(SD_);
COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
+*mipsV:
*vr5000:
{
+ check_fpu(SD_);
+ check_u64 (SD_, instruction_0);
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
}
110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
+ check_fpu(SD_);
COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
+*mipsV:
*vr5000:
{
+ check_fpu(SD_);
+ check_u64 (SD_, instruction_0);
COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
}
010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
+ check_fpu(SD_);
{
StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
}
010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
+ check_fpu(SD_);
{
StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
}
*mipsII:
*mipsIII:
{
+ check_fpu(SD_);
if (X)
{ /*MTC1*/
if (SizeFGR() == 64)
010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
"m%s<X>c1 r<RT>, f<FS>"
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
int fs = FS;
+ check_fpu(SD_);
if (X)
/*MTC1*/
StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
StoreFPR(destreg,format,ValueFPR(fs,format));
}
// MOVF
// MOVT
-000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
+000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32::MOVtf
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
+*mipsV:
*vr5000:
{
+ check_fpu(SD_);
if (GETFCC(CC) == TF)
GPR[RD] = GPR[RS];
}
010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if (GETFCC(CC) == TF)
StoreFPR (FD, format, ValueFPR (FS, format));
010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
+*mipsV:
*vr5000:
{
+ check_fpu(SD_);
if (GPR[RT] != 0)
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
else
010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
+*mipsV:
*vr5000:
{
+ check_fpu(SD_);
if (GPR[RT] == 0)
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
else
010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
+ check_fpu(SD_);
{
StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
}
010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
+ check_fpu(SD_);
{
StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
}
010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
+ check_fpu(SD_);
{
StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
}
010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
+ check_fpu(SD_);
{
StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
}
010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
+ check_fpu(SD_);
{
StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
}
010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int fr = ((instruction >> 21) & 0x0000001F);
+ check_fpu(SD_);
{
StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
}
010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
"recip.%s<FMT> f<FD>, f<FS>"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
"round.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
*mipsIV:
+*mipsV:
"rsqrt.%s<FMT> f<FD>, f<FS>"
*vr5000:
{
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
{
+ check_fpu(SD_);
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
}
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
+*mipsV:
*vr5000:
{
+ check_fpu(SD_);
+ check_u64 (SD_, instruction_0);
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
}
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int fs = ((instruction >> 11) & 0x0000001F);
int ft = ((instruction >> 16) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
"swc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
signed_word offset = EXTEND16 (OFFSET);
int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
+ check_fpu(SD_);
{
address_word vaddr = ((uword64)op1 + offset);
address_word paddr;
010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
+*mipsV:
*vr5000:
{
unsigned32 instruction = instruction_0;
int fs = ((instruction >> 11) & 0x0000001F);
signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ check_fpu(SD_);
+ check_u64 (SD_, instruction_0);
{
address_word vaddr = ((unsigned64)op1 + op2);
address_word paddr;
"trunc.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
*mipsII:
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
int destreg = ((instruction >> 6) & 0x0000001F);
int fs = ((instruction >> 11) & 0x0000001F);
int format = ((instruction >> 21) & 0x00000007);
+ check_fpu(SD_);
{
if ((format != fmt_single) && (format != fmt_double))
SignalException(ReservedInstruction,instruction);
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
"bc0fl <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
010000,01000,00001,16.OFFSET:COP0:32::BC0T
"bc0t <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
"bc0tl <OFFSET>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
*r3900:
}
-010000,10000,000000000000000,111001:COP0:32::DI
+010000,1,0000000000000000000,111001:COP0:32::DI
"di"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
-010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
+010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
-*mipsIII,mipsIV:
+*mipsIII:
+*mipsIV:
+*mipsV:
{
+ check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
}
-010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
+010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
-*mipsIII,mipsIV:
+*mipsIII:
+*mipsIV:
+*mipsV:
{
+ check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
}
-010000,10000,000000000000000,111000:COP0:32::EI
+010000,1,0000000000000000000,111000:COP0:32::EI
"ei"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
-010000,10000,000000000000000,011000:COP0:32::ERET
+010000,1,0000000000000000000,011000:COP0:32::ERET
"eret"
*mipsIII:
*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
{
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
"mfc0 r<RT>, r<RD> # <REGX>"
-*mipsI,mipsII,mipsIII,mipsIV:
-*r3900:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
+*r3900:
{
TRACE_ALU_INPUT0 ();
DecodeCoproc (instruction_0);
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
-*mipsI,mipsII,mipsIII,mipsIV:
-*r3900:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
+*r3900:
{
DecodeCoproc (instruction_0);
}
-010000,10000,000000000000000,010000:COP0:32::RFE
+010000,1,0000000000000000000,010000:COP0:32::RFE
"rfe"
-*mipsI,mipsII,mipsIII,mipsIV:
-*r3900:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
+*r3900:
{
DecodeCoproc (instruction_0);
}
0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*r3900:
{
-010000,10000,000000000000000,001000:COP0:32::TLBP
+010000,1,0000000000000000000,001000:COP0:32::TLBP
"tlbp"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
-010000,10000,000000000000000,000001:COP0:32::TLBR
+010000,1,0000000000000000000,000001:COP0:32::TLBR
"tlbr"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
-010000,10000,000000000000000,000010:COP0:32::TLBWI
+010000,1,0000000000000000000,000010:COP0:32::TLBWI
"tlbwi"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
-010000,10000,000000000000000,000110:COP0:32::TLBWR
+010000,1,0000000000000000000,000110:COP0:32::TLBWR
"tlbwr"
-*mipsI,mipsII,mipsIII,mipsIV:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000: