Re-fix 32 bit DSRAV instruction.

[deliverable/binutils-gdb.git] / sim / mips / mips.igen

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 64a7c73eb9c434e5a427374868ec50a9f4734751..7b4102c7daac63354e9fdf10826bfb93e5896e77 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -31,10 +31,10 @@
 
 
 // Models known by this simulator
-:model:::mipsI:mipsI:
-:model:::mipsII:mipsII:
-:model:::mipsIII:mipsIII:
-:model:::mipsIV:mipsIV:
+:model:::mipsI:mips3000:
+:model:::mipsII:mips6000:
+:model:::mipsIII:mips4000:
+:model:::mipsIV:mips8000:
 :model:::mips16:mips16:
 // start-sanitize-r5900
 :model:::r5900:mips5900:
@@ -43,6 +43,9 @@
 // start-sanitize-tx19
 :model:::tx19:tx19:
 // end-sanitize-tx19
+// start-sanitize-vr4320
+:model:::vr4320:mips4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 :model:::vr5400:mips5400:
 :model:::mdmx:mdmx:
@@ -68,6 +71,33 @@
 
 
 
+// Helper:
+//
+// Simulate a 32 bit delayslot instruction
+//
+
+:function:::address_word:delayslot32:address_word target
+{
+  instruction_word delay_insn;
+  sim_events_slip (SD, 1);
+  DSPC = CIA;
+  CIA = CIA + 4; /* NOTE not mips16 */
+  STATE |= simDELAYSLOT;
+  delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
+  idecode_issue (CPU_, delay_insn, (CIA));
+  STATE &= ~simDELAYSLOT;
+  return target;
+}
+
+:function:::address_word:nullify_next_insn32:
+{
+  sim_events_slip (SD, 1);
+  dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
+  return CIA + 8;
+}
+
+
+
 //
 // Mips Architecture:
 //
@@ -75,10 +105,14 @@
 //
 
 
+
 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 "add r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -96,10 +130,14 @@
 }
 
 
+
 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 "addi r<RT>, r<RS>, IMMEDIATE"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -117,10 +155,21 @@
 }
 
 
+
+:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
+{
+  TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+  GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
+  TRACE_ALU_RESULT (GPR[rt]);
+}
+
 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
-"add r<RT>, r<RS>, <IMMEDIATE>"
+"addiu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -132,14 +181,25 @@
 *tx19:
 // end-sanitize-tx19
 {
-  signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
-  GPR[RT] = EXTEND32 (temp);
+  do_addiu (SD_, RS, RT, IMMEDIATE);
 }
 
 
+
+:function:::void:do_addu:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
+"addu r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -151,15 +211,25 @@
 *tx19:
 // end-sanitize-tx19
 {
-  signed32 temp = GPR[RS] + GPR[RT];
-  GPR[RD] = EXTEND32 (temp);
+  do_addu (SD_, RS, RT, RD);
 }
 
 
+
+:function:::void:do_and:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = GPR[rs] & GPR[rt];
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 "and r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -171,14 +241,18 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = GPR[RS] & GPR[RT];
+  do_and (SD_, RS, RT, RD);
 }
 
 
+
 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 "and r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -194,10 +268,14 @@
 }
 
 
+
 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 "beq r<RS>, r<RT>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -215,12 +293,16 @@
 }
 
 
+
 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 "beql r<RS>, r<RT>, <OFFSET>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -240,10 +322,14 @@
 }
 
 
+
 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 "bgez r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -261,10 +347,14 @@
 }
 
 
+
 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 "bgezal r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -283,12 +373,16 @@
 }
 
 
+
 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 "bgezall r<RS>, <OFFSET>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -311,12 +405,16 @@
 }
 
 
+
 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 "bgezl r<RS>, <OFFSET>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -336,10 +434,14 @@
 }
 
 
+
 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 "bgtz r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -357,12 +459,16 @@
 }
 
 
+
 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 "bgtzl r<RS>, <OFFSET>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -384,10 +490,14 @@
 }
 
 
+
 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 "blez r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -407,12 +517,16 @@
 }
 
 
+
 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 "bgezl r<RS>, <OFFSET>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -432,10 +546,14 @@
 }
 
 
+
 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 "bltz r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -453,10 +571,14 @@
 }
 
 
+
 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 "bltzal r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -477,12 +599,16 @@
 }
 
 
+
 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 "bltzall r<RS>, <OFFSET>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -503,12 +629,16 @@
 }
 
 
+
 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 "bltzl r<RS>, <OFFSET>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -530,10 +660,14 @@
 }
 
 
+
 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 "bne r<RS>, r<RT>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -551,12 +685,16 @@
 }
 
 
+
 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 "bnel r<RS>, r<RT>, <OFFSET>"
 *mipsII:
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -576,10 +714,14 @@
 }
 
 
+
 000000,20.CODE,001101:SPECIAL:32::BREAK
 "break"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -595,6 +737,7 @@
 }
 
 
+
 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 "cop<ZZ> <COP_FUN>"
 *mipsI,mipsII,mipsIII,mipsIV:
@@ -610,18 +753,21 @@
 }
 
 
+
 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 "dadd r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -633,18 +779,21 @@
 }
 
 
+
 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -655,66 +804,74 @@
 }
 
 
+
+:function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
+{
+  TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+  GPR[rt] = GPR[rs] + EXTEND16 (immediate);
+  TRACE_ALU_RESULT (GPR[rt]);
+}
+
 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
+  do_daddiu (SD_, RS, RT, IMMEDIATE);
 }
 
 
+
+:function:::void:do_daddu:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = GPR[rs] + GPR[rt];
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 "daddu r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = GPR[RS] + GPR[RT];
+  do_daddu (SD_, RS, RT, RD);
 }
 
 
-000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
-"ddiv r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+
+:function:64::void:do_ddiv:int rs, int rt
 {
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   CHECKHILO ("Division");
   {
-    signed64 n = GPR[RS];
-    signed64 d = GPR[RT];
+    signed64 n = GPR[rs];
+    signed64 d = GPR[rt];
     if (d == 0)
       {
        LO = SIGNED64 (0x8000000000000000);
@@ -731,27 +888,39 @@
        HI = (n % d);
       }
   }
+  TRACE_ALU_RESULT2 (HI, LO);
 }
 
-
-
-000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
-"ddivu r<RS>, r<RT>"
+000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
+"ddiv r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
-*r3900:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
+  do_ddiv (SD_, RS, RT);
+}
+
+
+
+:function:64::void:do_ddivu:int rs, int rt
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   CHECKHILO ("Division");
   {
-    unsigned64 n = GPR[RS];
-    unsigned64 d = GPR[RT];
+    unsigned64 n = GPR[rs];
+    unsigned64 d = GPR[rt];
     if (d == 0)
       {
        LO = SIGNED64 (0x8000000000000000);
@@ -763,28 +932,36 @@
        HI = (n % d);
       }
   }
+  TRACE_ALU_RESULT2 (HI, LO);
 }
 
-
-000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
-"div r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
+"ddivu r<RS>, r<RT>"
+*mipsIII:
+*mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
+  do_ddivu (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_div:int rs, int rt
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   CHECKHILO("Division");
   {
-    signed32 n = GPR[RS];
-    signed32 d = GPR[RT];
+    signed32 n = GPR[rs];
+    signed32 d = GPR[rt];
     if (d == 0)
       {
        LO = EXTEND32 (0x80000000);
@@ -801,13 +978,16 @@
        HI = EXTEND32 (n % d);
       }
   }
+  TRACE_ALU_RESULT2 (HI, LO);
 }
 
-
-000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
-"divu r<RS>, r<RT>"
+000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
+"div r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -819,10 +999,18 @@
 *tx19:
 // end-sanitize-tx19
 {
+  do_div (SD_, RS, RT);
+}
+
+
+
+:function:::void:do_divu:int rs, int rt
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   CHECKHILO ("Division");
   {
-    unsigned32 n = GPR[RS];
-    unsigned32 d = GPR[RT];
+    unsigned32 n = GPR[rs];
+    unsigned32 d = GPR[rt];
     if (d == 0)
       {
        LO = EXTEND32 (0x80000000);
@@ -834,10 +1022,33 @@
        HI = EXTEND32 (n % d);
      }
   }
+  TRACE_ALU_RESULT2 (HI, LO);
+}
+
+000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
+"divu r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+  do_divu (SD_, RS, RT);
 }
 
 
-:function:::void:do_dmult:int rs, int rt, int rd, int signed_p
+
+:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
 {
   unsigned64 lo;
   unsigned64 hi;
@@ -849,6 +1060,7 @@
   int sign;
   unsigned64 op1 = GPR[rs];
   unsigned64 op2 = GPR[rt];
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   CHECKHILO ("Multiplication");
   /* make signed multiply unsigned */ 
   sign = 0;
@@ -893,18 +1105,25 @@
   HI = hi;
   if (rd != 0)
     GPR[rd] = lo;
+  TRACE_ALU_RESULT2 (HI, LO);
 }
 
+:function:::void:do_dmult:int rs, int rt, int rd
+{
+  do_dmultx (SD_, rs, rt, rd, 1);
+}
 
 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 "dmult r<RS>, r<RT>"
 *mipsIII,mipsIV:
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 {
-  do_dmult (SD_, RS, RT, 0, 1);
+  do_dmult (SD_, RS, RT, 0);
 }
 
 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
@@ -915,20 +1134,27 @@
 *vr5400:
 // end-sanitize-vr5400
 {
-  do_dmult (SD_, RS, RT, RD, 1);
+  do_dmult (SD_, RS, RT, RD);
 }
 
 
 
+:function:::void:do_dmultu:int rs, int rt, int rd
+{
+  do_dmultx (SD_, rs, rt, rd, 0);
+}
+
 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
 "dmultu r<RS>, r<RT>"
 *mipsIII,mipsIV:
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 {
-  do_dmult (SD_, RS, RT, 0, 0);
+  do_dmultu (SD_, RS, RT, 0);
 }
 
 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
@@ -939,7 +1165,7 @@
 *vr5400:
 // end-sanitize-vr5400
 {
-  do_dmult (SD_, RS, RT, RD, 0);
+  do_dmultu (SD_, RS, RT, RD);
 }
 
 
@@ -949,13 +1175,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -970,13 +1198,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -986,18 +1216,21 @@
 }
 
 
+
 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
 "dsllv r<RD>, r<RT>, r<RS>"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1007,18 +1240,21 @@
 }
 
 
+
 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
 "dsra r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1033,13 +1269,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1049,39 +1287,50 @@
 }
 
 
+:function:::void:do_dsrav:int rs, int rt, int rd
+{
+  int s = MASKED64 (GPR[rs], 5, 0);
+  TRACE_ALU_INPUT2 (GPR[rt], s);
+  GPR[rd] = ((signed64) GPR[rt]) >> s;
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
 "dsra32 r<RT>, r<RD>, r<RS>"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  int s = MASKED64 (GPR[RS], 5, 0);
-  GPR[RD] = ((signed64) GPR[RT]) >> s;
+  do_dsrav (SD_, RS, RT, RD);
 }
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
-"dsrav r<RD>, r<RT>, <SHIFT>"
+"dsrl r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1096,13 +1345,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1117,13 +1368,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1138,13 +1391,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1155,23 +1410,32 @@
 }
 
 
+:function:::void:do_dsubu:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = GPR[rs] - GPR[rt];
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
 "dsubu r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = GPR[RS] - GPR[RT];
+  do_dsubu (SD_, RS, RT, RD);
 }
 
 
@@ -1179,6 +1443,9 @@
 "j <INSTR_INDEX>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1201,6 +1468,9 @@
 "jal <INSTR_INDEX>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1225,6 +1495,9 @@
 "jalr r<RD>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1246,6 +1519,9 @@
 "jr r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1261,29 +1537,35 @@
 }
 
 
-:function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset
+:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
 {
-  address_word vaddr = offset + gpr_base;
+  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+  address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+  address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+  unsigned int byte;
   address_word paddr;
   int uncached;
-  if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-    {
-      unsigned64 memval = 0;
-      address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-      unsigned int reverse = (ReverseEndian ? mask : 0);
-      unsigned int bigend = (BigEndianCPU ? mask : 0);
-      unsigned int byte;
-      paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-      LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL);
-      byte = ((vaddr & mask) ^ bigend);
-      GPR[rt] = EXTEND8 ((memval >> (8 * byte)));
-    }
+  unsigned64 memval;
+  address_word vaddr;
+
+  vaddr = base + offset;
+  if ((vaddr & access) != 0)
+    SignalExceptionAddressLoad ();
+  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+  LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
+  byte = ((vaddr & mask) ^ bigendiancpu);
+  return (memval >> (8 * byte));
 }
 
+
 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
 "lb r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1295,34 +1577,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  do_load_byte (SD_, GPR[BASE], RT, OFFSET);
-#if 0
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((uword64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-       {
-         uword64 memval = 0;
-         uword64 memval1 = 0;
-         uword64 mask = 0x7;
-         unsigned int shift = 0;
-         unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-         unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-         unsigned int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-         LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
-         byte = ((vaddr & mask) ^ (bigend << shift));
-         GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
-       }
-    }
-  }
-#endif
+  GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
 }
 
 
@@ -1330,6 +1585,9 @@
 "lbu r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1341,31 +1599,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 0x7;
-         unsigned int shift = 0;
-         unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-         unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-         unsigned int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-         LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
-         byte = ((vaddr & mask) ^ (bigend << shift));
-         GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
-       }
-    }
-  }
+  GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
 }
 
 
@@ -1374,38 +1608,20 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 7) != 0)
-      SignalExceptionAddressLoad();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
-           GPR[destreg] = memval;
-         }
-      }
-  }
+  GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
 
 
@@ -1415,83 +1631,42 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 7) != 0)
-      SignalExceptionAddressLoad();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
-           COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
-         }
-      }
-  }
+  COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
 
 
+
+
 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
 "ldl r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 7;
-         unsigned int reverse = (ReverseEndian ? mask : 0);
-         unsigned int bigend = (BigEndianCPU ? mask : 0);
-         int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-         byte = ((vaddr & mask) ^ bigend);
-         if (!BigEndianMem)
-           paddr &= ~mask;
-         LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
-         GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
-       }
-    }
-  }
+  GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
@@ -1500,50 +1675,20 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 7;
-         unsigned int reverse = (ReverseEndian ? mask : 0);
-         unsigned int bigend = (BigEndianCPU ? mask : 0);
-         int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-         byte = ((vaddr & mask) ^ bigend);
-         if (BigEndianMem)
-           paddr &= ~mask;
-         LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
-         {
-           unsigned64 srcmask;
-           if (byte == 0)
-             srcmask = 0;
-           else
-             srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
-           GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
-         }
-       }
-    }
-  }
+  GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
@@ -1551,6 +1696,9 @@
 "lh r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1562,34 +1710,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 1) != 0)
-      SignalExceptionAddressLoad();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           unsigned64 mask = 0x7;
-           unsigned int shift = 1;
-           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-           LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
-           byte = ((vaddr & mask) ^ (bigend << shift));
-           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
-         }
-      }
-  }
+  GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
 
 
@@ -1597,6 +1718,9 @@
 "lhu r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1608,34 +1732,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 1) != 0)
-      SignalExceptionAddressLoad();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           unsigned64 mask = 0x7;
-           unsigned int shift = 1;
-           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-           LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
-           byte = ((vaddr & mask) ^ (bigend << shift));
-           GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
-         }
-      }
-  }
+  GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
 }
 
 
@@ -1645,13 +1742,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1693,13 +1792,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1733,6 +1834,9 @@
 "lui r<RT>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1752,6 +1856,9 @@
 "lw r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1763,34 +1870,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 3) != 0)
-      SignalExceptionAddressLoad();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           unsigned64 mask = 0x7;
-           unsigned int shift = 2;
-           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-           LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
-           byte = ((vaddr & mask) ^ (bigend << shift));
-           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
-         }
-      }
-  }
+  GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
 
 
@@ -1798,6 +1878,9 @@
 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1809,34 +1892,44 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 3) != 0)
-      SignalExceptionAddressLoad();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           unsigned64 mask = 0x7;
-           unsigned int shift = 2;
-           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-           LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
-           byte = ((vaddr & mask) ^ (bigend << shift));
-           COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
-         }
-      }
-  }
+  COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+  address_word reverseendian = (ReverseEndian ? -1 : 0);
+  address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+  unsigned int byte;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+  address_word vaddr;
+
+  vaddr = base + offset;
+  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+  paddr = (paddr ^ (reverseendian & mask));
+  if (BigEndianMem == 0)
+    paddr = paddr & ~access;
+  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+  LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
+  /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
+     (long) vaddr, byte, (long) paddr, (long) memval); */
+  if ((byte & ~access) == 0)
+    {
+      int bits = 8 * (access - byte);
+      unsigned_word screen = LSMASK (bits - 1, 0);
+      rt &= screen;
+      rt |= ((memval << bits) & ~screen);
+    }
+  else
+    {
+      unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
+      rt &= screen;
+      rt |= ((memval >> (8 * (mask - byte))) & ~screen);
+    }
+  return rt;
 }
 
 
@@ -1844,6 +1937,9 @@
 "lwl r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1855,36 +1951,38 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+  GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
+}
+
+
+:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+  address_word reverseendian = (ReverseEndian ? -1 : 0);
+  address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+  unsigned int byte;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+  address_word vaddr;
+
+  vaddr = base + offset;
+  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+  /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
+  paddr = (paddr ^ (reverseendian & mask));
+  if (BigEndianMem != 0)
+    paddr = paddr & ~access;
+  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+  /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
+  LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
+  /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
+     (long) paddr, byte, (long) paddr, (long) memval); */
   {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 3;
-         unsigned int reverse = (ReverseEndian ? mask : 0);
-         unsigned int bigend = (BigEndianCPU ? mask : 0);
-         int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-         byte = ((vaddr & mask) ^ bigend);
-         if (!BigEndianMem)
-           paddr &= ~mask;
-         LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
-         if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
-           memval >>= 32;
-         }
-         GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
-         GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
-       }
-    }
+    unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
+    rt &= ~screen;
+    rt |= (memval >> (8 * byte)) & screen;
   }
+  return rt;
 }
 
 
@@ -1892,6 +1990,9 @@
 "lwr r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1903,43 +2004,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 3;
-         unsigned int reverse = (ReverseEndian ? mask : 0);
-         unsigned int bigend = (BigEndianCPU ? mask : 0);
-         int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-         byte = ((vaddr & mask) ^ bigend);
-         if (BigEndianMem)
-           paddr &= ~mask;
-         LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
-         if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
-           memval >>= 32;
-         }
-         {
-           unsigned64 srcmask;
-           if (byte == 0)
-             srcmask = 0;
-           else
-             srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
-           GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
-         }
-         GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
-       }
-    }
-  }
+  GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
 }
 
 
@@ -1948,52 +2013,40 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 3) != 0)
-      SignalExceptionAddressLoad();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           unsigned64 mask = 0x7;
-           unsigned int shift = 2;
-           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-           LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
-           byte = ((vaddr & mask) ^ (bigend << shift));
-           GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
-         }
-      }
-  }
+  GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
 }
 
 
+:function:::void:do_mfhi:int rd
+{
+  TRACE_ALU_INPUT1 (HI);
+  GPR[rd] = HI;
+  TRACE_ALU_RESULT (GPR[rd]);
+#if 0
+  HIACCESS = 3;
+#endif
+}
+
 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
 "mfhi r<RD>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2005,17 +2058,28 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = HI;
+  do_mfhi (SD_, RD);
+}
+
+
+
+:function:::void:do_mflo:int rd
+{
+  TRACE_ALU_INPUT1 (LO);
+  GPR[rd] = LO;
+  TRACE_ALU_RESULT (GPR[rd]);
 #if 0
-  HIACCESS = 3;
+  LOACCESS = 3; /* 3rd instruction will be safe */
 #endif
 }
 
-
 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
 "mflo r<RD>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2027,17 +2091,18 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = LO;
-#if 0
-  LOACCESS = 3; /* 3rd instruction will be safe */
-#endif
+  do_mflo (SD_, RD);
 }
 
 
+
 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
 "movn r<RD>, r<RS>, r<RT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2050,10 +2115,14 @@
 }
 
 
+
 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
 "movz r<RD>, r<RS>, r<RT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2066,10 +2135,14 @@
 }
 
 
+
 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
 "mthi r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2092,10 +2165,14 @@
 }
 
 
+
 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
 "mtlo r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2118,17 +2195,32 @@
 }
 
 
-000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
-"mult r<RS>, r<RT>"
-*mipsI,mipsII,mipsIII,mipsIV:
+
+:function:::void:do_mult:int rs, int rt, int rd
 {
   signed64 prod;
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   CHECKHILO ("Multiplication");
-  prod = (((signed64)(signed32) GPR[RS])
-         * ((signed64)(signed32) GPR[RT]));
+  prod = (((signed64)(signed32) GPR[rs])
+         * ((signed64)(signed32) GPR[rt]));
   LO = EXTEND32 (VL4_8 (prod));
   HI = EXTEND32 (VH4_8 (prod));
+  if (rd != 0)
+    GPR[rd] = LO;
+  TRACE_ALU_RESULT2 (HI, LO);
+}
+
+000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
+"mult r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+{
+  do_mult (SD_, RS, RT, 0);
 }
+
+
 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
 "mult r<RD>, r<RS>, r<RT>"
 *vr5000:
@@ -2143,28 +2235,34 @@
 *tx19:
 // end-sanitize-tx19
 {
-  signed64 prod;
+  do_mult (SD_, RS, RT, RD);
+}
+
+
+:function:::void:do_multu:int rs, int rt, int rd
+{
+  unsigned64 prod;
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   CHECKHILO ("Multiplication");
-  prod = (((signed64)(signed32) GPR[RS])
-         * ((signed64)(signed32) GPR[RT]));
+  prod = (((unsigned64)(unsigned32) GPR[rs])
+         * ((unsigned64)(unsigned32) GPR[rt]));
   LO = EXTEND32 (VL4_8 (prod));
   HI = EXTEND32 (VH4_8 (prod));
-  if (RD != 0)
-    GPR[RD] = LO;
+  if (rd != 0)
+    GPR[rd] = LO;
+  TRACE_ALU_RESULT2 (HI, LO);
 }
 
-
 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
 "multu r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 {
-  unsigned64 prod;
-  CHECKHILO ("Multiplication");
-  prod = (((unsigned64)(unsigned32) GPR[RS])
-         * ((unsigned64)(unsigned32) GPR[RT]));
-  LO = EXTEND32 (VL4_8 (prod));
-  HI = EXTEND32 (VH4_8 (prod));
+  do_multu (SD_, RS, RT, 0);
 }
+
 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
 "multu r<RD>, r<RS>, r<RT>"
 *vr5000:
@@ -2179,21 +2277,24 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned64 prod;
-  CHECKHILO ("Multiplication");
-  prod = (((unsigned64)(unsigned32) GPR[RS])
-         * ((unsigned64)(unsigned32) GPR[RT]));
-  LO = EXTEND32 (VL4_8 (prod));
-  HI = EXTEND32 (VH4_8 (prod));
-  if (RD != 0)
-    GPR[RD] = LO;
+  do_multu (SD_, RS, RT, 0);
 }
 
 
+:function:::void:do_nor:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = ~ (GPR[rs] | GPR[rt]);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
 "nor r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2205,14 +2306,24 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = ~ (GPR[RS] | GPR[RT]);
+  do_nor (SD_, RS, RT, RD);
 }
 
 
+:function:::void:do_or:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = (GPR[rs] | GPR[rt]);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
 "or r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2224,14 +2335,25 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = (GPR[RS] | GPR[RT]);
+  do_or (SD_, RS, RT, RD);
 }
 
 
+
+:function:::void:do_ori:int rs, int rt, unsigned immediate
+{
+  TRACE_ALU_INPUT2 (GPR[rs], immediate);
+  GPR[rt] = (GPR[rs] | immediate);
+  TRACE_ALU_RESULT (GPR[rt]);
+}
+
 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
 "ori r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2243,13 +2365,16 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RT] = (GPR[RS] | IMMEDIATE);
+  do_ori (SD_, RS, RT, IMMEDIATE);
 }
 
 
 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2272,10 +2397,35 @@
   }
 }
 
+:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
+{
+  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+  address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+  address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+  unsigned int byte;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+  address_word vaddr;
+
+  vaddr = base + offset;
+  if ((vaddr & access) != 0)
+    SignalExceptionAddressStore ();
+  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+  byte = ((vaddr & mask) ^ bigendiancpu);
+  memval = (word << (8 * byte));
+  StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
+}
+
+
 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
 "sb r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2287,33 +2437,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 0x7;
-         unsigned int shift = 0;
-         unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-         unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-         unsigned int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-         byte = ((vaddr & mask) ^ (bigend << shift));
-         memval = ((unsigned64) op2 << (8 * byte));
-         {
-           StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
-         }
-       }
-    }
-  }
+  do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
@@ -2323,13 +2447,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -2371,13 +2497,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -2415,40 +2543,20 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 7) != 0)
-      SignalExceptionAddressStore();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           memval = op2;
-           {
-             StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
-           }
-         }
-      }
-  }
+  do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
@@ -2458,40 +2566,20 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 7) != 0)
-      SignalExceptionAddressStore();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
-           {
-             StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
-           }
-         }
-      }
-  }
+  do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
 }
 
 
@@ -2500,43 +2588,20 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 7;
-         unsigned int reverse = (ReverseEndian ? mask : 0);
-         unsigned int bigend = (BigEndianCPU ? mask : 0);
-         int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-         byte = ((vaddr & mask) ^ bigend);
-         if (!BigEndianMem)
-           paddr &= ~mask;
-         memval = (op2 >> (8 * (7 - byte)));
-         StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
-       }
-    }
-  }
+  do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
@@ -2545,32 +2610,20 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-  unsigned64 mask = 7;
-  unsigned int reverse = (ReverseEndian ? mask : 0);
-  unsigned int bigend = (BigEndianCPU ? mask : 0);
-  int byte;
-  address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
-  AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
-  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-  if (BigEndianMem)
-    paddr &= ~mask;
-  byte = ((vaddr & mask) ^ bigend);
-  memval = (GPR[RT] << (byte * 8));
-  StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,0,paddr,vaddr,isREAL);
+  do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
@@ -2578,6 +2631,9 @@
 "sh r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2585,47 +2641,29 @@
 *r5900:
 // end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 1) != 0)
-      SignalExceptionAddressStore();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           unsigned64 mask = 0x7;
-           unsigned int shift = 1;
-           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-           byte = ((vaddr & mask) ^ (bigend << shift));
-           memval = ((unsigned64) op2 << (8 * byte));
-           {
-             StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
-           }
-         }
-      }
-  }
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+  do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
+:function:::void:do_sll:int rt, int rd, int shift
+{
+  unsigned32 temp = (GPR[rt] << shift);
+  TRACE_ALU_INPUT2 (GPR[rt], shift);
+  GPR[rd] = EXTEND32 (temp);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
 "sll r<RD>, r<RT>, <SHIFT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2637,16 +2675,26 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = SHIFT;
-  unsigned32 temp = (GPR[RT] << s);
-  GPR[RD] = EXTEND32 (temp);
+  do_sll (SD_, RT, RD, SHIFT);
 }
 
 
+:function:::void:do_sllv:int rs, int rt, int rd
+{
+  int s = MASKED (GPR[rs], 4, 0);
+  unsigned32 temp = (GPR[rt] << s);
+  TRACE_ALU_INPUT2 (GPR[rt], s);
+  GPR[rd] = EXTEND32 (temp);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
 "sllv r<RD>, r<RT>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2658,16 +2706,24 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = MASKED (GPR[RS], 4, 0);
-  unsigned32 temp = (GPR[RT] << s);
-  GPR[RD] = EXTEND32 (temp);
+  do_sllv (SD_, RS, RT, RD);
 }
 
 
+:function:::void:do_slt:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
 "slt r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2679,14 +2735,24 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
+  do_slt (SD_, RS, RT, RD);
 }
 
 
+:function:::void:do_slti:int rs, int rt, unsigned16 immediate
+{
+  TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+  GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
+  TRACE_ALU_RESULT (GPR[rt]);
+}
+
 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
 "slti r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2698,14 +2764,24 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
+  do_slti (SD_, RS, RT, IMMEDIATE);
 }
 
 
+:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
+{
+  TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+  GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
+  TRACE_ALU_RESULT (GPR[rt]);
+}
+
 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2717,13 +2793,25 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
+  do_sltiu (SD_, RS, RT, IMMEDIATE);
+}
+
+
+
+:function:::void:do_sltu:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
+  TRACE_ALU_RESULT (GPR[rd]);
 }
 
 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
 "sltu r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2735,14 +2823,25 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
+  do_sltu (SD_, RS, RT, RD);
 }
 
 
+:function:::void:do_sra:int rt, int rd, int shift
+{
+  signed32 temp = (signed32) GPR[rt] >> shift;
+  TRACE_ALU_INPUT2 (GPR[rt], shift);
+  GPR[rd] = EXTEND32 (temp);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
 "sra r<RD>, r<RT>, <SHIFT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2754,16 +2853,27 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = SHIFT;
-  signed32 temp = (signed32) GPR[RT] >> s;
-  GPR[RD] = EXTEND32 (temp);
+  do_sra (SD_, RT, RD, SHIFT);
 }
 
 
+
+:function:::void:do_srav:int rs, int rt, int rd
+{
+  int s = MASKED (GPR[rs], 4, 0);
+  signed32 temp = (signed32) GPR[rt] >> s;
+  TRACE_ALU_INPUT2 (GPR[rt], s);
+  GPR[rd] = EXTEND32 (temp);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
 "srav r<RD>, r<RT>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2775,16 +2885,26 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = MASKED (GPR[RS], 4, 0);
-  signed32 temp = (signed32) GPR[RT] >> s;
-  GPR[RD] = EXTEND32 (temp);
+  do_srav (SD_, RS, RT, RD);
 }
 
 
+
+:function:::void:do_srl:int rt, int rd, int shift
+{
+  unsigned32 temp = (unsigned32) GPR[rt] >> shift;
+  TRACE_ALU_INPUT2 (GPR[rt], shift);
+  GPR[rd] = EXTEND32 (temp);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
 "srl r<RD>, r<RT>, <SHIFT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2796,16 +2916,26 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = SHIFT;
-  unsigned32 temp = (unsigned32) GPR[RT] >> s;
-  GPR[RD] = EXTEND32 (temp);
+  do_srl (SD_, RT, RD, SHIFT);
 }
 
 
+:function:::void:do_srlv:int rs, int rt, int rd
+{
+  int s = MASKED (GPR[rs], 4, 0);
+  unsigned32 temp = (unsigned32) GPR[rt] >> s;
+  TRACE_ALU_INPUT2 (GPR[rt], s);
+  GPR[rd] = EXTEND32 (temp);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
 "srlv r<RD>, r<RT>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2817,9 +2947,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = MASKED (GPR[RS], 4, 0);
-  unsigned32 temp = (unsigned32) GPR[RT] >> s;
-  GPR[RD] = EXTEND32 (temp);
+  do_srlv (SD_, RS, RT, RD);
 }
 
 
@@ -2827,6 +2955,9 @@
 "sub r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2844,10 +2975,20 @@
 }
 
 
+:function:::void:do_subu:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
 "subu r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2859,13 +3000,20 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
+  do_subu (SD_, RS, RT, RD);
 }
 
 
 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
 "sw r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+*r3900:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 *vr5000:
 // start-sanitize-vr5400
 *vr5400:
@@ -2873,38 +3021,8 @@
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 3) != 0)
-      SignalExceptionAddressStore();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           unsigned64 mask = 0x7;
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
-           byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
-           memval = ((unsigned64) op2 << (8 * byte));
-           {
-             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
-           }
-         }
-      }
-  }
+  do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
@@ -2912,44 +3030,44 @@
 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  int destreg = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 3) != 0)
-      SignalExceptionAddressStore();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           unsigned64 mask = 0x7;
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
-           byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
-           memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
-           {
-             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
-           }
-         }
-      }
-  }
+  do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
+}
+
+
+
+:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+  address_word reverseendian = (ReverseEndian ? -1 : 0);
+  address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+  unsigned int byte;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+  address_word vaddr;
+
+  vaddr = base + offset;
+  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+  paddr = (paddr ^ (reverseendian & mask));
+  if (BigEndianMem == 0)
+    paddr = paddr & ~access;
+  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+  if ((byte & ~access) == 0)
+    memval = (rt >> (8 * (access - byte)));
+  else
+    memval = (rt << (8 * (mask - byte)));
+  StoreMemory (uncached, byte & access, memval, NULL, paddr, vaddr, isREAL);
 }
 
 
@@ -2957,6 +3075,9 @@
 "swl r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2968,42 +3089,38 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 3;
-         unsigned int reverse = (ReverseEndian ? mask : 0);
-         unsigned int bigend = (BigEndianCPU ? mask : 0);
-         int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-         byte = ((vaddr & mask) ^ bigend);
-         if (!BigEndianMem)
-           paddr &= ~mask;
-         memval = (op2 >> (8 * (3 - byte)));
-         if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
-           memval <<= 32;
-         }
-         StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
-       }
-    }
-  }
+  do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
+:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+  address_word reverseendian = (ReverseEndian ? -1 : 0);
+  address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+  unsigned int byte;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+  address_word vaddr;
+
+  vaddr = base + offset;
+  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+  paddr = (paddr ^ (reverseendian & mask));
+  if (BigEndianMem != 0)
+    paddr &= ~access;
+  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+  memval = (rt << (byte * 8));
+  StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
+}
+
 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
 "swr r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3015,23 +3132,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned64 memval = 0;
-  unsigned64 mask = 3;
-  unsigned int reverse = (ReverseEndian ? mask : 0);
-  unsigned int bigend = (BigEndianCPU ? mask : 0);
-  int byte;
-  address_word paddr;
-  int uncached;
-  address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
-  AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
-  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-  if (BigEndianMem)
-    paddr &= ~mask;
-  byte = ((vaddr & mask) ^ bigend);
-  memval = (GPR[RT] << (byte * 8));
-  if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2))
-    memval <<= 32;
-  StoreMemory(uncached,(AccessLength_WORD - byte),memval,0,paddr,vaddr,isREAL);
+  do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
 
 
@@ -3042,6 +3143,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3061,6 +3165,9 @@
 "syscall <CODE>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3082,13 +3189,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3104,13 +3213,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3126,13 +3237,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3148,13 +3261,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3170,13 +3285,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3192,13 +3309,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3214,13 +3333,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3236,13 +3357,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3258,13 +3381,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3280,13 +3405,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3302,13 +3429,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3324,13 +3453,15 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3340,10 +3471,20 @@
 }
 
 
+:function:::void:do_xor:int rs, int rt, int rd
+{
+  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+  GPR[rd] = GPR[rs] ^ GPR[rt];
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
 "xor r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3355,14 +3496,24 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = GPR[RS] ^ GPR[RT];
+  do_xor (SD_, RS, RT, RD);
 }
 
 
+:function:::void:do_xori:int rs, int rt, unsigned16 immediate
+{
+  TRACE_ALU_INPUT2 (GPR[rs], immediate);
+  GPR[rt] = GPR[rs] ^ immediate;
+  TRACE_ALU_RESULT (GPR[rt]);
+}
+
 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
 "xori r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3374,7 +3525,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RT] = GPR[RS] ^ IMMEDIATE;
+  do_xori (SD_, RS, RT, IMMEDIATE);
 }
 
 \f
@@ -3452,6 +3603,9 @@
 "abs.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3478,6 +3632,9 @@
 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3536,6 +3693,9 @@
 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3608,6 +3768,9 @@
 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3625,6 +3788,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3654,6 +3820,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3708,6 +3877,9 @@
 "c%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3765,6 +3937,9 @@
 "cvt.d.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3791,6 +3966,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3819,6 +3997,9 @@
 "cvt.s.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3844,6 +4025,9 @@
 "cvt.w.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3869,6 +4053,9 @@
 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3921,6 +4108,9 @@
 "dm%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3956,6 +4146,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3986,6 +4179,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4016,6 +4212,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4024,18 +4223,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
-  address_word paddr;
-  int uncached;
-  if ((vaddr & 7) != 0)
-    SignalExceptionAddressLoad();
-  else
-    {
-      unsigned64 memval;
-      AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
-      LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
-      COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
-    }
+  COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
 
 
@@ -4043,31 +4231,14 @@
 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 {
-  unsigned32 instruction = instruction_0;
-  int destreg = ((instruction >> 6) & 0x0000001F);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + op2);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 7) != 0)
-      SignalExceptionAddressLoad();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
-           COP_LD(1,destreg,memval);;
-         }
-      }
-  }
+  COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
 }
 
 
@@ -4076,6 +4247,9 @@
 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4087,34 +4261,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = EXTEND16 (OFFSET);
-  int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
-  signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((uword64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 3) != 0)
-      SignalExceptionAddressLoad();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-         {
-           uword64 memval = 0;
-           uword64 memval1 = 0;
-           uword64 mask = 0x7;
-           unsigned int shift = 2;
-           unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
-           unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
-           unsigned int byte UNUSED;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-           LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
-           byte = ((vaddr & mask) ^ (bigend << shift));
-           COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
-         }
-      }
-  }
+  COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
 
 
@@ -4122,38 +4269,14 @@
 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 {
-  unsigned32 instruction = instruction_0;
-  int destreg = ((instruction >> 6) & 0x0000001F);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-   address_word vaddr = ((unsigned64)op1 + op2);
-   address_word paddr;
-   int uncached;
-   if ((vaddr & 3) != 0)
-    SignalExceptionAddressLoad();
-   else
-   {
-    if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-    {
-     unsigned64 memval = 0;
-     unsigned64 memval1 = 0;
-     unsigned64 mask = 0x7;
-     unsigned int shift = 2;
-     unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-     unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-     unsigned int byte;
-     paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-     LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
-     byte = ((vaddr & mask) ^ (bigend << shift));
-     COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
-    }
-   }
-  }
+  COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
 }
 
 
@@ -4165,6 +4288,9 @@
 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4184,6 +4310,9 @@
 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4221,6 +4350,9 @@
 "m%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4241,6 +4373,9 @@
 "mov.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4264,6 +4399,9 @@
 "mov%s<TF> r<RD>, r<RS>, <CC>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4281,6 +4419,9 @@
 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4302,6 +4443,9 @@
 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4330,6 +4474,9 @@
 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4352,6 +4499,9 @@
 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4375,6 +4525,9 @@
 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4400,6 +4553,9 @@
 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4426,6 +4582,9 @@
 "neg.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4452,6 +4611,9 @@
 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4472,6 +4634,9 @@
 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4492,6 +4657,9 @@
 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4512,6 +4680,9 @@
 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4531,6 +4702,9 @@
 "prefx <HINT>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4552,6 +4726,9 @@
 *mipsIV:
 "recip.%s<FMT> f<FD>, f<FS>"
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4574,6 +4751,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4604,6 +4784,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4632,6 +4815,9 @@
 *mipsIV:
 "rsqrt.%s<FMT> f<FD>, f<FS>"
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4655,6 +4841,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4663,52 +4852,22 @@
 *tx19:
 // end-sanitize-tx19
 {
-  address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
-  int uncached;
-  if ((vaddr & 7) != 0)
-    SignalExceptionAddressStore();
-  else
-    {
-      address_word paddr;
-      unsigned64 memval;
-      AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
-      memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
-      StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
-    }
+  do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
 }
 
 
-
-010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
+010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
+"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 {
-  unsigned32 instruction = instruction_0;
-  int fs = ((instruction >> 11) & 0x0000001F);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + op2);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 7) != 0)
-      SignalExceptionAddressStore();
-    else
-      {
-       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           memval = (unsigned64)COP_SD(1,fs);
-           {
-             StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
-           }
-         }
-      }
-  }
+  do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
 }
 
 
@@ -4718,6 +4877,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4743,6 +4905,9 @@
 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4770,6 +4935,9 @@
 "swc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4815,6 +4983,9 @@
 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4854,6 +5025,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4884,6 +5058,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4919,6 +5096,9 @@
 "bc0f <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4931,6 +5111,9 @@
 "bc0fl <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4952,6 +5135,9 @@
 "bc0tl <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4964,6 +5150,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4993,6 +5182,9 @@
 "di"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -5005,6 +5197,9 @@
 "ei"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -5018,6 +5213,9 @@
 *mipsIII:
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -5030,6 +5228,9 @@
 "mfc0 r<RT>, r<RD> # <REGX>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -5043,6 +5244,13 @@
 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
 "mtc0 r<RT>, r<RD> # <REGX>"
 *mipsI,mipsII,mipsIII,mipsIV:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+*r3900:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 *vr5000:
 // start-sanitize-vr5400
 *vr5400:
@@ -5059,6 +5267,9 @@
 "tlbp"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -5071,6 +5282,9 @@
 "tlbr"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -5083,6 +5297,9 @@
 "tlbwi"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -5095,6 +5312,9 @@
 "tlbwr"
 *mipsI,mipsII,mipsIII,mipsIV:
 *vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -5103,7 +5323,10 @@
 // end-sanitize-r5900
 
 \f
-:include:16::m16.igen
+:include:::m16.igen
+// start-sanitize-vr4320
+:include::vr4320:vr4320.igen
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 :include::vr5400:vr5400.igen
 :include:64,f::mdmx.igen
@@ -5111,6 +5334,7 @@
 // start-sanitize-r5900
 :include::r5900:r5900.igen
 // end-sanitize-r5900
+:include:::tx.igen
 \f
 // start-sanitize-cygnus-never