:model:::mipsIII:mips4000:
:model:::mipsIV:mips8000:
:model:::mipsV:mipsisaV:
+:model:::mips32:mipsisa32:
+:model:::mips64:mipsisa64:
// Vendor ISAs:
//
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
*vr4100:
*vr5000:
*r3900:
return base + offset;
}
+:function:::address_word:loadstore_ea:address_word base, address_word offset
+*mips64:
+{
+#if 0 /* XXX FIXME: enable this only after some additional testing. */
+ /* If in user mode and UX is not set, use 32-bit compatibility effective
+ address computations as defined in the MIPS64 Architecture for
+ Programmers Volume III, Revision 0.95, section 4.9. */
+ if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
+ == (ksu_user << status_KSU_shift))
+ return (address_word)((signed32)base + (signed32)offset);
+#endif
+ return base + offset;
+}
+
// Helper:
//
}
:function:::int:check_mt_hilo:hilo_history *history
+*mips32:
+*mips64:
*r3900:
{
signed64 time = sim_events_time (SD);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
// The r3900 mult and multu insns _can_ be exectuted immediatly after
// a mf{hi,lo}
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mips32:
+*mips64:
*r3900:
{
/* FIXME: could record the fact that a stall occured if we want */
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*vr4100:
*vr5000:
{
- // On mips64, if UserMode check SR:PX & SR:UX bits.
// The check should be similar to mips64 for any with PX/UX bit equivalents.
}
+:function:::void:check_u64:instruction_word insn
+*mips64:
+{
+#if 0 /* XXX FIXME: enable this only after some additional testing. */
+ if (UserMode && (SR & (status_UX|status_PX)) == 0)
+ SignalException (ReservedInstruction, insn);
+#endif
+}
+
//
// MIPS Architecture:
//
-// CPU Instruction Set (mipsI - mipsV)
+// CPU Instruction Set (mipsI - mipsV, mips32, mips64)
//
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
+011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
+"clo r<RD>, r<RS>"
+*mips32:
+*mips64:
+{
+ unsigned32 temp = GPR[RS];
+ unsigned32 i, mask;
+ if (RT != RD)
+ Unpredictable();
+ TRACE_ALU_INPUT1 (GPR[RS]);
+ for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ {
+ if ((temp & mask) == 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[RD] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
+"clz r<RD>, r<RS>"
+*mips32:
+*mips64:
+{
+ unsigned32 temp = GPR[RS];
+ unsigned32 i, mask;
+ if (RT != RD)
+ Unpredictable();
+ TRACE_ALU_INPUT1 (GPR[RS]);
+ for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ {
+ if ((temp & mask) != 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[RD] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
"dadd r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
+011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
+"dclo r<RD>, r<RS>"
+*mips64:
+{
+ unsigned64 temp = GPR[RS];
+ unsigned32 i;
+ unsigned64 mask;
+ check_u64 (SD_, instruction_0);
+ if (RT != RD)
+ Unpredictable();
+ TRACE_ALU_INPUT1 (GPR[RS]);
+ for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ {
+ if ((temp & mask) == 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[RD] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
+"dclz r<RD>, r<RS>"
+*mips64:
+{
+ unsigned64 temp = GPR[RS];
+ unsigned32 i;
+ unsigned64 mask;
+ check_u64 (SD_, instruction_0);
+ if (RT != RD)
+ Unpredictable();
+ TRACE_ALU_INPUT1 (GPR[RS]);
+ for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ {
+ if ((temp & mask) != 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[RD] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
:function:::void:do_ddiv:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
{
check_u64 (SD_, instruction_0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
{
check_u64 (SD_, instruction_0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
}
+
+011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
+"madd r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ signed64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
+"maddu r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ unsigned64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
:function:::void:do_mfhi:int rd
{
check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
if (GPR[RT] != 0)
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
if (GPR[RT] == 0)
+011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
+"msub r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ signed64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
+"msubu r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ unsigned64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
*mipsI:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
+011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
+"mul r<RD>, r<RS>, r<RT>"
+*mips32:
+*mips64:
+{
+ signed64 prod;
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ prod = (((signed64)(signed32) GPR[RS])
+ * ((signed64)(signed32) GPR[RT]));
+ GPR[RD] = EXTEND32 (VL4_8 (prod));
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
:function:::void:do_mult:int rs, int rt, int rd
{
signed64 prod;
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"pref <HINT>, <OFFSET>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
address_word base = GPR[BASE];
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
"nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI:
do_sll (SD_, RT, RD, SHIFT);
}
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
+"nop":RD == 0 && RT == 0 && SHIFT == 0
+"ssnop":RD == 0 && RT == 0 && SHIFT == 1
+"sll r<RD>, r<RT>, <SHIFT>"
+*mips32:
+*mips64:
+{
+ /* Skip shift for NOP and SSNOP, so that there won't be lots of
+ extraneous trace output. */
+ if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
+ do_sll (SD_, RT, RD, SHIFT);
+}
+
:function:::void:do_sllv:int rs, int rt, int rd
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*r3900:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsII:
*mipsIII:
*mipsIV:
-*mipsV:
+*mips32:
*vr4100:
*vr5000:
*r3900:
{
/* None of these ISAs support Paired Single, so just fall back to
the single/double check. */
- /* XXX FIXME: not true for mipsV, but we don't support .ps insns yet. */
check_fmt (SD_, fmt, insn);
}
+:function:::void:check_fmt_p:int fmt, instruction_word insn
+*mipsV:
+*mips64:
+{
+#if 0 /* XXX FIXME: FP code doesn't yet support paired single ops. */
+ if ((fmt != fmt_single) && (fmt != fmt_double)
+ && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
+ SignalException (ReservedInstruction, insn);
+#else
+ check_fmt (SD_, fmt, insn);
+#endif
+}
+
// Helper:
//
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
#*vr4100:
*vr5000:
*r3900:
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"c%s<X>c1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"dm%s<X>c1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"m%s<X>c1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
int fmt = FMT;
"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
address_word base = GPR[BASE];
"recip.%s<FMT> f<FD>, f<FS>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
int fmt = FMT;
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
*mipsIV:
*mipsV:
+*mips64:
"rsqrt.%s<FMT> f<FD>, f<FS>"
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
check_fpu (SD_);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*r3900:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000: