// -*- C -*-
//
-// In mips.igen, the semantics for many of the instructions were created
-// using code generated by gencode. Those semantic segments could be
-// greatly simplified.
-//
// <insn> ::=
// <insn-word> { "+" <insn-word> }
// ":" <format-name>
:model:::mipsIII:mips4000:
:model:::mipsIV:mips8000:
:model:::mipsV:mipsisaV:
+:model:::mips32:mipsisa32:
+:model:::mips64:mipsisa64:
// Vendor ISAs:
//
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
+:model:::vr4120:mips4120:
:model:::vr5000:mips5000:
+:model:::vr5400:mips5400:
+:model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
//
// Instructions for the ASEs are in separate .igen files.
+// ASEs add instructions on to a base ISA.
:model:::mips16:mips16: // m16.igen (and m16.dc)
+:model:::mips3d:mips3d: // mips3d.igen
+:model:::mdmx:mdmx: // mdmx.igen
+
+// Vendor Extensions
+//
+// Instructions specific to these extensions are in separate .igen files.
+// Extensions add instructions on to a base ISA.
+:model:::sb1:sb1: // sb1.igen
// Pseudo instructions known by IGEN
return CIA + 8;
}
+
+// Helper:
+//
+// Calculate an effective address given a base and an offset.
+//
+
+:function:::address_word:loadstore_ea:address_word base, address_word offset
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*mips32:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ return base + offset;
+}
+
+:function:::address_word:loadstore_ea:address_word base, address_word offset
+*mips64:
+{
+#if 0 /* XXX FIXME: enable this only after some additional testing. */
+ /* If in user mode and UX is not set, use 32-bit compatibility effective
+ address computations as defined in the MIPS64 Architecture for
+ Programmers Volume III, Revision 0.95, section 4.9. */
+ if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
+ == (ksu_user << status_KSU_shift))
+ return (address_word)((signed32)base + (signed32)offset);
+#endif
+ return base + offset;
+}
+
+
+// Helper:
+//
+// Check that a 32-bit register value is properly sign-extended.
+// (See NotWordValue in ISA spec.)
+//
+
+:function:::int:not_word_value:unsigned_word value
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ /* For historical simulator compatibility (until documentation is
+ found that makes these operations unpredictable on some of these
+ architectures), this check never returns true. */
+ return 0;
+}
+
+:function:::int:not_word_value:unsigned_word value
+*mips32:
+{
+ /* On MIPS32, since registers are 32-bits, there's no check to be done. */
+ return 0;
+}
+
+:function:::int:not_word_value:unsigned_word value
+*mips64:
+{
+ return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
+}
+
+
+// Helper:
+//
+// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
+// theoretically portable code which invokes non-portable behaviour from
+// running with no indication of the portability issue.
+// (See definition of UNPREDICTABLE in ISA spec.)
+//
+
+:function:::void:unpredictable:
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+}
+
+:function:::void:unpredictable:
+*mips32:
+*mips64:
+{
+ unpredictable_action (CPU, CIA);
+}
+
+
// Helper:
-//
+//
// Check that an access to a HI/LO register meets timing requirements
//
// The following requirements exist:
sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
itable[MY_INDEX].name,
new, (long) CIA,
- (long) history->mf.cia);
+ (long) history->mf.cia);
return 0;
}
return 1;
}
:function:::int:check_mt_hilo:hilo_history *history
+*mips32:
+*mips64:
*r3900:
{
signed64 time = sim_events_time (SD);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
itable[MY_INDEX].name,
(long) CIA,
(long) history->op.cia,
- (long) peer->mt.cia);
+ (long) peer->mt.cia);
ok = 0;
}
history->mf.timestamp = time;
// The r3900 mult and multu insns _can_ be exectuted immediatly after
// a mf{hi,lo}
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mips32:
+*mips64:
*r3900:
{
/* FIXME: could record the fact that a stall occured if we want */
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
// Helper:
-//
+//
// Check that the 64-bit instruction can currently be used, and signal
-// an ReservedInstruction exception if not.
+// a ReservedInstruction exception if not.
//
:function:::void:check_u64:instruction_word insn
*vr4100:
*vr5000:
{
- // On mips64, if UserMode check SR:PX & SR:UX bits.
// The check should be similar to mips64 for any with PX/UX bit equivalents.
}
+:function:::void:check_u64:instruction_word insn
+*mips64:
+{
+#if 0 /* XXX FIXME: enable this only after some additional testing. */
+ if (UserMode && (SR & (status_UX|status_PX)) == 0)
+ SignalException (ReservedInstruction, insn);
+#endif
+}
+
//
// MIPS Architecture:
//
-// CPU Instruction Set (mipsI - mipsV)
+// CPU Instruction Set (mipsI - mipsV, mips32, mips64)
//
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU32_BEGIN (GPR[RS]);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
+ if (NotWordValue (GPR[RS]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
{
ALU32_BEGIN (GPR[RS]);
:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
{
+ if (NotWordValue (GPR[rs]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
TRACE_ALU_RESULT (GPR[rt]);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
:function:::void:do_addu:int rs, int rt, int rd
{
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
-"and r<RT>, r<RS>, <IMMEDIATE>"
+"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
+ if (RS == 31)
+ Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
+ if (RS == 31)
+ Unpredictable ();
RA = (CIA + 8);
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
+ if (RS == 31)
+ Unpredictable ();
RA = (CIA + 8);
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
+ if (RS == 31)
+ Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
000000,20.CODE,001101:SPECIAL:32::BREAK
-"break <CODE>"
+"break %#lx<CODE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
PC = cia - 4; /* reference the branch instruction */
else
PC = cia;
- SignalException(BreakPoint, instruction_0);
+ SignalException (BreakPoint, instruction_0);
}
else
{
- /* If we get this far, we're not an instruction reserved by the sim. Raise
+ /* If we get this far, we're not an instruction reserved by the sim. Raise
the exception. */
- SignalException(BreakPoint, instruction_0);
+ SignalException (BreakPoint, instruction_0);
+ }
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
+"clo r<RD>, r<RS>"
+*mips32:
+*mips64:
+*vr5500:
+{
+ unsigned32 temp = GPR[RS];
+ unsigned32 i, mask;
+ if (RT != RD)
+ Unpredictable ();
+ if (NotWordValue (GPR[RS]))
+ Unpredictable ();
+ TRACE_ALU_INPUT1 (GPR[RS]);
+ for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ {
+ if ((temp & mask) == 0)
+ break;
+ mask >>= 1;
}
+ GPR[RD] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
+"clz r<RD>, r<RS>"
+*mips32:
+*mips64:
+*vr5500:
+{
+ unsigned32 temp = GPR[RS];
+ unsigned32 i, mask;
+ if (RT != RD)
+ Unpredictable ();
+ if (NotWordValue (GPR[RS]))
+ Unpredictable ();
+ TRACE_ALU_INPUT1 (GPR[RS]);
+ for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ {
+ if ((temp & mask) != 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[RD] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[RD]);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
+011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
+"dclo r<RD>, r<RS>"
+*mips64:
+*vr5500:
+{
+ unsigned64 temp = GPR[RS];
+ unsigned32 i;
+ unsigned64 mask;
+ check_u64 (SD_, instruction_0);
+ if (RT != RD)
+ Unpredictable ();
+ TRACE_ALU_INPUT1 (GPR[RS]);
+ for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ {
+ if ((temp & mask) == 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[RD] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
+011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
+"dclz r<RD>, r<RS>"
+*mips64:
+*vr5500:
+{
+ unsigned64 temp = GPR[RS];
+ unsigned32 i;
+ unsigned64 mask;
+ check_u64 (SD_, instruction_0);
+ if (RT != RD)
+ Unpredictable ();
+ TRACE_ALU_INPUT1 (GPR[RS]);
+ for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ {
+ if ((temp & mask) != 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[RD] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
:function:::void:do_ddiv:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
- else
- {
- LO = EXTEND32 (n / d);
- HI = EXTEND32 (n % d);
- }
+ else
+ {
+ LO = EXTEND32 (n / d);
+ HI = EXTEND32 (n % d);
+ }
}
TRACE_ALU_RESULT2 (HI, LO);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
unsigned64 op2 = GPR[rt];
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- /* make signed multiply unsigned */
+ /* make signed multiply unsigned */
sign = 0;
if (signed_p)
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
{
check_u64 (SD_, instruction_0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
{
check_u64 (SD_, instruction_0);
:function:::void:do_dsll:int rt, int rd, int shift
{
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = GPR[rt] << shift;
+ TRACE_ALU_RESULT (GPR[rd]);
}
-:function:::void:do_dsllv:int rs, int rt, int rd
-{
- int s = MASKED64 (GPR[rs], 5, 0);
- GPR[rd] = GPR[rt] << s;
-}
-
-
000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
+ TRACE_ALU_INPUT2 (GPR[RT], s);
GPR[RD] = GPR[RT] << s;
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+:function:::void:do_dsllv:int rs, int rt, int rd
+{
+ int s = MASKED64 (GPR[rs], 5, 0);
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = GPR[rt] << s;
+ TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
:function:::void:do_dsra:int rt, int rd, int shift
{
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = ((signed64) GPR[rt]) >> shift;
+ TRACE_ALU_RESULT (GPR[rd]);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
-"dsra32 r<RT>, r<RD>, <SHIFT>"
+"dsra32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
+ TRACE_ALU_INPUT2 (GPR[RT], s);
GPR[RD] = ((signed64) GPR[RT]) >> s;
+ TRACE_ALU_RESULT (GPR[RD]);
}
}
000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
-"dsrav r<RT>, r<RD>, r<RS>"
+"dsrav r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
:function:::void:do_dsrl:int rt, int rd, int shift
{
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = (unsigned64) GPR[rt] >> shift;
+ TRACE_ALU_RESULT (GPR[rd]);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
+ TRACE_ALU_INPUT2 (GPR[RT], s);
GPR[RD] = (unsigned64) GPR[RT] >> s;
+ TRACE_ALU_RESULT (GPR[RD]);
}
:function:::void:do_dsrlv:int rs, int rt, int rd
{
int s = MASKED64 (GPR[rs], 5, 0);
+ TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = (unsigned64) GPR[rt] >> s;
+ TRACE_ALU_RESULT (GPR[rd]);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
unsigned64 memval;
address_word vaddr;
- vaddr = base + offset;
+ vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0)
{
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
unsigned_word lhs_mask;
unsigned_word temp;
- vaddr = base + offset;
+ vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0)
unsigned64 memval;
address_word vaddr;
- vaddr = base + offset;
+ vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
paddr = (paddr ^ (reverseendian & mask));
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ address_word base = GPR[BASE];
+ address_word offset = EXTEND16 (OFFSET);
{
- address_word vaddr = ((unsigned64)op1 + offset);
+ address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
+ GPR[RT] = EXTEND32 (memval >> (8 * byte));
LLBIT = 1;
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ address_word base = GPR[BASE];
+ address_word offset = EXTEND16 (OFFSET);
check_u64 (SD_, instruction_0);
{
- address_word vaddr = ((unsigned64)op1 + offset);
+ address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
if ((vaddr & 7) != 0)
unsigned64 memval = 0;
unsigned64 memval1 = 0;
LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
+ GPR[RT] = memval;
LLBIT = 1;
}
}
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
-"lui r<RT>, <IMMEDIATE>"
+"lui r<RT>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
}
-100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
+100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
"lwu r<RT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
}
+
+011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
+"madd r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+ signed64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
+"maddu r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+ unsigned64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
:function:::void:do_mfhi:int rd
{
check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
if (GPR[RT] != 0)
- GPR[RD] = GPR[RS];
+ {
+ GPR[RD] = GPR[RS];
+ TRACE_ALU_RESULT (GPR[RD]);
+ }
}
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
if (GPR[RT] == 0)
- GPR[RD] = GPR[RS];
+ {
+ GPR[RD] = GPR[RS];
+ TRACE_ALU_RESULT (GPR[RD]);
+ }
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
+"msub r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+ signed64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
+
+011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
+"msubu r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+ unsigned64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
+011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
+"mul r<RD>, r<RS>, r<RT>"
+*mips32:
+*mips64:
+*vr5500:
+{
+ signed64 prod;
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ prod = (((signed64)(signed32) GPR[RS])
+ * ((signed64)(signed32) GPR[RT]));
+ GPR[RD] = EXTEND32 (VL4_8 (prod));
+ TRACE_ALU_RESULT (GPR[RD]);
+}
+
+
+
:function:::void:do_mult:int rs, int rt, int rd
{
signed64 prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
prod = (((signed64)(signed32) GPR[rs])
* ((signed64)(signed32) GPR[rt]));
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
{
unsigned64 prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
prod = (((unsigned64)(unsigned32) GPR[rs])
* ((unsigned64)(unsigned32) GPR[rt]));
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
}
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
-"ori r<RT>, r<RS>, <IMMEDIATE>"
+"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
}
-110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
+110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
+"pref <HINT>, <OFFSET>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int hint = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ address_word base = GPR[BASE];
+ address_word offset = EXTEND16 (OFFSET);
{
- address_word vaddr = ((unsigned64)op1 + offset);
+ address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
{
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- Prefetch(uncached,paddr,vaddr,isDATA,hint);
+ Prefetch(uncached,paddr,vaddr,isDATA,HINT);
}
}
}
unsigned64 memval;
address_word vaddr;
- vaddr = base + offset;
+ vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0)
{
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
int nr_lhs_bits;
int nr_rhs_bits;
- vaddr = base + offset;
+ vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0)
unsigned64 memval;
address_word vaddr;
- vaddr = base + offset;
+ vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem != 0)
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ address_word base = GPR[BASE];
+ address_word offset = EXTEND16 (OFFSET);
{
- address_word vaddr = ((unsigned64)op1 + offset);
+ address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
+ memval = ((unsigned64) GPR[RT] << (8 * byte));
if (LLBIT)
{
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
}
- GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
+ GPR[RT] = LLBIT;
}
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ address_word base = GPR[BASE];
+ address_word offset = EXTEND16 (OFFSET);
check_u64 (SD_, instruction_0);
{
- address_word vaddr = ((unsigned64)op1 + offset);
+ address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
if ((vaddr & 7) != 0)
{
unsigned64 memval = 0;
unsigned64 memval1 = 0;
- memval = op2;
+ memval = GPR[RT];
if (LLBIT)
{
StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
}
- GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
+ GPR[RT] = LLBIT;
}
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
TRACE_ALU_RESULT (GPR[rd]);
}
-000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
"nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI:
do_sll (SD_, RT, RD, SHIFT);
}
+000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
+"nop":RD == 0 && RT == 0 && SHIFT == 0
+"ssnop":RD == 0 && RT == 0 && SHIFT == 1
+"sll r<RD>, r<RT>, <SHIFT>"
+*mips32:
+*mips64:
+{
+ /* Skip shift for NOP and SSNOP, so that there won't be lots of
+ extraneous trace output. */
+ if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
+ do_sll (SD_, RT, RD, SHIFT);
+}
+
:function:::void:do_sllv:int rs, int rt, int rd
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
:function:::void:do_sra:int rt, int rd, int shift
{
signed32 temp = (signed32) GPR[rt] >> shift;
+ if (NotWordValue (GPR[rt]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
int s = MASKED (GPR[rs], 4, 0);
signed32 temp = (signed32) GPR[rt] >> s;
+ if (NotWordValue (GPR[rt]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
:function:::void:do_srl:int rt, int rd, int shift
{
unsigned32 temp = (unsigned32) GPR[rt] >> shift;
+ if (NotWordValue (GPR[rt]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
int s = MASKED (GPR[rs], 4, 0);
unsigned32 temp = (unsigned32) GPR[rt] >> s;
+ if (NotWordValue (GPR[rt]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU32_BEGIN (GPR[RS]);
:function:::void:do_subu:int rs, int rt, int rd
{
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
TRACE_ALU_RESULT (GPR[rd]);
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*r3900:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
000000,20.CODE,001100:SPECIAL:32::SYSCALL
-"syscall <CODE>"
+"syscall %#lx<CODE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- SignalException(SystemCall, instruction_0);
+ SignalException (SystemCall, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
-"tne r<RS>, <IMMEDIATE>"
+"tnei r<RS>, <IMMEDIATE>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
- SignalException(Trap, instruction_0);
+ SignalException (Trap, instruction_0);
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
}
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
-"xori r<RT>, r<RS>, <IMMEDIATE>"
+"xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
case fmt_double: return "d";
case fmt_word: return "w";
case fmt_long: return "l";
- default: return "?";
- }
-}
-
-:%s::::X:int x
-{
- switch (x)
- {
- case 0: return "f";
- case 1: return "t";
+ case fmt_ps: return "ps";
default: return "?";
}
}
}
}
-// Helper:
-//
-// Check that the FPU is currently usable, and signal a CoProcessorUnusable
-// exception if not.
+
+// Helpers:
+//
+// Check that the given FPU format is usable, and signal a
+// ReservedInstruction exception if not.
//
-:function:::void:check_fpu:
-*mipsI:
+// check_fmt checks that the format is single or double.
+:function:::void:check_fmt:int fmt, instruction_word insn
+*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
-#if 0 /* XXX FIXME: For now, never treat the FPU as disabled. */
- if (! COP_Usable (1))
- SignalExceptionCoProcessorUnusable (1);
-#endif
+ if ((fmt != fmt_single) && (fmt != fmt_double))
+ SignalException (ReservedInstruction, insn);
}
-
-010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
-"abs.%s<FMT> f<FD>, f<FS>"
+// check_fmt_p checks that the format is single, double, or paired single.
+:function:::void:check_fmt_p:int fmt, instruction_word insn
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-*mipsV:
+*mips32:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
- }
+ /* None of these ISAs support Paired Single, so just fall back to
+ the single/double check. */
+ check_fmt (SD_, fmt, insn);
+}
+
+:function:::void:check_fmt_p:int fmt, instruction_word insn
+*mipsV:
+*mips64:
+{
+ if ((fmt != fmt_single) && (fmt != fmt_double)
+ && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
+ SignalException (ReservedInstruction, insn);
}
+// Helper:
+//
+// Check that the FPU is currently usable, and signal a CoProcessorUnusable
+// exception if not.
+//
-010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
-"add.%s<FMT> f<FD>, f<FS>, f<FT>"
+:function:::void:check_fpu:
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction, instruction);
- else
- StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
- }
+ if (! COP_Usable (1))
+ SignalExceptionCoProcessorUnusable (1);
}
+// Helper:
+//
+// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32. do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
-// BC1F
-// BC1FL
-// BC1T
-// BC1TL
-
-010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
-"bc1%s<TF>%s<ND> <OFFSET>"
-*mipsI:
+:function:::unsigned64:do_load_double:address_word base, address_word offset
*mipsII:
-*mipsIII:
+*mips32:
{
- check_fpu(SD_);
- check_branch_bug ();
- TRACE_BRANCH_INPUT (PREVCOC1());
- if (PREVCOC1() == TF)
+ int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+ address_word vaddr;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ unsigned64 v;
+
+ vaddr = loadstore_ea (SD_, base, offset);
+ if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
+ AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
+ sim_core_unaligned_signal);
+ }
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
+ isREAL);
+ LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
+ isDATA, isREAL);
+ v = (unsigned64)memval;
+ LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
+ isDATA, isREAL);
+ return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
+}
+
+
+// Helper:
+//
+// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32. do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
+*mipsII:
+*mips32:
+{
+ int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+ address_word vaddr;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+
+ vaddr = loadstore_ea (SD_, base, offset);
+ if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
+ AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
+ sim_core_unaligned_signal);
+ }
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
+ isREAL);
+ memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
+ StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
+ isREAL);
+ memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
+ StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
+ isREAL);
+}
+
+
+010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
+"abs.%s<FMT> f<FD>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*mips32:
+*mips64:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
+}
+
+
+
+010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
+"add.%s<FMT> f<FD>, f<FS>, f<FT>"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*mips32:
+*mips64:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
+}
+
+
+010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
+"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
+*mipsV:
+*mips64:
+{
+ unsigned64 fs;
+ unsigned64 ft;
+ unsigned64 fd;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ fs = ValueFPR (FS, fmt_ps);
+ if ((GPR[RS] & 0x3) != 0)
+ Unpredictable ();
+ if ((GPR[RS] & 0x4) == 0)
+ fd = fs;
+ else
+ {
+ ft = ValueFPR (FT, fmt_ps);
+ if (BigEndianCPU)
+ fd = PackPS (PSLower (fs), PSUpper (ft));
+ else
+ fd = PackPS (PSLower (ft), PSUpper (fs));
+ }
+ StoreFPR (FD, fmt_ps, fd);
+}
+
+
+// BC1F
+// BC1FL
+// BC1T
+// BC1TL
+
+010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
+"bc1%s<TF>%s<ND> <OFFSET>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+ check_fpu (SD_);
+ TRACE_BRANCH_INPUT (PREVCOC1());
+ if (PREVCOC1() == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
TRACE_BRANCH_RESULT (dest);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
#*vr4100:
*vr5000:
*r3900:
{
- check_fpu(SD_);
- check_branch_bug ();
+ check_fpu (SD_);
if (GETFCC(CC) == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
}
-
-
-
-
-// C.EQ.S
-// C.EQ.D
-// ...
-
-:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
-{
- if ((fmt != fmt_single) && (fmt != fmt_double))
- SignalException (ReservedInstruction, insn);
- else
- {
- int less;
- int equal;
- int unordered;
- int condition;
- unsigned64 ofs = ValueFPR (fs, fmt);
- unsigned64 oft = ValueFPR (ft, fmt);
- if (NaN (ofs, fmt) || NaN (oft, fmt))
- {
- if (FCSR & FP_ENABLE (IO))
- {
- FCSR |= FP_CAUSE (IO);
- SignalExceptionFPE ();
- }
- less = 0;
- equal = 0;
- unordered = 1;
- }
- else
- {
- less = Less (ofs, oft, fmt);
- equal = Equal (ofs, oft, fmt);
- unordered = 0;
- }
- condition = (((cond & (1 << 2)) && less)
- || ((cond & (1 << 1)) && equal)
- || ((cond & (1 << 0)) && unordered));
- SETFCC (cc, condition);
- }
-}
-
-010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
+010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIII:
{
- check_fpu(SD_);
- do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
+ TRACE_ALU_RESULT (ValueFCR (31));
}
-010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
+010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- check_fpu(SD_);
- do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
+ TRACE_ALU_RESULT (ValueFCR (31));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
"ceil.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
+ fmt_long));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
+010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
+"ceil.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
-// CFC1
-// CTC1
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
+"cfc1 r<RT>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
{
- check_fpu(SD_);
- if (X)
- {
- if (FS == 0)
- PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
- else if (FS == 31)
- PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
- /* else NOP */
- PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
- }
- else
- { /* control from */
- if (FS == 0)
- PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
- else if (FS == 31)
- PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
- /* else NOP */
- }
+ check_fpu (SD_);
+ if (FS == 0)
+ PENDING_FILL (RT, EXTEND32 (FCR0));
+ else if (FS == 31)
+ PENDING_FILL (RT, EXTEND32 (FCR31));
+ /* else NOP */
}
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
+"cfc1 r<RT>, f<FS>"
*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
*r3900:
{
- check_fpu(SD_);
- if (X)
+ check_fpu (SD_);
+ if (FS == 0 || FS == 31)
{
- /* control to */
- TRACE_ALU_INPUT1 (GPR[RT]);
- if (FS == 0)
- {
- FCR0 = VL4_8(GPR[RT]);
- TRACE_ALU_RESULT (FCR0);
- }
- else if (FS == 31)
- {
- FCR31 = VL4_8(GPR[RT]);
- SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
- TRACE_ALU_RESULT (FCR31);
- }
- else
- {
- TRACE_ALU_RESULT0 ();
- }
- /* else NOP */
+ unsigned_word fcr = ValueFCR (FS);
+ TRACE_ALU_INPUT1 (fcr);
+ GPR[RT] = fcr;
}
- else
- { /* control from */
- if (FS == 0)
- {
- TRACE_ALU_INPUT1 (FCR0);
- GPR[RT] = SIGNEXTEND (FCR0, 32);
- }
- else if (FS == 31)
- {
- TRACE_ALU_INPUT1 (FCR31);
- GPR[RT] = SIGNEXTEND (FCR31, 32);
- }
- TRACE_ALU_RESULT (GPR[RT]);
- /* else NOP */
+ /* else NOP */
+ TRACE_ALU_RESULT (GPR[RT]);
+}
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
+"cfc1 r<RT>, f<FS>"
+*mipsV:
+*mips32:
+*mips64:
+{
+ check_fpu (SD_);
+ if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
+ {
+ unsigned_word fcr = ValueFCR (FS);
+ TRACE_ALU_INPUT1 (fcr);
+ GPR[RT] = fcr;
}
+ /* else NOP */
+ TRACE_ALU_RESULT (GPR[RT]);
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
+"ctc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+ check_fpu (SD_);
+ if (FS == 31)
+ PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
+ /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
+"ctc1 r<RT>, f<FS>"
+*mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ check_fpu (SD_);
+ TRACE_ALU_INPUT1 (GPR[RT]);
+ if (FS == 31)
+ StoreFCR (FS, GPR[RT]);
+ /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
+"ctc1 r<RT>, f<FS>"
+*mipsV:
+*mips32:
+*mips64:
+{
+ check_fpu (SD_);
+ TRACE_ALU_INPUT1 (GPR[RT]);
+ if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
+ StoreFCR (FS, GPR[RT]);
+ /* else NOP */
}
//
// FIXME: Does not correctly differentiate between mips*
//
-010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format == fmt_double) | 0)
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ if ((fmt == fmt_double) | 0)
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+ fmt_double));
}
-010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
"cvt.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+ fmt_long));
+}
+
+
+010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
+"cvt.ps.s f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips64:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
+ ValueFPR (FT, fmt_single)));
}
//
// FIXME: Does not correctly differentiate between mips*
//
-010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
+010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
"cvt.s.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format == fmt_single) | 0)
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ if ((fmt == fmt_single) | 0)
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+ fmt_single));
+}
+
+
+010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
+"cvt.s.pl f<FD>, f<FS>"
+*mipsV:
+*mips64:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
}
-010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
+010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
+"cvt.s.pu f<FD>, f<FS>"
+*mipsV:
+*mips64:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
+}
+
+
+010001,10,3.FMT!6,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
"cvt.w.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
-010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
+010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
}
-// DMFC1
-// DMTC1
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
+"dmfc1 r<RT>, f<FS>"
*mipsIII:
{
- check_fpu(SD_);
+ unsigned64 v;
+ check_fpu (SD_);
check_u64 (SD_, instruction_0);
- if (X)
- {
- if (SizeFGR() == 64)
- PENDING_FILL((FS + FGRIDX),GPR[RT]);
- else if ((FS & 0x1) == 0)
- {
- PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
- PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
- }
- }
+ if (SizeFGR () == 64)
+ v = FGR[FS];
+ else if ((FS & 0x1) == 0)
+ v = SET64HI (FGR[FS+1]) | FGR[FS];
else
- {
- if (SizeFGR() == 64)
- PENDING_FILL(RT,FGR[FS]);
- else if ((FS & 0x1) == 0)
- PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
- else
- {
- if (STATE_VERBOSE_P(SD))
- sim_io_eprintf (SD,
- "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
- (long) CIA);
- PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
- }
- }
+ v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+ PENDING_FILL (RT, v);
+ TRACE_ALU_RESULT (v);
}
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
+"dmfc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- check_fpu(SD_);
+ check_fpu (SD_);
check_u64 (SD_, instruction_0);
- if (X)
- {
- if (SizeFGR() == 64)
- StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
- else if ((FS & 0x1) == 0)
- StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
- }
+ if (SizeFGR () == 64)
+ GPR[RT] = FGR[FS];
+ else if ((FS & 0x1) == 0)
+ GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
else
+ GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+ TRACE_ALU_RESULT (GPR[RT]);
+}
+
+
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
+"dmtc1 r<RT>, f<FS>"
+*mipsIII:
+{
+ unsigned64 v;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ if (SizeFGR () == 64)
+ PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
+ else if ((FS & 0x1) == 0)
{
- if (SizeFGR() == 64)
- GPR[RT] = FGR[FS];
- else if ((FS & 0x1) == 0)
- GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
- else
- {
- if (STATE_VERBOSE_P(SD))
- sim_io_eprintf (SD,
- "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
- (long) CIA);
- GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
- }
+ PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
+ PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
}
+ else
+ Unpredictable ();
+ TRACE_FP_RESULT (GPR[RT]);
}
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
+"dmtc1 r<RT>, f<FS>"
+*mipsIV:
+*mipsV:
+*mips64:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ if (SizeFGR () == 64)
+ StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+ else if ((FS & 0x1) == 0)
+ StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+ else
+ Unpredictable ();
+}
-010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
+
+010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
"floor.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
+ fmt_long));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
"floor.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
-110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
"ldc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsI:
*mipsII:
+*mips32:
+{
+ check_fpu (SD_);
+ COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
+"ldc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- check_fpu(SD_);
+ check_fpu (SD_);
COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
-010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
+010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- check_fpu(SD_);
+ check_fpu (SD_);
check_u64 (SD_, instruction_0);
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
}
-110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
+110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- check_fpu(SD_);
+ check_fpu (SD_);
COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
-010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
+010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- check_fpu(SD_);
+ check_fpu (SD_);
check_u64 (SD_, instruction_0);
COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
}
-//
-// FIXME: Not correct for mips*
-//
-010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
-"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
+"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int fr = ((instruction >> 21) & 0x0000001F);
- check_fpu(SD_);
- {
- StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
- }
-}
-
-
-010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
-"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*vr5000:
-{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int fr = ((instruction >> 21) & 0x0000001F);
- check_fpu(SD_);
- {
- StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+ ValueFPR (FR, fmt), fmt));
}
-// MFC1
-// MTC1
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
+"mfc1 r<RT>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
{
- check_fpu(SD_);
- if (X)
- { /*MTC1*/
- if (SizeFGR() == 64)
- {
- if (STATE_VERBOSE_P(SD))
- sim_io_eprintf (SD,
- "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
- (long) CIA);
- PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
- }
- else
- PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
- }
- else /*MFC1*/
- PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
+ unsigned64 v;
+ check_fpu (SD_);
+ v = EXTEND32 (FGR[FS]);
+ PENDING_FILL (RT, v);
+ TRACE_ALU_RESULT (v);
}
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
+"mfc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
-{
- int fs = FS;
- check_fpu(SD_);
- if (X)
- /*MTC1*/
- StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
- else /*MFC1*/
- GPR[RT] = SIGNEXTEND(FGR[FS],32);
+{
+ check_fpu (SD_);
+ GPR[RT] = EXTEND32 (FGR[FS]);
+ TRACE_ALU_RESULT (GPR[RT]);
}
-010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- StoreFPR(destreg,format,ValueFPR(fs,format));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, ValueFPR (FS, fmt));
}
// MOVF
// MOVT
-000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32::MOVtf
+000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
- check_fpu(SD_);
+ check_fpu (SD_);
if (GETFCC(CC) == TF)
GPR[RD] = GPR[RS];
}
// MOVF.fmt
// MOVT.fmt
-010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
+010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if (GETFCC(CC) == TF)
- StoreFPR (FD, format, ValueFPR (FS, format));
- else
- StoreFPR (FD, format, ValueFPR (FD, format));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ if (fmt != fmt_ps)
+ {
+ if (GETFCC(CC) == TF)
+ StoreFPR (FD, fmt, ValueFPR (FS, fmt));
+ else
+ StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
+ }
+ else
+ {
+ unsigned64 fd;
+ fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
+ fmt_ps)),
+ PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
+ fmt_ps)));
+ StoreFPR (FD, fmt_ps, fd);
+ }
}
-010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
+010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
- check_fpu(SD_);
+ check_fpu (SD_);
if (GPR[RT] != 0)
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
else
-010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
+010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr5000:
{
- check_fpu(SD_);
+ check_fpu (SD_);
if (GPR[RT] == 0)
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
else
}
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
-"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
+"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int fr = ((instruction >> 21) & 0x0000001F);
- check_fpu(SD_);
- {
- StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+ ValueFPR (FR, fmt), fmt));
}
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
-"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
+"mtc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+ check_fpu (SD_);
+ if (SizeFGR () == 64)
+ PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
+ else
+ PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
+ TRACE_FP_RESULT (GPR[RT]);
+}
+
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
+"mtc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
+*vr4100:
*vr5000:
+*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int fr = ((instruction >> 21) & 0x0000001F);
- check_fpu(SD_);
- {
- StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
- }
+ check_fpu (SD_);
+ StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
}
-// MTC1 see MxC1
-
-
-010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
+010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
}
-010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
}
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
-"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
+"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int fr = ((instruction >> 21) & 0x0000001F);
- check_fpu(SD_);
- {
- StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+ ValueFPR (FR, fmt), fmt));
}
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
-"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
+"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int fr = ((instruction >> 21) & 0x0000001F);
- check_fpu(SD_);
- {
- StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+ ValueFPR (FR, fmt), fmt));
}
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
-"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
+"pll.ps f<FD>, f<FS>, f<FT>"
*mipsV:
-*vr5000:
+*mips64:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int fr = ((instruction >> 21) & 0x0000001F);
- check_fpu(SD_);
- {
- StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
- }
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
+ PSLower (ValueFPR (FT, fmt_ps))));
}
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
-"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
+"plu.ps f<FD>, f<FS>, f<FT>"
*mipsV:
-*vr5000:
+*mips64:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int fr = ((instruction >> 21) & 0x0000001F);
- check_fpu(SD_);
- {
- StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
- }
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
+ PSUpper (ValueFPR (FT, fmt_ps))));
}
-010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
+010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- int fs = ((instruction >> 11) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ address_word base = GPR[BASE];
+ address_word index = GPR[INDEX];
{
- address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
+ address_word vaddr = loadstore_ea (SD_, base, index);
address_word paddr;
int uncached;
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- Prefetch(uncached,paddr,vaddr,isDATA,fs);
+ Prefetch(uncached,paddr,vaddr,isDATA,HINT);
}
}
-010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
+
+010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
+"pul.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips64:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
+ PSLower (ValueFPR (FT, fmt_ps))));
+}
+
+
+010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
+"puu.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips64:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
+ PSUpper (ValueFPR (FT, fmt_ps))));
+}
+
+
+010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
"recip.%s<FMT> f<FD>, f<FS>"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
"round.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
+ fmt_long));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
"round.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
-010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
+"rsqrt.%s<FMT> f<FD>, f<FS>"
*mipsIV:
*mipsV:
-"rsqrt.%s<FMT> f<FD>, f<FS>"
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
}
-111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsI:
*mipsII:
+*mips32:
+{
+ check_fpu (SD_);
+ do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
+}
+
+
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
+"sdc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- check_fpu(SD_);
+ check_fpu (SD_);
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
}
-010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
-"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
+010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
+"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- check_fpu(SD_);
+ check_fpu (SD_);
check_u64 (SD_, instruction_0);
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
}
-010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
"sqrt.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
}
-010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
+010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int ft = ((instruction >> 16) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
}
-111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
+111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
"swc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = EXTEND16 (OFFSET);
- int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
- signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
- check_fpu(SD_);
+ address_word base = GPR[BASE];
+ address_word offset = EXTEND16 (OFFSET);
+ check_fpu (SD_);
{
- address_word vaddr = ((uword64)op1 + offset);
+ address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
- memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
+ memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
}
}
}
-010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
+010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips64:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- int fs = ((instruction >> 11) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- check_fpu(SD_);
+
+ address_word base = GPR[BASE];
+ address_word index = GPR[INDEX];
+ check_fpu (SD_);
check_u64 (SD_, instruction_0);
{
- address_word vaddr = ((unsigned64)op1 + op2);
+ address_word vaddr = loadstore_ea (SD_, base, index);
address_word paddr;
int uncached;
if ((vaddr & 3) != 0)
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
+ memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
{
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
}
}
-010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
+010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
"trunc.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
+ fmt_long));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
+010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
"trunc.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- int fs = ((instruction >> 11) & 0x0000001F);
- int format = ((instruction >> 21) & 0x00000007);
- check_fpu(SD_);
- {
- if ((format != fmt_single) && (format != fmt_double))
- SignalException(ReservedInstruction,instruction);
- else
- StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
- }
+ int fmt = FMT;
+ check_fpu (SD_);
+ check_fmt (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
\f
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
+"cache <OP>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int hint = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ address_word base = GPR[BASE];
+ address_word offset = EXTEND16 (OFFSET);
{
- address_word vaddr = (op1 + offset);
+ address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr;
int uncached;
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- CacheOp(hint,vaddr,paddr,instruction);
+ CacheOp(OP,vaddr,paddr,instruction_0);
}
}
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
*mipsIII:
*mipsIV:
*mipsV:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*r3900:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*r3900:
{
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
*mipsIII:
*mipsIV:
*mipsV:
+*mips32:
+*mips64:
*vr4100:
*vr5000:
\f
:include:::m16.igen
+:include:::mdmx.igen
+:include:::mips3d.igen
+:include:::sb1.igen
:include:::tx.igen
:include:::vr.igen
\f
projects / deliverable / binutils-gdb.git / blobdiff