2003-01-04 Richard Sandiford <rsandifo@redhat.com>

[deliverable/binutils-gdb.git] / sim / mips / mips.igen

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index a26436519978ce55e961ce2b3080671eb6a22869..fece487e10d6a3a9844b8b59fd12fdd57125796e 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -55,7 +55,10 @@
 //  (or which pre-date or use different encodings than the standard
 //  instructions) are (for the most part) in separate .igen files.
 :model:::vr4100:mips4100:              // vr.igen
+:model:::vr4120:mips4120:
 :model:::vr5000:mips5000:
+:model:::vr5400:mips5400:
+:model:::vr5500:mips5500:
 :model:::r3900:mips3900:               // tx.igen
 
 //  MIPS Application Specific Extensions (ASEs)
@@ -63,6 +66,7 @@
 //  Instructions for the ASEs are in separate .igen files.
 //  ASEs add instructions on to a base ISA.
 :model:::mips16:mips16:                        // m16.igen (and m16.dc)
+:model:::mips3d:mips3d:                        // mips3d.igen
 :model:::mdmx:mdmx:                    // mdmx.igen
 
 //  Vendor Extensions
@@ -564,10 +568,8 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -587,10 +589,8 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -613,10 +613,8 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] >= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -637,13 +635,11 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if (RS == 31)
     Unpredictable ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] >= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -663,7 +659,6 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if (RS == 31)
     Unpredictable ();
   RA = (CIA + 8);
@@ -671,7 +666,6 @@
      executed */
   if ((signed_word) GPR[RS] >= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -693,10 +687,8 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] >= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -719,10 +711,8 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] > 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -742,12 +732,10 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] > 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -770,12 +758,10 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] <= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -795,10 +781,8 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] <= 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -821,10 +805,8 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] < 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -845,7 +827,6 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if (RS == 31)
     Unpredictable ();
   RA = (CIA + 8);
@@ -853,7 +834,6 @@
      executed */
   if ((signed_word) GPR[RS] < 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -873,13 +853,11 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if (RS == 31)
     Unpredictable ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] < 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -901,12 +879,10 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] < 0)
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -929,10 +905,8 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
 }
@@ -952,10 +926,8 @@
 *r3900:
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  check_branch_bug ();
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
     {
-      mark_branch_bug (NIA+offset);
       DELAY_SLOT (NIA + offset);
     }
   else
@@ -1009,6 +981,7 @@
 "clo r<RD>, r<RS>"
 *mips32:
 *mips64:
+*vr5500:
 {
   unsigned32 temp = GPR[RS];
   unsigned32 i, mask;
@@ -1033,6 +1006,7 @@
 "clz r<RD>, r<RS>"
 *mips32:
 *mips64:
+*vr5500:
 {
   unsigned32 temp = GPR[RS];
   unsigned32 i, mask;
@@ -1142,6 +1116,7 @@
 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
 "dclo r<RD>, r<RS>"
 *mips64:
+*vr5500:
 {
   unsigned64 temp = GPR[RS];
   unsigned32 i;
@@ -1165,6 +1140,7 @@
 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
 "dclz r<RD>, r<RS>"
 *mips64:
+*vr5500:
 {
   unsigned64 temp = GPR[RS];
   unsigned32 i;
@@ -2188,6 +2164,7 @@
 "madd r<RS>, r<RT>"
 *mips32:
 *mips64:
+*vr5500:
 {
   signed64 temp;
   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2207,6 +2184,7 @@
 "maddu r<RS>, r<RT>"
 *mips32:
 *mips64:
+*vr5500:
 {
   unsigned64 temp;
   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2311,6 +2289,7 @@
 "msub r<RS>, r<RT>"
 *mips32:
 *mips64:
+*vr5500:
 {
   signed64 temp;
   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2330,6 +2309,7 @@
 "msubu r<RS>, r<RT>"
 *mips32:
 *mips64:
+*vr5500:
 {
   unsigned64 temp;
   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2387,6 +2367,7 @@
 "mul r<RD>, r<RS>, r<RT>"
 *mips32:
 *mips64:
+*vr5500:
 {
   signed64 prod;
   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
@@ -3640,6 +3621,77 @@
 }
 
 
+// Helper:
+//
+// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32.  do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::unsigned64:do_load_double:address_word base, address_word offset
+*mipsII:
+*mips32:
+{
+  int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+  address_word vaddr;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+  unsigned64 v;
+
+  vaddr = loadstore_ea (SD_, base, offset);
+  if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
+                      AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
+                      sim_core_unaligned_signal);
+    }
+  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
+                     isREAL);
+  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
+             isDATA, isREAL);
+  v = (unsigned64)memval;
+  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
+             isDATA, isREAL);
+  return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
+}
+
+
+// Helper:
+//
+// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32.  do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
+*mipsII:
+*mips32:
+{
+  int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+  address_word vaddr;
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+
+  vaddr = loadstore_ea (SD_, base, offset);
+  if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
+                      AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
+                      sim_core_unaligned_signal);
+    }
+  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
+                     isREAL);
+  memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
+  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
+              isREAL);
+  memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
+  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
+              isREAL);
+}
+
+
 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
 "abs.%s<FMT> f<FD>, f<FS>"
 *mipsI:
@@ -3720,13 +3772,11 @@
 *mipsIII:
 {
   check_fpu (SD_);
-  check_branch_bug ();
   TRACE_BRANCH_INPUT (PREVCOC1());
   if (PREVCOC1() == TF)
     {
       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
       TRACE_BRANCH_RESULT (dest);
-      mark_branch_bug (dest);
       DELAY_SLOT (dest);
     }
   else if (ND)
@@ -3752,11 +3802,9 @@
 *r3900:
 {
   check_fpu (SD_);
-  check_branch_bug ();
   if (GETFCC(CC) == TF)
     {
       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
-      mark_branch_bug (dest);
       DELAY_SLOT (dest);
     }
   else if (ND)
@@ -4028,7 +4076,7 @@
 }
 
 
-010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
+010001,10,3.FMT!6,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
 "cvt.w.%s<FMT> f<FD>, f<FS>"
 *mipsI:
 *mipsII:
@@ -4185,13 +4233,21 @@
 }
 
 
-110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsII:
+*mips32:
+{
+  check_fpu (SD_);
+  COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
+"ldc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
 *mipsV:
-*mips32:
 *mips64:
 *vr4100:
 *vr5000:
@@ -4649,13 +4705,21 @@
 }
 
 
-111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsII:
+*mips32:
+{
+  check_fpu (SD_);
+  do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
+}
+
+
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
+"sdc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
 *mipsV:
-*mips32:
 *mips64:
 *vr4100:
 *vr5000:
@@ -5123,6 +5187,7 @@
 \f
 :include:::m16.igen
 :include:::mdmx.igen
+:include:::mips3d.igen
 :include:::sb1.igen
 :include:::tx.igen
 :include:::vr.igen