2005-05-26 David Ung <davidu@mips.com>

[deliverable/binutils-gdb.git] / sim / mips / sim-main.c

diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c
index 7b3e6c61501b486b5fe84c1a687a9953ea92f4a7..edee498bc94c2ac494e018b8a463241d0081467a 100644 (file)
--- a/sim/mips/sim-main.c
+++ b/sim/mips/sim-main.c
@@ -163,35 +163,35 @@ load_memory (SIM_DESC SD,
 
   switch (AccessLength)
     {
-    case AccessLength_QUADWORD :
+    case AccessLength_QUADWORD:
       {
        unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
        value1 = VH8_16 (val);
        value = VL8_16 (val);
        break;
       }
-    case AccessLength_DOUBLEWORD :
+    case AccessLength_DOUBLEWORD:
       value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_SEPTIBYTE :
+    case AccessLength_SEPTIBYTE:
       value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_SEXTIBYTE :
+    case AccessLength_SEXTIBYTE:
       value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_QUINTIBYTE :
+    case AccessLength_QUINTIBYTE:
       value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_WORD :
+    case AccessLength_WORD:
       value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_TRIPLEBYTE :
+    case AccessLength_TRIPLEBYTE:
       value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_HALFWORD :
+    case AccessLength_HALFWORD:
       value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
       break;
-    case AccessLength_BYTE :
+    case AccessLength_BYTE:
       value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
       break;
     default:
@@ -292,34 +292,34 @@ store_memory (SIM_DESC SD,
   
   switch (AccessLength)
     {
-    case AccessLength_QUADWORD :
+    case AccessLength_QUADWORD:
       {
        unsigned_16 val = U16_8 (MemElem1, MemElem);
        sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
        break;
       }
-    case AccessLength_DOUBLEWORD :
+    case AccessLength_DOUBLEWORD:
       sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_SEPTIBYTE :
+    case AccessLength_SEPTIBYTE:
       sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_SEXTIBYTE :
+    case AccessLength_SEXTIBYTE:
       sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_QUINTIBYTE :
+    case AccessLength_QUINTIBYTE:
       sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_WORD :
+    case AccessLength_WORD:
       sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_TRIPLEBYTE :
+    case AccessLength_TRIPLEBYTE:
       sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_HALFWORD :
+    case AccessLength_HALFWORD:
       sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
       break;
-    case AccessLength_BYTE :
+    case AccessLength_BYTE:
       sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
       break;
     default: