-/* Simulator for the MIPS architecture.
+/* Copyright (C) 1998, Cygnus Solutions
- This file is part of the MIPS sim
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
- THIS SOFTWARE IS NOT COPYRIGHTED
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
- Cygnus offers the following for use in the public domain. Cygnus
- makes no warranty with regard to the software or it's performance
- and the user accepts the software "AS IS" with all faults.
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
- THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
- $Revision$
- $Date$
-
- */
#ifndef SIM_MAIN_C
#define SIM_MAIN_C
#include "sim-main.h"
-
-#if !(WITH_IGEN)
-#define SIM_MANIFESTS
-#include "oengine.c"
-#undef SIM_MANIFESTS
-#endif
+#include "sim-assert.h"
/*---------------------------------------------------------------------------*/
/*-- simulator engine -------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
+
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
(revision 3.1) */
/* Translate a virtual address to a physical address and cache
NOTE: Normally (RAW == 0), when address translation fails, this
function raises an exception and does not return. */
-INLINE_SIM_MAIN (int)
+INLINE_SIM_MAIN
+(int)
address_translation (SIM_DESC sd,
- sim_cpu *cpu,
+ sim_cpu * cpu,
address_word cia,
address_word vAddr,
int IorD,
int LorS,
- address_word *pAddr,
+ address_word * pAddr,
int *CCA,
int raw)
{
- int res = -1; /* TRUE : Assume good return */
+ int res = -1; /* TRUE : Assume good return */
#ifdef DEBUG
- sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
+ sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "isINSTRUCTION"), (LorS ? "iSTORE" : "isLOAD"));
#endif
/* Check that the address is valid for this memory model */
addressess through (mostly) unchanged. */
vAddr &= 0xFFFFFFFF;
- *pAddr = vAddr; /* default for isTARGET */
- *CCA = Uncached; /* not used for isHOST */
+ *pAddr = vAddr; /* default for isTARGET */
+ *CCA = Uncached; /* not used for isHOST */
- return(res);
+ return (res);
}
+
+
/* Description from page A-23 of the "MIPS IV Instruction Set" manual
(revision 3.1) */
/* Prefetch data from memory. Prefetch is an advisory instruction for
sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
#endif /* WARN_MEM */
- /* If instruction fetch then we need to check that the two lo-order
- bits are zero, otherwise raise a InstructionFetch exception: */
- if ((IorD == isINSTRUCTION)
- && ((pAddr & 0x3) != 0)
- && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
- SignalExceptionInstructionFetch ();
-
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
{
/* In reality this should be a Bus Error */
switch (AccessLength)
{
- case AccessLength_QUADWORD :
+ case AccessLength_QUADWORD:
{
- unsigned_16 val = sim_core_read_aligned_16 (CPU, NULL_CIA, read_map, pAddr);
+ unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
- case AccessLength_DOUBLEWORD :
- value = sim_core_read_aligned_8 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_DOUBLEWORD:
+ value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_SEPTIBYTE :
- value = sim_core_read_misaligned_7 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_SEPTIBYTE:
+ value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_SEXTIBYTE :
- value = sim_core_read_misaligned_6 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_SEXTIBYTE:
+ value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_QUINTIBYTE :
- value = sim_core_read_misaligned_5 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_QUINTIBYTE:
+ value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_WORD :
- value = sim_core_read_aligned_4 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_WORD:
+ value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_TRIPLEBYTE :
- value = sim_core_read_misaligned_3 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_TRIPLEBYTE:
+ value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_HALFWORD :
- value = sim_core_read_aligned_2 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_HALFWORD:
+ value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_BYTE :
- value = sim_core_read_aligned_1 (CPU, NULL_CIA,
- read_map, pAddr);
+ case AccessLength_BYTE:
+ value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
break;
default:
abort ();
switch (AccessLength)
{
- case AccessLength_QUADWORD :
+ case AccessLength_QUADWORD:
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
- sim_core_write_aligned_16 (CPU, NULL_CIA, write_map, pAddr, val);
+ sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
break;
}
- case AccessLength_DOUBLEWORD :
- sim_core_write_aligned_8 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_DOUBLEWORD:
+ sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_SEPTIBYTE :
- sim_core_write_misaligned_7 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_SEPTIBYTE:
+ sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_SEXTIBYTE :
- sim_core_write_misaligned_6 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_SEXTIBYTE:
+ sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_QUINTIBYTE :
- sim_core_write_misaligned_5 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_QUINTIBYTE:
+ sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_WORD :
- sim_core_write_aligned_4 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_WORD:
+ sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_TRIPLEBYTE :
- sim_core_write_misaligned_3 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_TRIPLEBYTE:
+ sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_HALFWORD :
- sim_core_write_aligned_2 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_HALFWORD:
+ sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_BYTE :
- sim_core_write_aligned_1 (CPU, NULL_CIA,
- write_map, pAddr, MemElem);
+ case AccessLength_BYTE:
+ sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
break;
default:
abort ();
address_word vaddr)
{
/* Copy the action of the LW instruction */
- address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
- address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
- unsigned64 value;
+ address_word mask = LOADDRMASK;
+ address_word access = AccessLength_WORD;
+ address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+ unsigned int byte;
address_word paddr;
- unsigned32 instruction;
- unsigned byte;
- int cca;
- AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
- paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
- LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
- byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
- return instruction;
+ int uncached;
+ unsigned64 memval;
+
+ if ((vaddr & access) != 0)
+ SignalExceptionInstructionFetch ();
+ AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ return (memval >> (8 * byte));
}
+INLINE_SIM_MAIN (unsigned16)
+ifetch16 (SIM_DESC SD,
+ sim_cpu *CPU,
+ address_word cia,
+ address_word vaddr)
+{
+ /* Copy the action of the LH instruction */
+ address_word mask = LOADDRMASK;
+ address_word access = AccessLength_HALFWORD;
+ address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+
+ if ((vaddr & access) != 0)
+ SignalExceptionInstructionFetch ();
+ AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ return (memval >> (8 * byte));
+}
+
+
+
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* Order loads and stores to synchronise shared memory. Perform the
action necessary to make the effects of groups of synchronizable
break;
case 1: /* data cache */
+ case 3: /* secondary data cache */
switch (op >> 2) {
case 0: /* Index Writeback Invalidate */
case 1: /* Index Load Tag */
address_word cia)
{
if (PENDING_TRACE)
- sim_io_printf (SD, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
+ sim_io_eprintf (SD, "PENDING_DRAIN - 0x%lx - pending_in = %d, pending_out = %d, pending_total = %d\n", (unsigned long) cia, PENDING_IN, PENDING_OUT, PENDING_TOTAL);
if (PENDING_OUT != PENDING_IN)
{
int loop;
int total = PENDING_TOTAL;
if (PENDING_TOTAL == 0)
sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
- for (loop = 0; (loop < total); loop++)
+ for (loop = 0, index = PENDING_OUT;
+ (loop < total);
+ loop++, index = (index + 1) % PSLOTS)
{
if (PENDING_SLOT_DEST[index] != NULL)
{
PENDING_SLOT_DELAY[index] -= 1;
if (PENDING_SLOT_DELAY[index] == 0)
{
+ if (PENDING_TRACE)
+ sim_io_eprintf (SD, "PENDING_DRAIN - drained - index %d, dest 0x%lx, bit %d, val 0x%lx, size %d\n",
+ index,
+ (unsigned long) PENDING_SLOT_DEST[index],
+ PENDING_SLOT_BIT[index],
+ (unsigned long) PENDING_SLOT_VALUE[index],
+ PENDING_SLOT_SIZE[index]);
if (PENDING_SLOT_BIT[index] >= 0)
switch (PENDING_SLOT_SIZE[index])
{
- case 32:
+ case 4:
if (PENDING_SLOT_VALUE[index])
*(unsigned32*)PENDING_SLOT_DEST[index] |=
BIT32 (PENDING_SLOT_BIT[index]);
*(unsigned32*)PENDING_SLOT_DEST[index] &=
BIT32 (PENDING_SLOT_BIT[index]);
break;
- case 64:
+ case 8:
if (PENDING_SLOT_VALUE[index])
*(unsigned64*)PENDING_SLOT_DEST[index] |=
BIT64 (PENDING_SLOT_BIT[index]);
*(unsigned64*)PENDING_SLOT_DEST[index] &=
BIT64 (PENDING_SLOT_BIT[index]);
break;
- break;
}
else
switch (PENDING_SLOT_SIZE[index])
{
- case 32:
+ case 4:
*(unsigned32*)PENDING_SLOT_DEST[index] =
PENDING_SLOT_VALUE[index];
break;
- case 64:
+ case 8:
*(unsigned64*)PENDING_SLOT_DEST[index] =
PENDING_SLOT_VALUE[index];
break;
}
+ if (PENDING_OUT == index)
+ {
+ PENDING_SLOT_DEST[index] = NULL;
+ PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
+ PENDING_TOTAL--;
+ }
}
- if (PENDING_OUT == index)
- {
- PENDING_SLOT_DEST[index] = NULL;
- PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
- PENDING_TOTAL--;
- }
+ else if (PENDING_TRACE && PENDING_SLOT_DELAY[index] > 0)
+ sim_io_eprintf (SD, "PENDING_DRAIN - queued - index %d, delay %d, dest 0x%lx, bit %d, val 0x%lx, size %d\n",
+ index, PENDING_SLOT_DELAY[index],
+ (unsigned long) PENDING_SLOT_DEST[index],
+ PENDING_SLOT_BIT[index],
+ (unsigned long) PENDING_SLOT_VALUE[index],
+ PENDING_SLOT_SIZE[index]);
+
}
}
- index = (index + 1) % PSLOTS;
}
}
projects / deliverable / binutils-gdb.git / blobdiff