#define WITH_WATCHPOINTS 1
#define WITH_MODULO_MEMORY 1
+
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
+
#include "sim-basics.h"
typedef address_word sim_cia;
instruction: */
#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
-#if 1
-#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
+#ifdef TARGET_ENABLE_FR
+/* FIXME: this should be enabled for all targets, but needs testing first. */
+#define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
+ ? ((SR & status_FR) ? 64 : 32) \
+ : (WITH_TARGET_FLOATING_POINT_BITSIZE))
#else
-/* They depend on the CPU being simulated */
-#define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
+#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
#endif
/* Standard FCRS bits: */
#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#ifdef SKY_FUNIT
-#include <assert.h>
-#include "wf.h"
-#endif
-#endif
-/* end-sanitize-sky */
(ANS) = ALU64_OVERFLOW_RESULT;
-/* start-sanitize-r5900 */
-
-/* Figure 10-5 FPU Control/Status Register.
- Note: some of these bits are different to what is found in a
- standard MIPS manual. */
-enum {
- R5900_FCSR_C = BIT (23), /* OK */
- R5900_FCSR_I = BIT (17),
- R5900_FCSR_D = BIT (16),
- R5900_FCSR_O = BIT (15),
- R5900_FCSR_U = BIT (14),
- R5900_FCSR_CAUSE = MASK (16,14),
- R5900_FCSR_SI = BIT (6),
- R5900_FCSR_SD = BIT (5),
- R5900_FCSR_SO = BIT (4),
- R5900_FCSR_SU = BIT (3),
-};
-
-/* Table 10-1 FP format values.
- Note: some of these bits are different to what is found in a
- standard MIPS manual. */
-enum {
- R5900_EXPMAX = 128,
- R5900_EXPMIN = -127,
- R5900_EXPBIAS = 127,
-};
-
-/* MAX and MIN FP values */
-enum {
- R5900_FPMAX = LSMASK32 (30, 0),
- R5900_FPMIN = LSMASK32 (31, 0),
-};
-
-typedef struct _r4000_tlb_entry {
- unsigned32 mask;
- unsigned32 hi;
- unsigned32 lo0;
- unsigned32 lo1;
-} r4000_tlb_entry_t;
-
-#define TLB_MASK_MASK_MASK 0x01ffe000
-#define TLB_HI_VPN2_MASK 0xffffe000
-#define TLB_HI_G_MASK 0x00001000
-#define TLB_HI_ASID_MASK 0x000000ff
-
-#define TLB_LO_S_MASK 0x80000000
-#define TLB_LO_PFN_MASK 0x03ffffc0
-#define TLB_LO_C_MASK 0x00000038
-#define TLB_LO_D_MASK 0x00000004
-#define TLB_LO_V_MASK 0x00000002
-
-#define TLB_SIZE 48
-
-typedef struct _sim_r5900_cpu {
-
- /* The R5900 has 32 x 128bit general purpose registers.
- Fortunatly, the high 64 bits are only touched by multimedia (MMI)
- instructions. The normal mips instructions just use the lower 64
- bits. To avoid changing the older parts of the simulator to
- handle this weirdness, the high 64 bits of each register are kept
- in a separate array (registers1). The high 64 bits of any
- register are by convention refered by adding a '1' to the end of
- the normal register's name. So LO still refers to the low 64
- bits of the LO register, LO1 refers to the high 64 bits of that
- same register. */
- signed_word gpr1[32];
-#define GPR1 ((CPU)->r5900.gpr1)
-#define GPR1_SET(N,VAL) (GPR1[(N]) = (VAL))
- signed_word lo1;
- signed_word hi1;
-#define LO1 ((CPU)->r5900.lo1)
-#define HI1 ((CPU)->r5900.hi1)
-
- /* The R5900 defines a shift amount register, that controls the
- amount of certain shift instructions */
- unsigned_word sa; /* the shift amount register */
-#define REGISTER_SA (124) /* GET RID IF THIS! */
-#define SA ((CPU)->r5900.sa)
-
- /* The R5900, in addition to the (almost) standard floating point
- registers, defines a 32 bit accumulator. This is used in
- multiply/accumulate style instructions */
- fp_word acc; /* floating-point accumulator */
-#define ACC ((CPU)->r5900.acc)
-
- /* See comments below about needing to count cycles between updating
- and setting HI/LO registers */
- hilo_history hi1_history;
-#define HI1HISTORY (&(CPU)->r5900.hi1_history)
- hilo_history lo1_history;
-#define LO1HISTORY (&(CPU)->r5900.lo1_history)
-
- r4000_tlb_entry_t tlb[TLB_SIZE];
-#define TLB ((CPU)->r5900.tlb)
-
-} sim_r5900_cpu;
-
-#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
-#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
-#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
-#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
-
-#define BYTES_IN_MIPS_REGS (sizeof(signed_word))
-#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
-#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
-#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
-
-/* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
- T - type of the sub part
- TC - # of T's in the mips part of the "register"
- I - index (from 0) of desired sub part
- A - low part of "register"
- A1 - high part of register
-*/
-#define SUB_REG_FETCH(T,TC,A,A1,I) \
-(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
- + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
- ? ((TC) - 1 - (I) % (TC)) \
- : ((I) % (TC)) \
- ) \
- ) \
- )
-
-/*
-GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
- where <type> has two letters:
- 1 is S=signed or U=unsigned
- 2 is B=byte H=halfword W=word D=doubleword
-*/
-
-#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
-
-#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
-#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
-
-#define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
-#define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
-#define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
-#define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
-
-#define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
-#define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
-#define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
-#define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
-
-#define TMP_DCL unsigned64 tmp_reg, tmp_reg1
-
-#define TMP_SB(I) SUB_REG_SB(&tmp_reg, &tmp_reg1, I)
-#define TMP_SH(I) SUB_REG_SH(&tmp_reg, &tmp_reg1, I)
-#define TMP_SW(I) SUB_REG_SW(&tmp_reg, &tmp_reg1, I)
-#define TMP_SD(I) SUB_REG_SD(&tmp_reg, &tmp_reg1, I)
-
-#define TMP_UB(I) SUB_REG_UB(&tmp_reg, &tmp_reg1, I)
-#define TMP_UH(I) SUB_REG_UH(&tmp_reg, &tmp_reg1, I)
-#define TMP_UW(I) SUB_REG_UW(&tmp_reg, &tmp_reg1, I)
-#define TMP_UD(I) SUB_REG_UD(&tmp_reg, &tmp_reg1, I)
-
-#define TMP_WRT(R) do { GPR[R] = tmp_reg; GPR1[R] = tmp_reg1; } while(0)
-
-#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
-#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
-#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
-#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
-
-#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
-#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
-#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
-#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
-
-#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
-#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
-#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
-#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
-
-#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
-#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
-#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
-#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
-
-
-
-#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
-#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
-#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
-#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
-
-#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
-#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
-#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
-#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
-
-#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
-#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
-#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
-#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
-
-#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
-#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
-#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
-#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
-
-/* end-sanitize-r5900 */
/* For backward compatibility */
#define PENDING_FILL(R,VAL) \
-{ \
+do { \
if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \
{ \
PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1); \
} \
else \
PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
-}
+} while (0)
address_word dspc; /* delay-slot PC */
#define DSPC ((CPU)->dspc)
-#if !WITH_IGEN
- /* Issue a delay slot instruction immediatly by re-calling
- idecode_issue */
-#define DELAY_SLOT(TARGET) \
- do { \
- address_word target = (TARGET); \
- instruction_word delay_insn; \
- sim_events_slip (SD, 1); \
- CIA = CIA + 4; /* NOTE not mips16 */ \
- STATE |= simDELAYSLOT; \
- delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ \
- idecode_issue (CPU_, delay_insn, (CIA)); \
- STATE &= ~simDELAYSLOT; \
- NIA = target; \
- } while (0)
-#define NULLIFY_NEXT_INSTRUCTION() \
- do { \
- sim_events_slip (SD, 1); \
- dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
- NIA = CIA + 8; \
- } while (0)
-#else
#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
-#endif
/* State of the simulator */
#define LAST_EMBED_REGNUM (89)
#define NUM_REGS (LAST_EMBED_REGNUM + 1)
-/* start-sanitize-r5900 */
-#define FIRST_COP0_REG 128
-#define NUM_COP0_REGS 22
-#undef NUM_REGS
-#define NUM_REGS (150)
-/* end-sanitize-r5900 */
#endif
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#ifndef TM_TXVU_H
-/* Number of machine registers */
-#define NUM_VU_REGS 160
-
-#define NUM_VU_INTEGER_REGS 16
-#define FIRST_VEC_REG 32
-
-#define NUM_VIF_REGS 26
-
-#define NUM_CORE_REGS 150
-
-#undef NUM_REGS
-#define NUM_REGS (NUM_CORE_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
-#endif /* no tm-txvu.h */
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
enum float_operation
-/* start-sanitize-sky */
-/* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
-/* end-sanitize-sky */
{
FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
manifests to access the correct slot. */
unsigned_word registers[LAST_EMBED_REGNUM + 1];
+
int register_widths[NUM_REGS];
#define REGISTERS ((CPU)->registers)
#define EPC (REGISTERS[88])
#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
+ /* All internal state modified by signal_exception() that may need to be
+ rolled back for passing moment-of-exception image back to gdb. */
+ unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
+ unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
+ int exc_suspended;
+
+#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
+#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
+#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
+
unsigned_word c0_config_reg;
#define C0_CONFIG ((CPU)->c0_config_reg)
#define NR_COP0_GPR 32
unsigned_word cop0_gpr[NR_COP0_GPR];
#define COP0_GPR ((CPU)->cop0_gpr)
- /* start-sanitize-r5900 */
-#define NR_COP0_BP 8
- unsigned_word cop0_bp[NR_COP0_BP];
-#define COP0_BP ((CPU)->cop0_bp)
-#define NR_COP0_P 64
- unsigned_word cop0_p[NR_COP0_P];
-
-#define COP0_P ((CPU)->cop0_p)
-#define COP0_INDEX ((unsigned32)(COP0_GPR[0]))
-#define COP0_RANDOM ((unsigned32)(COP0_GPR[1]))
-#define COP0_ENTRYLO0 ((unsigned32)(COP0_GPR[2]))
-#define COP0_ENTRYLO1 ((unsigned32)(COP0_GPR[3]))
-#define COP0_CONTEXT ((unsigned32)(COP0_GPR[4]))
-#define COP0_PAGEMASK ((unsigned32)(COP0_GPR[5]))
-#define COP0_WIRED ((unsigned32)(COP0_GPR[6]))
#define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
-#define COP0_COUNT ((unsigned32)(COP0_GPR[9]))
-#define COP0_ENTRYHI ((unsigned32)(COP0_GPR[10]))
-#define COP0_COMPARE ((unsigned32)(COP0_GPR[11]))
-#define COP0_EPC ((unsigned32)(EPC)) /* 14 */
-#define COP0_PRID ((unsigned32)(COP0_GPR[15]))
-#define COP0_CONFIG ((unsigned32)(C0_CONFIG)) /* 16 */
-#define COP0_TAGLO ((unsigned32)(COP0_GPR[28]))
-#define COP0_TAGHI ((unsigned32)(COP0_GPR[29]))
-#define COP0_ERROREPC ((unsigned32)(COP0_GPR[30]))
-
-#define COP0_CONTEXT_BADVPN2_MASK 0x007ffff0
-
-#define COP0_CONTEXT_set_BADVPN2(x) \
- (COP0_CONTEXT = ((COP0_CONTEXT & 0xff100000) | ((x << 4) & 0x007ffff0)))
- /* end-sanitize-r5900 */
/* Keep the current format state for each register: */
FP_formats fpr_state[32];
hilo_history lo_history;
#define LOHISTORY (&(CPU)->lo_history)
- /* start-sanitize-branchbug4011 */
-#if 1
- int branchbug4011_option;
-#define BRANCHBUG4011_OPTION ((CPU)->branchbug4011_option)
- address_word branchbug4011_last_target;
-#define BRANCHBUG4011_LAST_TARGET ((CPU)->branchbug4011_last_target)
- address_word branchbug4011_last_cia;
-#define BRANCHBUG4011_LAST_CIA ((CPU)->branchbug4011_last_cia)
-
-#define check_branch_bug() (check_4011_branch_bug (_SD))
-#define mark_branch_bug(TARGET) (mark_4011_branch_bug (_SD,TARGET))
-#else
- /* end-sanitize-branchbug4011 */
#define check_branch_bug()
#define mark_branch_bug(TARGET)
- /* start-sanitize-branchbug4011 */
-#endif
- /* end-sanitize-branchbug4011 */
- /* start-sanitize-r5900 */
- sim_r5900_cpu r5900;
- /* end-sanitize-r5900 */
-
- /* start-sanitize-cygnus */
- /* The MDMX ISA has a very very large accumulator */
- unsigned8 acc[3 * 8];
- /* end-sanitize-cygnus */
-
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- /* Device on which instruction issue last occured. */
- char cur_device;
-#endif
- /* end-sanitize-sky */
+
+
sim_cpu_base base;
};
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
#endif
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#ifdef SKY_FUNIT
- /* Record of option for floating point implementation type. */
- int fp_type_opt;
-#define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
-#define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
-#endif
-#endif
-/* end-sanitize-sky */
sim_state_base base;
};
#define status_ERL (1 << 2) /* Error level */
#define status_IM7 (1 << 15) /* Timer Interrupt Mask */
#define status_RP (1 << 27) /* Reduced Power mode */
-/* start-sanitize-r5900 */
-#define status_CU0 (1 << 28) /* COP0 usable */
-#define status_CU1 (1 << 29) /* COP1 usable */
-#define status_CU2 (1 << 30) /* COP2 usable */
-/* end-sanitize-r5900 */
/* Specializations for TX39 family */
#define status_IEc (1 << 0) /* Interrupt enable (current) */
#define cause_IP3 (1 << 11) /* Int 0 pending */
#define cause_IP2 (1 << 10) /* Int 1 pending */
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#define cause_EXC_mask (0x7c) /* Exception code */
-#else
-/* end-sanitize-sky */
#define cause_EXC_mask (0x1c) /* Exception code */
-/* start-sanitize-sky */
-#endif
-/* end-sanitize-sky */
#define cause_EXC_shift (2)
#define cause_SW0 (1 << 8) /* Software interrupt 0 */
#define TLB_REFILL (0)
#define TLB_INVALID (1)
-/* start-sanitize-r5900 */
-/* For the 5900, we have level 1 and level 2 exceptions. The level 2 exceptions
- are ColdReset, NMI, Counter, and Debug/SIO. Of these, we support only
- the NMIReset exception. */
-
-#define is5900Level2Exception(x) (x == NMIReset)
-/* end-sanitize-r5900 */
/* The following break instructions are reserved for use by the
simulator. The first is used to halt the simulation. The second
#define HALT_INSTRUCTION (0x03ff000d)
#define HALT_INSTRUCTION2 (0x0000ffcd)
-/* start-sanitize-sky */
-#define HALT_INSTRUCTION_PASS (0x03fffc0d) /* break 0xffff0 */
-#define HALT_INSTRUCTION_FAIL (0x03ffffcd) /* break 0xfffff */
-/* end-sanitize-sky */
#define BREAKPOINT_INSTRUCTION (0x0005000d)
#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
-/* start-sanitize-sky */
-#define LOAD_INSTRUCTION (0x03fffc4d) /* break 0xffff1 */
-#define PRINTF_INSTRUCTION (0x03fffc8d) /* break 0xffff2 */
-/* end-sanitize-sky */
void interrupt_event (SIM_DESC sd, void *data);
#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
+#define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
#define COP_SD(coproc_num,coproc_reg) \
cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
- int coproc_num, int coproc_reg, unsigned128 memword));
-unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
- int coproc_num, int coproc_reg));
-#define COP_LQ(coproc_num,coproc_reg,memword) \
-cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
-#define COP_SQ(coproc_num,coproc_reg) \
-cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
#define DecodeCoproc(instruction) \
decode_coproc (SD, CPU, cia, (instruction))
+void sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
+
/* Memory accesses */
#define AccessLength_DOUBLEWORD (7)
#define AccessLength_QUADWORD (15)
-#if (WITH_IGEN)
#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
? AccessLength_DOUBLEWORD /*7*/ \
: AccessLength_WORD /*3*/)
#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
-#endif
INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
extern FILE *tracefh;
INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
+extern SIM_CORE_SIGNAL_FN mips_core_signal;
char* pr_addr PARAMS ((SIM_ADDR addr));
char* pr_uword64 PARAMS ((uword64 addr));
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-
-#ifdef SIM_ENGINE_HALT_HOOK
-#undef SIM_ENGINE_HALT_HOOK
-#endif
-
-void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
-#define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia)
-
-#ifdef SIM_ENGINE_RESTART_HOOK
-#undef SIM_ENGINE_RESTART_HOOK
-#endif
-
-void sky_sim_engine_restart PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
-#define SIM_ENGINE_RESTART_HOOK(sd, L, pc) sky_sim_engine_restart(sd, L, pc)
-
-/* for resume/suspend modules */
-SIM_RC sky_sim_module_install PARAMS ((SIM_DESC sd));
-
-#define MODULE_LIST sky_sim_module_install,
-
-void sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
-
-#ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
-enum txvu_cpu_context
-{
- TXVU_CPU_AUTO = -1, /* context-sensitive context */
- TXVU_CPU_MASTER = 0, /* R5900 core */
- TXVU_CPU_VU0 = 1, /* Vector units */
- TXVU_CPU_VU1 = 2,
- TXVU_CPU_VIF0 = 3, /* Vector interface units */
- TXVU_CPU_VIF1 = 4,
- TXVU_CPU_LAST /* Count of context types */
-};
-
-/* memory segment for communication with GDB */
-#define VIO_BASE 0xa0000000
-#define GDB_COMM_AREA 0x19810000 /* Random choice */
-#define GDB_COMM_SIZE 0x4000
-
-/* Memory address containing last device to execute */
-#define LAST_DEVICE GDB_COMM_AREA
-
-/* The FIFO breakpoint count and table */
-#define FIFO_BPT_CNT (GDB_COMM_AREA + 4)
-#define FIFO_BPT_TBL (GDB_COMM_AREA + 8)
-
-/* Each element of the breakpoint table is three four-byte integers. */
-#define BPT_ELEM_SZ 4*3
-#define TXVU_VU_BRK_MASK 0x02 /* Breakpoint bit is #57 for VU insns */
-#define TXVU_VIF_BRK_MASK 0x80 /* Use interrupt bit for VIF insns */
+void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
+void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
+void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
-#endif /* !TM_TXVU_H */
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
#include "sim-main.c"