arc: Don't generate dynamic relocation for non SEC_ALLOC sections

[deliverable/binutils-gdb.git] / sim / mips / tx.igen

diff --git a/sim/mips/tx.igen b/sim/mips/tx.igen
index 7e4af39ce0a8828eac58affcc5cf8796b37acedb..cd8d76abc770b2deb84d2c6575b506ef1117cde5 100644 (file)
--- a/sim/mips/tx.igen
+++ b/sim/mips/tx.igen
@@ -7,13 +7,11 @@
 "madd r<RS>, r<RT>":RD == 0
 "madd r<RD>, r<RS>, r<RT>"
 *r3900
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
                   + ((signed64) EXTEND32 (GPR[RT])
                      * (signed64) EXTEND32 (GPR[RS])));
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
   LO = EXTEND32 (prod);
   HI = EXTEND32 (VH4_8 (prod));
@@ -27,13 +25,11 @@
 "maddu r<RS>, r<RT>":RD == 0
 "maddu r<RD>, r<RS>, r<RT>"
 *r3900
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
                     + ((unsigned64) VL4_8 (GPR[RS])
                        * (unsigned64) VL4_8 (GPR[RT])));
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
   LO = EXTEND32 (prod);
   HI = EXTEND32 (VH4_8 (prod));
@@ -42,4 +38,9 @@
     GPR[RD] = LO;
 }
 
-
+000000,CODE.20,001110::CO1:::SDBBP
+"sdbbp"
+*r3900:
+{
+  SignalException (DebugBreakPoint, instruction);
+}