This commit was generated by cvs2svn to track changes on a CVS vendor

[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen

diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
index f5e9c4e7547cd00b17537975697880cc80a2d2b3..31bbc730de597c184fc8aa6b101aa2c907f2df29 100644 (file)
--- a/sim/mn10300/am33.igen
+++ b/sim/mn10300/am33.igen
@@ -19,6 +19,25 @@
     return REG_E0 + rreg;
 }
 
+:function:::int:translate_xreg:int xreg
+{
+  switch (xreg)
+    {
+    case 0:
+      return REG_SP;
+    case 1:
+      return REG_MDRQ;
+    case 2:
+      return REG_MCRH;
+    case 3:
+      return REG_MCRL;
+    case 4:
+      return REG_MCVF;
+    default:
+      abort ();
+    }
+}
+
 // 1111 0000 0010 00An; mov USP,An
 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
 "mov"
@@ -222,7 +241,6 @@
       usp += 4;
     }
 
-  /* start-sanitize-am33 */
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
     {
       if (mask & 0x1)
@@ -255,7 +273,6 @@
          usp += 4;
        }
     }
-  /* end-sanitize-am33 */
 
   /* And make sure to update the stack pointer.  */
   State.regs[REG_USP] = usp;
@@ -301,7 +318,6 @@
          /* Need to save MDQR, MCRH, MCRL, and MCVF */
        }
     }
-  /* end-sanitize-am33 */
 
   if (mask & 0x80)
     {
@@ -589,17 +605,13 @@
 "mov"
 *am33
 {
-  int dstreg;
+  int dstreg, srcreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
+  srcreg = translate_xreg (SD_, XRM2);
 
-  if (XRM2 == 0)
-    {
-      State.regs[dstreg] = State.regs[REG_SP];
-    }
-  else
-    abort ();
+  State.regs[dstreg] = State.regs[srcreg];
 }
 
 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
@@ -607,17 +619,13 @@
 "mov"
 *am33
 {
-  int srcreg;
+  int srcreg, dstreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    {
-      State.regs[REG_SP] = State.regs[srcreg];
-    }
-  else
-    abort ();
+  State.regs[dstreg] = State.regs[srcreg];
 }
 
 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
@@ -841,7 +849,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)State.regs[srcreg]);
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1001,7 +1009,7 @@
 }
 
 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
-8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
+8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
 "mov"
 *am33
 {
@@ -1101,7 +1109,7 @@
 }
 
 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
-8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
+8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
 "movhu"
 *am33
 {
@@ -1713,11 +1721,9 @@
   int dstreg;
 
   PC = cia;
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    State.regs[REG_SP] = IMM8;
-  else
-    abort ();
+  State.regs[dstreg] = IMM8;
 }
 
 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
@@ -1848,7 +1854,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)EXTEND8 (IMM8));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1963,7 +1969,7 @@
 }
 
 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
-8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
+8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
 "mov"
 *am33
 {
@@ -1972,8 +1978,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
-  State.regs[srcreg] += 4;
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND8 (IMM8);
 }
 
 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
@@ -1985,8 +1991,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
-  State.regs[dstreg] += 4;
+  store_word (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += EXTEND8 (IMM8);
 }
 
 
@@ -2057,7 +2063,7 @@
 }
 
 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
-8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
+8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
 "movhu"
 *am33
 {
@@ -2066,8 +2072,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
-  State.regs[srcreg] += 2;
+  State.regs[dstreg] = load_half (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND8 (IMM8);
 }
 
 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
@@ -2079,8 +2085,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
-  State.regs[dstreg] += 2;
+  store_half (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += EXTEND8 (IMM8);
 }
 
 
@@ -2583,7 +2589,7 @@
   srcreg2 = translate_rreg (SD_, RN0);
   dstreg = translate_rreg (SD_, RD0);
 
-  State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
+  State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
 
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000);
@@ -2593,7 +2599,7 @@
 }
 
 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
-8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
+8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
 "mul"
 *am33
 {
@@ -2609,18 +2615,18 @@
 
   temp = ((signed64)(signed32)State.regs[srcreg1]
           *  (signed64)(signed32)State.regs[srcreg2]);
-  State.regs[dstreg1] = temp & 0xffffffff;
-  State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[dstreg2] = temp & 0xffffffff;
+  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
 
   z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
-  n = (State.regs[dstreg2] & 0x80000000);
+  n = (State.regs[dstreg1] & 0x80000000);
 
   PSW &= ~(PSW_Z | PSW_N);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
 }
 
 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
-8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
+8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
 "mulu"
 *am33
 {
@@ -2636,11 +2642,11 @@
 
   temp = ((unsigned64)State.regs[srcreg1]
           *  (unsigned64)State.regs[srcreg2]);
-  State.regs[dstreg1] = temp & 0xffffffff;
-  State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[dstreg2] = temp & 0xffffffff;
+  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
 
   z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
-  n = (State.regs[dstreg2] & 0x80000000);
+  n = (State.regs[dstreg1] & 0x80000000);
 
   PSW &= ~(PSW_Z | PSW_N);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
@@ -2803,7 +2809,7 @@
 }
 
 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
+8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
 "mac"
 *am33
 {
@@ -2839,7 +2845,7 @@
 }
 
 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
+8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
 "macu"
 *am33
 {
@@ -2930,26 +2936,28 @@
     }
 }
 
-// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
-8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
+// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
 "mach"
 *am33
 {
-  int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  int srcreg1, srcreg2, dstreg1, dstreg2;
+  long long temp, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
-  dstreg = translate_rreg (SD_, RD0);
+  dstreg1 = translate_rreg (SD_, RD0);
+  dstreg2 = translate_rreg (SD_, RD0);
 
   temp = ((signed32)(State.regs[srcreg2] & 0xffff)
           * (signed32)(State.regs[srcreg1] & 0xffff));
-  sum = State.regs[dstreg] + temp;
-  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+  State.regs[dstreg2] += (temp & 0xffffffff);
+  sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
-  State.regs[dstreg] = sum;
+  State.regs[dstreg1] = sum;
   if (v)
     {
       State.regs[REG_MCVF] = 1;
@@ -2958,26 +2966,28 @@
     }
 }
 
-// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
-8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
+// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
 "machu"
 *am33
 {
-  int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  int srcreg1, srcreg2, dstreg1, dstreg2;
+  long long temp, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
-  dstreg = translate_rreg (SD_, RD0);
+  dstreg1 = translate_rreg (SD_, RD0);
+  dstreg2 = translate_rreg (SD_, RD0);
 
   temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
           * (unsigned32)(State.regs[srcreg1] & 0xffff));
-  sum = State.regs[dstreg] + temp;
-  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+  State.regs[dstreg2] += (temp & 0xffffffff);
+  sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
-  State.regs[dstreg] = sum;
+  State.regs[dstreg1] = sum;
   if (v)
     {
       State.regs[REG_MCVF] = 1;
@@ -3047,7 +3057,7 @@
 }
 
 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
+8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
 "dmulh"
 *am33
 {
@@ -3069,7 +3079,7 @@
 }
 
 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
+8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
 "dmulhu"
 *am33
 {
@@ -3274,14 +3284,12 @@
 "mov"
 *am33
 {
+  int dstreg;
+
   PC = cia;
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    {
-      State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
-    }
-  else
-    abort ();
+  State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
 }
 
 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
@@ -3413,7 +3421,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -3435,7 +3443,7 @@
   temp = ((unsigned64)State.regs[dstreg]
           *  (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -3542,7 +3550,7 @@
 }
 
 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
-8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
+8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
 "mov"
 *am33
 {
@@ -3551,10 +3559,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (State.regs[srcreg]
-                                 + EXTEND24 (FETCH24 (IMM24A,
-                                                      IMM24B, IMM24C)));
-  State.regs[srcreg] += 4;
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
@@ -3567,9 +3573,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
-             State.regs[srcreg]);
-  State.regs[dstreg] += 4;
+  store_word (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 
@@ -3655,7 +3660,7 @@
 }
 
 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
-8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
+8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
 "movhu"
 *am33
 {
@@ -3664,10 +3669,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (State.regs[srcreg]
-                                 + EXTEND24 (FETCH24 (IMM24A,
-                                             IMM24B, IMM24C)));
-  State.regs[dstreg] += 2;
+  State.regs[dstreg] = load_half (State.regs[srcreg]);
+  State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
@@ -3680,9 +3683,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
-             State.regs[srcreg]);
-  State.regs[srcreg] += 2;
+  store_half (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
@@ -4043,12 +4045,12 @@
 "mov"
 *am33
 {
+  int dstreg;
+
   PC = cia;
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
-  else
-    abort ();
+  State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
@@ -4179,7 +4181,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -4201,7 +4203,7 @@
   temp = ((unsigned64)State.regs[dstreg]
           *  (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -4305,7 +4307,7 @@
 }
 
 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
-8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
+8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
 "mov"
 *am33
 {
@@ -4314,9 +4316,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (State.regs[srcreg]
-                                 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
-  State.regs[srcreg] += 4;
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
@@ -4329,9 +4330,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
-             State.regs[srcreg]);
-  State.regs[dstreg] += 4;
+  store_word (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 
@@ -4415,7 +4415,7 @@
 
 
 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
-8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
+8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
 "movhu"
 *am33
 {
@@ -4424,9 +4424,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (State.regs[srcreg]
-                                 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
-  State.regs[srcreg] += 2;
+  State.regs[dstreg] = load_half (State.regs[srcreg]);
+  State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
@@ -4439,134 +4438,365 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
-             State.regs[srcreg]);
-  State.regs[dstreg] += 2;
+  store_half (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 
-// ??? mac
-// ??? macu
-// ??? macb
-// ??? macbu
-// ??? mach
-// ??? machu
-// ??? dmach
-// ??? dmachu
-// ??? dmulh
-// ??? dmulhu
-
-// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
-8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
-"mov"
+// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
+8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
+"mac"
 *am33
 {
-  int dstreg;
+  int srcreg, imm;
+  long long temp, sum;
+  int c, v;
 
   PC = cia;
-  dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed64)(signed32)State.regs[srcreg]
+          * (signed64)(signed32)imm);
+  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+  State.regs[REG_MCRL] = sum;
+  temp >>= 32;
+  temp &= 0xffffffff;
+  sum = State.regs[REG_MCRH] + temp + c;
+  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRH] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
-8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
-"mov"
+// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
+8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
+"macu"
 *am33
 {
-  int srcreg;
+  int srcreg, imm;
+  long long temp, sum;
+  int c, v;
 
   PC = cia;
-  srcreg = translate_rreg (SD_, RM2);
-  store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned64)State.regs[srcreg]
+          * (unsigned64)imm);
+  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+  State.regs[REG_MCRL] = sum;
+  temp >>= 32;
+  temp &= 0xffffffff;
+  sum = State.regs[REG_MCRH] + temp + c;
+  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRH] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
-8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
-"movbu"
+// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
+8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
+"macb"
 *am33
 {
-  int dstreg;
+  int srcreg, imm;
+  long temp, sum;
+  int v;
 
   PC = cia;
-  dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
+          * (signed32)(signed8)(imm & 0xff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
-8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
-"movbu"
+// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
+8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
+"macbu"
 *am33
 {
-  int srcreg;
+  int srcreg, imm;
+  long temp, sum;
+  int v;
 
   PC = cia;
-  srcreg = translate_rreg (SD_, RM2);
-  store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[srcreg] & 0xff)
+          * (unsigned32)(imm & 0xff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
-8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
-"movhu"
+// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
+8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
+"mach"
 *am33
 {
-  int dstreg;
+  int srcreg, imm;
+  long temp, sum;
+  int v;
 
   PC = cia;
-  dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+          * (signed32)(signed16)(imm & 0xffff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
-8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
-"movhu"
+// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
+8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
+"machu"
 *am33
 {
-  int srcreg;
+  int srcreg, imm;
+  long temp, sum;
+  int v;
 
   PC = cia;
-  srcreg = translate_rreg (SD_, RM2);
-  store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+          * (unsigned32)(imm & 0xffff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_add
-"add_add"
+// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
+8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
+"dmach"
 *am33
 {
-  int srcreg1, srcreg2, dstreg1, dstreg2;
+  int srcreg, imm;
+  long temp, temp2, sum;
+  int v;
 
   PC = cia;
-  srcreg1 = translate_rreg (SD_, RM1);
-  srcreg2 = translate_rreg (SD_, RM2);
-  dstreg1 = translate_rreg (SD_, RN1);
-  dstreg2 = translate_rreg (SD_, RN2);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
-  State.regs[dstreg2] += State.regs[srcreg2];
+  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+          * (signed32)(signed16)(imm & 0xffff));
+  temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
+          * (signed32)(signed16)((imm >> 16) & 0xffff));
+  sum = temp + temp2 + State.regs[REG_MCRL];
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
-// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_add
-"add_add"
+// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
+8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
+"dmachu"
 *am33
 {
-  int srcreg1, dstreg1, dstreg2;
+  int srcreg, imm;
+  long temp, temp2, sum;
+  int v;
 
   PC = cia;
-  srcreg1 = translate_rreg (SD_, RM1);
-  dstreg1 = translate_rreg (SD_, RN1);
-  dstreg2 = translate_rreg (SD_, RN2);
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
-  State.regs[dstreg2] += EXTEND4 (IMM4);
-}
-  
-// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_sub
+  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+          * (unsigned32)(imm & 0xffff));
+  temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
+          * (unsigned32)((imm >> 16) & 0xffff));
+  sum = temp + temp2 + State.regs[REG_MCRL];
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
+8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
+"dmulh"
+*am33
+{
+  int imm, dstreg;
+  long temp;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
+          * (signed32)(signed16)(imm & 0xffff));
+  State.regs[REG_MDRQ] = temp;
+  temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
+          * (signed32)(signed16)((imm>>16) & 0xffff));
+  State.regs[dstreg] = temp;
+}
+
+// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
+8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
+"dmulhu"
+*am33
+{
+  int imm, dstreg;
+  long temp;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
+          * (unsigned32)(imm & 0xffff));
+  State.regs[REG_MDRQ] = temp;
+  temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
+          * (unsigned32)((imm >>16) & 0xffff));
+  State.regs[dstreg] = temp;
+}
+
+// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
+8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
+"mov"
+*am33
+{
+  int dstreg;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN2);
+  State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
+8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
+"mov"
+*am33
+{
+  int srcreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM2);
+  store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
+8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
+"movbu"
+*am33
+{
+  int dstreg;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN2);
+  State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
+8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
+"movbu"
+*am33
+{
+  int srcreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM2);
+  store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
+8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
+"movhu"
+*am33
+{
+  int dstreg;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN2);
+  State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
+8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
+"movhu"
+*am33
+{
+  int srcreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM2);
+  store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
+"add_add"
+*am33
+{
+  int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
+
+  PC = cia;
+  srcreg1 = translate_rreg (SD_, RM1);
+  srcreg2 = translate_rreg (SD_, RM2);
+  dstreg1 = translate_rreg (SD_, RN1);
+  dstreg2 = translate_rreg (SD_, RN2);
+
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
+  State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
+"add_add"
+*am33
+{
+  int srcreg1, dstreg1, dstreg2;
+  int result1;
+
+  PC = cia;
+  srcreg1 = translate_rreg (SD_, RM1);
+  dstreg1 = translate_rreg (SD_, RN1);
+  dstreg2 = translate_rreg (SD_, RN2);
+
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
+  State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
+}
+  
+// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
 "add_sub"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4574,28 +4804,31 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_sub
+8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
 "add_sub"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_cmp
+8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
 "add_cmp"
 *am33
 {
@@ -4607,12 +4840,12 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] += State.regs[srcreg1];
 }
 
 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_cmp
+8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
 "add_cmp"
 *am33
 {
@@ -4623,16 +4856,17 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] += State.regs[srcreg1];
 }
   
 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_mov
+8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
 "add_mov"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4640,32 +4874,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_mov
+8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
 "add_mov"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asr
+8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
 "add_asr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -4674,18 +4912,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asr
+8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
 "add_asr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -4693,18 +4933,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_lsr
+8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
 "add_lsr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4712,16 +4954,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_lsr
+8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
 "add_lsr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -4729,17 +4973,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asl
+8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
 "add_asl"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4747,16 +4993,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asl
+8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
 "add_asl"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -4764,12 +5012,13 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_add
+8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
 "cmp_add"
 *am33
 {
@@ -4786,7 +5035,7 @@
 }
 
 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_add
+8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
 "cmp_add"
 *am33
 {
@@ -4802,7 +5051,7 @@
 }
   
 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_sub
+8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
 "cmp_sub"
 *am33
 {
@@ -4819,7 +5068,7 @@
 }
 
 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_sub
+8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
 "cmp_sub"
 *am33
 {
@@ -4835,7 +5084,7 @@
 }
   
 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_mov
+8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
 "cmp_mov"
 *am33
 {
@@ -4852,7 +5101,7 @@
 }
 
 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_mov
+8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
 "cmp_mov"
 *am33
 {
@@ -4868,7 +5117,7 @@
 }
   
 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asr
+8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
 "cmp_asr"
 *am33
 {
@@ -4888,7 +5137,7 @@
 }
 
 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asr
+8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
 "cmp_asr"
 *am33
 {
@@ -4907,7 +5156,7 @@
 }
 
 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_lsr
+8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
 "cmp_lsr"
 *am33
 {
@@ -4924,7 +5173,7 @@
 }
 
 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_lsr
+8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
 "cmp_lsr"
 *am33
 {
@@ -4942,7 +5191,7 @@
   
   
 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asl
+8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
 "cmp_asl"
 *am33
 {
@@ -4959,7 +5208,7 @@
 }
 
 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asl
+8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
 "cmp_asl"
 *am33
 {
@@ -4976,11 +5225,12 @@
 }
 
 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_add
+8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
 "sub_add"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4988,32 +5238,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_add
+8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
 "sub_add"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_sub
+8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
 "sub_sub"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5021,28 +5275,31 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_sub
+8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
 "sub_sub"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_cmp
+8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
 "sub_cmp"
 *am33
 {
@@ -5054,32 +5311,34 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] -= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_cmp
+8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
 "sub_cmp"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] -= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_mov
+8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
 "sub_mov"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5087,32 +5346,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_mov
+8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
 "sub_mov"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asr
+8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
 "sub_asr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5121,18 +5384,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asr
+8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
 "sub_asr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5140,18 +5405,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_lsr
+8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
 "sub_lsr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5159,16 +5426,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_lsr
+8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
 "sub_lsr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5176,17 +5445,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asl
+8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
 "sub_asl"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5194,16 +5465,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asl
+8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
 "sub_asl"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5211,16 +5484,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_add
+8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
 "mov_add"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5228,32 +5503,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_add
+8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
 "mov_add"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_sub
+8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
 "mov_sub"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5261,28 +5540,31 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_sub
+8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
 "mov_sub"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_cmp
+8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
 "mov_cmp"
 *am33
 {
@@ -5294,12 +5576,12 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] = State.regs[srcreg1];
 }
 
 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_cmp
+8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
 "mov_cmp"
 *am33
 {
@@ -5310,16 +5592,17 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] = State.regs[srcreg1];
 }
   
 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_mov
+8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
 "mov_mov"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5327,32 +5610,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_mov
+8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
 "mov_mov"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asr
+8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
 "mov_asr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5361,18 +5648,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asr
+8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
 "mov_asr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5380,18 +5669,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_lsr
+8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
 "mov_lsr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5399,16 +5690,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_lsr
+8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
 "mov_lsr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5416,17 +5709,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asl
+8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
 "mov_asl"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5434,16 +5729,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asl
+8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
 "mov_asl"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5451,74 +5748,83 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_add
+8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
 "add_add"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_add
+8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
 "add_add"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_sub
+8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
 "add_sub"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_sub
+8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
 "add_sub"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_cmp
+8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
 "add_cmp"
 *am33
 {
@@ -5529,12 +5835,12 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] += EXTEND4 (IMM4A);
 }
 
 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_cmp
+8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
 "add_cmp"
 *am33
 {
@@ -5544,47 +5850,52 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] += EXTEND4 (IMM4A);
 }
   
 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_mov
+8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
 "add_mov"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_mov
+8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
 "add_mov"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asr
+8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
 "add_asr"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5592,97 +5903,108 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asr
+8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
 "add_asr"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_lsr
+8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
 "add_lsr"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_lsr
+8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
 "add_lsr"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asl
+8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
 "add_asl"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asl
+8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
 "add_asl"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_add
+8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
 "cmp_add"
 *am33
 {
@@ -5698,7 +6020,7 @@
 }
 
 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_add
+8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
 "cmp_add"
 *am33
 {
@@ -5713,7 +6035,7 @@
 }
   
 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_sub
+8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
 "cmp_sub"
 *am33
 {
@@ -5729,7 +6051,7 @@
 }
 
 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_sub
+8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
 "cmp_sub"
 *am33
 {
@@ -5744,7 +6066,7 @@
 }
   
 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_mov
+8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
 "cmp_mov"
 *am33
 {
@@ -5760,7 +6082,7 @@
 }
 
 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_mov
+8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
 "cmp_mov"
 *am33
 {
@@ -5775,7 +6097,7 @@
 }
   
 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asr
+8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
 "cmp_asr"
 *am33
 {
@@ -5794,7 +6116,7 @@
 }
 
 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asr
+8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
 "cmp_asr"
 *am33
 {
@@ -5812,7 +6134,7 @@
 }
   
 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_lsr
+8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
 "cmp_lsr"
 *am33
 {
@@ -5828,7 +6150,7 @@
 }
 
 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_lsr
+8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
 "cmp_lsr"
 *am33
 {
@@ -5845,7 +6167,7 @@
   
   
 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asl
+8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
 "cmp_asl"
 *am33
 {
@@ -5861,7 +6183,7 @@
 }
 
 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asl
+8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
 "cmp_asl"
 *am33
 {
@@ -5877,135 +6199,150 @@
 }
 
 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_add
+8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
 "sub_add"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_add
+8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
 "sub_add"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_sub
+8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
 "sub_sub"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_sub
+8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
 "sub_sub"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_cmp
+8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
 "sub_cmp"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] -= EXTEND4 (IMM4A);
 }
 
 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_cmp
+8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
 "sub_cmp"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] -= EXTEND4 (IMM4A);
 }
   
 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_mov
+8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
 "sub_mov"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_mov
+8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
 "sub_mov"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asr
+8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
 "sub_asr"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6013,159 +6350,178 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asr
+8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
 "sub_asr"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_lsr
+8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
 "sub_lsr"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_lsr
+8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
 "sub_lsr"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asl
+8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
 "sub_asl"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asl
+8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
 "sub_asl"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_add
+8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
 "mov_add"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_add
+8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
 "mov_add"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_sub
+8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
 "mov_sub"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_sub
+8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
 "mov_sub"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_cmp
+8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
 "mov_cmp"
 *am33
 {
@@ -6176,12 +6532,12 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] = EXTEND4 (IMM4A);
 }
 
 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_cmp
+8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
 "mov_cmp"
 *am33
 {
@@ -6191,47 +6547,52 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] = EXTEND4 (IMM4A);
 }
   
 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_mov
+8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
 "mov_mov"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_mov
+8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
 "mov_mov"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asr
+8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
 "mov_asr"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6239,101 +6600,113 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asr
+8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
 "mov_asr"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_lsr
+8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
 "mov_lsr"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_lsr
+8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
 "mov_lsr"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asl
+8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
 "mov_asl"
 *am33
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asl
+8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
 "mov_asl"
 *am33
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
  
 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_add
+8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
 "and_add"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6341,32 +6714,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_add
+8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
 "and_add"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_sub
+8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
 "and_sub"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6374,28 +6751,31 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_sub
+8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
 "and_sub"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_cmp
+8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
 "and_cmp"
 *am33
 {
@@ -6407,12 +6787,12 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] &= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_cmp
+8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
 "and_cmp"
 *am33
 {
@@ -6423,16 +6803,17 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] &= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_mov
+8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
 "and_mov"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6440,32 +6821,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_mov
+8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
 "and_mov"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asr
+8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
 "and_asr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6474,18 +6859,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asr
+8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
 "and_asr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6493,18 +6880,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_lsr
+8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
 "and_lsr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6512,16 +6901,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_lsr
+8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
 "and_lsr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6529,17 +6920,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asl
+8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
 "and_asl"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6547,16 +6940,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asl
+8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
 "and_asl"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6564,12 +6959,13 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_add
+8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
 "dmach_add"
 *am33
 {
@@ -6588,12 +6984,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_add
+8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
 "dmach_add"
 *am33
 {
@@ -6611,12 +7007,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_sub
+8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
 "dmach_sub"
 *am33
 {
@@ -6635,12 +7031,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_sub
+8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
 "dmach_sub"
 *am33
 {
@@ -6658,12 +7054,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_cmp
+8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
 "dmach_cmp"
 *am33
 {
@@ -6682,12 +7078,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_cmp
+8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
 "dmach_cmp"
 *am33
 {
@@ -6705,12 +7101,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_mov
+8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
 "dmach_mov"
 *am33
 {
@@ -6729,12 +7125,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_mov
+8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
 "dmach_mov"
 *am33
 {
@@ -6752,12 +7148,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asr
+8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
 "dmach_asr"
 *am33
 {
@@ -6776,14 +7172,14 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asr
+8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
 "dmach_asr"
 *am33
 {
@@ -6801,14 +7197,14 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_lsr
+8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
 "dmach_lsr"
 *am33
 {
@@ -6827,12 +7223,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_lsr
+8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
 "dmach_lsr"
 *am33
 {
@@ -6844,12 +7240,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  sum = temp + temp2 + State.regs[REG_MCRL];
+
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = sum;
 }
   
   
 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asl
+8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
 "dmach_asl"
 *am33
 {
@@ -6868,12 +7271,12 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asl
+8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
 "dmach_asl"
 *am33
 {
@@ -6891,16 +7294,17 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_add
+8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
 "xor_add"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6908,32 +7312,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_add
+8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
 "xor_add"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_sub
+8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
 "xor_sub"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6941,28 +7349,31 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_sub
+8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
 "xor_sub"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_cmp
+8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
 "xor_cmp"
 *am33
 {
@@ -6974,12 +7385,12 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] ^= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_cmp
+8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
 "xor_cmp"
 *am33
 {
@@ -6990,16 +7401,17 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] ^= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_mov
+8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
 "xor_mov"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7007,32 +7419,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_mov
+8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
 "xor_mov"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asr
+8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
 "xor_asr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7041,18 +7457,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asr
+8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
 "xor_asr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7060,18 +7478,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_lsr
+8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
 "xor_lsr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7079,16 +7499,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_lsr
+8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
 "xor_lsr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7096,17 +7518,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asl
+8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
 "xor_asl"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7114,16 +7538,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asl
+8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
 "xor_asl"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7131,16 +7557,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_add
+8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
 "swhw_add"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7148,33 +7576,37 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_add
+8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
 "swhw_add"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_sub
+8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
 "swhw_sub"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7182,30 +7614,33 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_sub
+8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
 "swhw_sub"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_cmp
+8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
 "swhw_cmp"
 *am33
 {
@@ -7217,13 +7652,13 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
   State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
                          | ((State.regs[srcreg1] >> 16) & 0xffff));
-  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
 }
 
 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_cmp
+8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
 "swhw_cmp"
 *am33
 {
@@ -7234,17 +7669,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
   State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
                          | ((State.regs[srcreg1] >> 16) & 0xffff));
-  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
 }
   
 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_mov
+8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
 "swhw_mov"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7252,34 +7688,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_mov
+8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
 "swhw_mov"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asr
+8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
 "swhw_asr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7288,19 +7728,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asr
+8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
 "swhw_asr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7308,19 +7750,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_lsr
+8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
 "swhw_lsr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7328,17 +7772,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_lsr
+8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
 "swhw_lsr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7346,18 +7792,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asl
+8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
 "swhw_asl"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7365,17 +7813,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asl
+8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
 "swhw_asl"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7383,17 +7833,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_add
+8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
 "or_add"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7401,32 +7853,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_add
+8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
 "or_add"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_sub
+8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
 "or_sub"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7434,28 +7890,31 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_sub
+8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
 "or_sub"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_cmp
+8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
 "or_cmp"
 *am33
 {
@@ -7467,12 +7926,12 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] |= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_cmp
+8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
 "or_cmp"
 *am33
 {
@@ -7483,16 +7942,17 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] |= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_mov
+8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
 "or_mov"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7500,32 +7960,36 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_mov
+8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
 "or_mov"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asr
+8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
 "or_asr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7534,18 +7998,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asr
+8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
 "or_asr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7553,18 +8019,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_lsr
+8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
 "or_lsr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7572,16 +8040,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_lsr
+8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
 "or_lsr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7589,17 +8059,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asl
+8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
 "or_asl"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7607,16 +8079,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asl
+8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
 "or_asl"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7624,16 +8098,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_add
+8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
 "sat16_add"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7642,21 +8118,23 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_add
+8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
 "sat16_add"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7664,21 +8142,23 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_sub
+8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
 "sat16_sub"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7687,21 +8167,23 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_sub
+8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
 "sat16_sub"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7709,21 +8191,23 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_cmp
+8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
 "sat16_cmp"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7731,18 +8215,17 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  State.regs[dstreg1] = result1;
   if (State.regs[srcreg1] >= 0x7fff)
     State.regs[dstreg1] = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
     State.regs[dstreg1] = 0xffff8000;
   else
     State.regs[dstreg1] = State.regs[srcreg1];
-
-  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
 }
 
 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_cmp
+8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
 "sat16_cmp"
 *am33
 {
@@ -7753,22 +8236,22 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
   if (State.regs[srcreg1] >= 0x7fff)
     State.regs[dstreg1] = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
     State.regs[dstreg1] = 0xffff8000;
   else
     State.regs[dstreg1] = State.regs[srcreg1];
-
-  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
 }
   
 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_mov
+8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
 "sat16_mov"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7777,21 +8260,23 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_mov
+8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
 "sat16_mov"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7799,21 +8284,23 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asr
+8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
 "sat16_asr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7823,23 +8310,25 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asr
+8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
 "sat16_asr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7848,23 +8337,25 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_lsr
+8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
 "sat16_lsr"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7873,21 +8364,23 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_lsr
+8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
 "sat16_lsr"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7896,22 +8389,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asl
+8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
 "sat16_asl"
 *am33
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7920,21 +8415,23 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asl
+8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
 "sat16_asl"
 *am33
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7943,12 +8440,244 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
+"mov_llt"
+*am33
+{
+  int srcreg, dstreg;
+  int result1;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+  State.regs[dstreg] = result1;
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
+"mov_lgt"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!((PSW & PSW_Z)
+        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
+"mov_lge"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
+"mov_lle"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if ((PSW & PSW_Z)
+      || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
+"mov_lcs"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (PSW & PSW_C)
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
+"mov_lhi"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
+"mov_lcc"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!(PSW & PSW_C))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
+"mov_lls"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
+"mov_leq"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (PSW & PSW_Z)
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
+"mov_lne"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!(PSW & PSW_Z))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
+"mov_lra"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+  nia = PC;
+}