case 4:
return REG_MCVF;
default:
- abort ();
+ sim_engine_abort (SD, CPU, cia, "%s:%d: bad switch\n", __FILE__, __LINE__);
}
}
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_USP];
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_A0 + AN0] = PC;
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_USP] = State.regs[REG_A0 + AM1];
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
8.0xf0+4.0xe,IMM4:D0t:::syscall
"syscall"
*am33
+*am33_2
{
unsigned32 sp, next_pc;
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
State.regs[REG_D0 + DN0] = PSW;
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
"mov"
*am33
+*am33_2
{
PC = cia;
PSW = State.regs[REG_D0 + DM1];
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RN0);
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
"mov"
*am33
+*am33_2
{
int destreg = translate_rreg (SD_, RM1);
8.0xf8+8.0xce+8.REGS:D1a:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x1)
8.0xf8+8.0xcf+8.REGS:D1b:::movm
"movm"
*am33
+*am33_2
{
unsigned32 usp = State.regs[REG_USP];
unsigned32 mask;
+ PC = cia;
+ mask = REGS;
+
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
)
{
if (mask & 0x4)
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
"and"
*am33
+*am33_2
{
PC = cia;
PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
"or"
*am33
+*am33_2
{
PC = cia;
PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
"extb"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
"extbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
"exth"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
"exthu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
"clr"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
"add"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
"addc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
"sub"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
"subc"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, c, n, v;
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
"inc"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
"inc4"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2;
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
"mov"
*am33
+*am33_2
{
int dstreg, srcreg;
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
"and"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
"or"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
"xor"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
"not"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
"asr"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
"lsr"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n, c;
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
"asl"
*am33
+*am33_2
{
int srcreg, dstreg;
int z, n;
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
"asl2"
*am33
+*am33_2
{
int dstreg;
int n, z;
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
"ror"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
"rol"
*am33
+*am33_2
{
int dstreg;
int c, n, z;
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
"mul"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
"div"
*am33
+*am33_2
{
int srcreg, dstreg;
signed64 temp;
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
"divu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned64 temp;
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned64 temp, sum;
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, sum;
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed64 temp, sum;
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2;
signed32 temp, temp2, sum;
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2;
unsigned32 temp, temp2, sum;
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg, dstreg;
signed32 temp;
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
"dmachu"
*am33
+*am33_2
{
int srcreg, dstreg;
unsigned32 temp;
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
"sat16"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, z, n;
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
"mcste"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
"swap"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
"swaph"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
"swhw"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg, dstreg;
if (start == -1)
start = 31;
+ c = 0;
for (i = start; i >= 0; i--)
{
if (temp & (1 << i))
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
"add"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
"addc"
*am33
+*am33_2
{
int dstreg, imm;
int z, c, n, v;
- unsigned32 reg1, reg2, sum;
+ unsigned32 reg2, sum;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
"subc"
*am33
+*am33_2
{
int imm, dstreg;
int z, c, n, v;
- unsigned32 reg1, reg2, difference;
+ unsigned32 reg2, difference;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z, n;
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
"asl"
*am33
+*am33_2
{
- int srcreg, dstreg;
+ int dstreg;
int z, n;
PC = cia;
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
"mcste"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
"add"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
"addc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 sum, source1, source2;
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
"sub"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
z = (difference == 0);
n = (difference & 0x80000000);
- c = (source1 > source1);
+ c = (source1 > source2);
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
&& (source1 & 0x80000000) != (difference & 0x80000000));
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
"subc"
*am33
+*am33_2
{
int z, c, n, v;
unsigned32 difference, source1, source2;
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
"and"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
"or"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
"xor"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
"asr"
*am33
+*am33_2
{
int z, c, n;
signed32 temp;
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
"lsr"
*am33
+*am33_2
{
int z, c, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
"asl"
*am33
+*am33_2
{
int z, n;
int srcreg1, srcreg2, dstreg;
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
"mul"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
"mulu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
"mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
PC = cia;
srcreg1 = translate_rreg (SD_, RM0);
- srcreg1 = translate_rreg (SD_, RI0);
+ srcreg2 = translate_rreg (SD_, RI0);
dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
}
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
PC = cia;
srcreg1 = translate_rreg (SD_, RM0);
- srcreg1 = translate_rreg (SD_, RI0);
+ srcreg2 = translate_rreg (SD_, RI0);
dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
}
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
PC = cia;
srcreg1 = translate_rreg (SD_, RM0);
- srcreg1 = translate_rreg (SD_, RI0);
+ srcreg2 = translate_rreg (SD_, RI0);
dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
}
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg1, dstreg2;
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
"mac"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
"macu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
"macb"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, sum;
8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
"mach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
"machu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp, sum;
8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg;
signed32 temp, temp2, sum;
8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
"dmulh"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed64 temp;
8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
"sat24"
*am33
+*am33_2
{
int srcreg, dstreg;
int value, n, z;
8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
"bsch"
*am33
+*am33_2
{
int temp, c, i;
int srcreg1, srcreg2, dstreg;
start = (State.regs[srcreg2] & 0x1f) - 1;
if (start == -1)
start = 31;
-
+
+ c = 0;
for (i = start; i >= 0; i--)
{
if (temp & (1 << i))
8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
"add"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
"addc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 sum, imm, reg2;
8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
"subc"
*am33
+*am33_2
{
int dstreg, z, n, c, v;
unsigned32 difference, imm, reg2;
8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
"asl"
*am33
+*am33_2
{
- int srcreg, dstreg;
+ int dstreg;
int z, n;
PC = cia;
8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
"mac"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
"macu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
"macb"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
"mach"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
"machu"
*am33
+*am33_2
{
int srcreg;
signed64 temp, sum;
8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
"movu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
"add"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
"addc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, sum;
8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
"sub"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
"subc"
*am33
+*am33_2
{
int dstreg;
unsigned32 imm, reg2, difference;
8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
"cmp"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
"and"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
"or"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
"xor"
*am33
+*am33_2
{
int dstreg;
int z,n;
8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
"asr"
*am33
+*am33_2
{
int dstreg;
signed32 temp;
8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
"lsr"
*am33
+*am33_2
{
int dstreg;
int z, n, c;
8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
"asl"
*am33
+*am33_2
{
- int srcreg, dstreg;
+ int dstreg;
int z, n;
PC = cia;
8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
"mul"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
"mulu"
*am33
+*am33_2
{
int dstreg;
unsigned64 temp;
8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
"btst"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
"mov"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
"mac"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
"macu"
*am33
+*am33_2
{
int srcreg, imm;
signed64 temp, sum;
8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
"macb"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
"macbu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
"mach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
"machu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, sum;
8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
"dmach"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
"dmachu"
*am33
+*am33_2
{
int srcreg, imm;
signed32 temp, temp2, sum;
8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
"dmulh"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
"dmulhu"
*am33
+*am33_2
{
int imm, dstreg;
signed32 temp;
8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
"mov"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
"mov"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
"movbu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
"movbu"
*am33
+*am33_2
{
int srcreg;
8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
"movhu"
*am33
+*am33_2
{
int dstreg;
8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
"movhu"
*am33
+*am33_2
{
int srcreg;
8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed int temp;
8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed int temp;
8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
- int result1;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
"add_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
"add_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
"add_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
"add_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
"add_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
"add_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
"add_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
"add_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
"add_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
"add_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
"add_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
"add_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
"cmp_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
"cmp_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
"cmp_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
signed int temp;
8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
"cmp_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
signed int temp;
8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
"cmp_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
"cmp_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
"sub_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
"sub_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
"sub_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
- int result1;
PC = cia;
srcreg2 = translate_rreg (SD_, RM2);
8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
"sub_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
- int result1;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
"sub_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
"sub_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
"sub_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
"sub_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
"mov_add"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
"mov_add"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
"mov_sub"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
"mov_cmp"
*am33
+*am33_2
{
int dstreg1, dstreg2;
8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
"mov_mov"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
"mov_asr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
"mov_lsr"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
"mov_asl"
*am33
+*am33_2
{
int dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
dstreg1 = translate_rreg (SD_, RN1);
8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
"and_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
"and_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
"and_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
"and_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
"and_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
"and_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
"and_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
"dmach_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
"dmach_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
"dmach_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
"dmach_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
"dmach_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
"dmach_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
"dmach_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
signed32 temp, temp2, sum;
8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
"xor_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
"xor_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
"xor_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
"xor_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
"xor_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
"xor_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
"xor_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
"swhw_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
"swhw_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
"swhw_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
"swhw_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
"swhw_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
"swhw_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
"swhw_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
"or_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
"or_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
"or_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
"or_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
"or_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
"or_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
"or_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
"sat16_add"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
"sat16_sub"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- int result1;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- State.regs[dstreg1] = result1;
+ genericCmp (State.regs[dstreg2], State.regs[dstreg1]);
if (State.regs[srcreg1] >= 0x7fff)
State.regs[dstreg1] = 0x7fff;
else if (State.regs[srcreg1] <= 0xffff8000)
8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
"sat16_cmp"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
"sat16_mov"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
"sat16_asr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
"sat16_lsr"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
int result1;
8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
"sat16_asl"
*am33
+*am33_2
{
int srcreg1, dstreg1, dstreg2;
int result1;
- signed int temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
"mov_llt"
*am33
+*am33_2
{
int srcreg, dstreg;
- int result1;
PC = cia;
srcreg = translate_rreg (SD_, RM);
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
- State.regs[dstreg] = result1;
}
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
"mov_lgt"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
"mov_lge"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
"mov_lle"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
"mov_lcs"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
"mov_lhi"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
"mov_lcc"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
"mov_lls"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
"mov_leq"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
"mov_lne"
*am33
+*am33_2
{
int srcreg, dstreg;
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
"mov_lra"
*am33
+*am33_2
{
int srcreg, dstreg;
nia = PC;
}
+:include::am33_2:am33-2.igen