* am33.igen: Autoincrement loads/store fixes.

[deliverable/binutils-gdb.git] / sim / mn10300 / simops.c

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index 719aaf573279e21b0d95f3d1e1e7574b0915dc0d..7a190566bcb68b167e027053eb8946351e4286f3 100644 (file)
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -6,7 +6,8 @@
 #endif
 #include "mn10300_sim.h"
 #include "simops.h"
-#include "sys/syscall.h"
+#include "sim-types.h"
+#include "targ-vals.h"
 #include "bfd.h"
 #include <errno.h>
 #include <sys/stat.h>
@@ -110,7 +111,7 @@ void OP_70 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1 (insn)]
-    = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
+    = load_word (State.regs[REG_A0 + REG0 (insn)]);
 }
 
 /* mov (d8,am), dn */
@@ -118,8 +119,7 @@ void OP_F80000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1_8 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
-                + SEXT8 (insn & 0xff)), 4);
+    = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)));
 }
 
 /* mov (d16,am), dn */
@@ -127,8 +127,8 @@ void OP_FA000000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1_16 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                + SEXT16 (insn & 0xffff)), 4);
+    = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
+                 + SEXT16 (insn & 0xffff)));
 }
 
 /* mov (d32,am), dn */
@@ -136,8 +136,8 @@ void OP_FC000000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1_16 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                + ((insn & 0xffff) << 16) + extension), 4);
+    = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
+                 + ((insn & 0xffff) << 16) + extension));
 }
 
 /* mov (d8,sp), dn */
@@ -145,7 +145,7 @@ void OP_5800 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_8 (insn)]
-    = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
+    = load_word (State.regs[REG_SP] + (insn & 0xff));
 }
 
 /* mov (d16,sp), dn */
@@ -153,7 +153,7 @@ void OP_FAB40000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_16 (insn)]
-    = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
+    = load_word (State.regs[REG_SP] + (insn & 0xffff));
 }
 
 /* mov (d32,sp), dn */
@@ -161,7 +161,7 @@ void OP_FCB40000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_16 (insn)]
-    = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
+    = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
 }
 
 /* mov (di,am), dn */
@@ -169,15 +169,15 @@ void OP_F300 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_4 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0 (insn)]
-                + State.regs[REG_D0 + REG1 (insn)]), 4);
+    = load_word ((State.regs[REG_A0 + REG0 (insn)]
+                 + State.regs[REG_D0 + REG1 (insn)]));
 }
 
 /* mov (abs16), dn */
 void OP_300000 (insn, extension)
      unsigned long insn, extension;
 {
-  State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
+  State.regs[REG_D0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
 }
 
 /* mov (abs32), dn */
@@ -185,7 +185,7 @@ void OP_FCA40000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_16 (insn)]
-    = load_mem ((((insn & 0xffff) << 16) + extension), 4);
+    = load_word ((((insn & 0xffff) << 16) + extension));
 }
 
 /* mov (am), an */
@@ -193,7 +193,7 @@ void OP_F000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_A0 + REG1 (insn)]
-    = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
+    = load_word (State.regs[REG_A0 + REG0 (insn)]);
 }
 
 /* mov (d8,am), an */
@@ -201,8 +201,8 @@ void OP_F82000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_A0 + REG1_8 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
-                + SEXT8 (insn & 0xff)), 4);
+    = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
+                 + SEXT8 (insn & 0xff)));
 }
 
 /* mov (d16,am), an */
@@ -210,8 +210,8 @@ void OP_FA200000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_A0 + REG1_16 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                + SEXT16 (insn & 0xffff)), 4);
+    = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
+                 + SEXT16 (insn & 0xffff)));
 }
 
 /* mov (d32,am), an */
@@ -219,8 +219,8 @@ void OP_FC200000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_A0 + REG1_16 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                + ((insn & 0xffff) << 16) + extension), 4);
+    = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
+                 + ((insn & 0xffff) << 16) + extension));
 }
 
 /* mov (d8,sp), an */
@@ -228,7 +228,7 @@ void OP_5C00 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_A0 + REG0_8 (insn)]
-    = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
+    = load_word (State.regs[REG_SP] + (insn & 0xff));
 }
 
 /* mov (d16,sp), an */
@@ -236,7 +236,7 @@ void OP_FAB00000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_A0 + REG0_16 (insn)]
-    = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
+    = load_word (State.regs[REG_SP] + (insn & 0xffff));
 }
 
 /* mov (d32,sp), an */
@@ -244,7 +244,7 @@ void OP_FCB00000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_A0 + REG0_16 (insn)]
-    = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
+    = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
 }
 
 /* mov (di,am), an */
@@ -252,15 +252,15 @@ void OP_F380 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_A0 + REG0_4 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0 (insn)]
-                + State.regs[REG_D0 + REG1 (insn)]), 4);
+    = load_word ((State.regs[REG_A0 + REG0 (insn)]
+                + State.regs[REG_D0 + REG1 (insn)]));
 }
 
 /* mov (abs16), an */
 void OP_FAA00000 (insn, extension)
      unsigned long insn, extension;
 {
-  State.regs[REG_A0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
+  State.regs[REG_A0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
 }
 
 /* mov (abs32), an */
@@ -268,7 +268,7 @@ void OP_FCA00000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_A0 + REG0_16 (insn)]
-    = load_mem ((((insn & 0xffff) << 16) + extension), 4);
+    = load_word ((((insn & 0xffff) << 16) + extension));
 }
 
 /* mov (d8,am), sp */
@@ -276,180 +276,177 @@ void OP_F8F000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_SP]
-    = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
-                + SEXT8 (insn & 0xff)), 4);
+    = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
+                 + SEXT8 (insn & 0xff)));
 }
 
 /* mov dm, (an) */
 void OP_60 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
-            State.regs[REG_D0 + REG1 (insn)]);
+  store_word (State.regs[REG_A0 + REG0 (insn)],
+             State.regs[REG_D0 + REG1 (insn)]);
 }
 
 /* mov dm, (d8,an) */
 void OP_F81000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
-             + SEXT8 (insn & 0xff)), 4,
-            State.regs[REG_D0 + REG1_8 (insn)]);
+  store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
+             State.regs[REG_D0 + REG1_8 (insn)]);
 }
 
 /* mov dm (d16,an) */
 void OP_FA100000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-             + SEXT16 (insn & 0xffff)), 4,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* mov dm (d32,an) */
 void OP_FC100000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-             + ((insn & 0xffff) << 16) + extension), 4,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_word ((State.regs[REG_A0 + REG0_16 (insn)]
+              + ((insn & 0xffff) << 16) + extension),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* mov dm, (d8,sp) */
 void OP_4200 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
-            State.regs[REG_D0 + REG1_8 (insn)]);
+  store_word (State.regs[REG_SP] + (insn & 0xff),
+             State.regs[REG_D0 + REG1_8 (insn)]);
 }
 
 /* mov dm, (d16,sp) */
 void OP_FA910000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_word (State.regs[REG_SP] + (insn & 0xffff),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* mov dm, (d32,sp) */
 void OP_FC910000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* mov dm, (di,an) */
 void OP_F340 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0 (insn)]
-             + State.regs[REG_D0 + REG1 (insn)]), 4,
-            State.regs[REG_D0 + REG0_4 (insn)]);
+  store_word ((State.regs[REG_A0 + REG0 (insn)]
+              + State.regs[REG_D0 + REG1 (insn)]),
+             State.regs[REG_D0 + REG0_4 (insn)]);
 }
 
 /* mov dm, (abs16) */
 void OP_10000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + REG1_16 (insn)]);
+  store_word ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* mov dm, (abs32) */
 void OP_FC810000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + REG1_16 (insn)]);
+  store_word ((((insn & 0xffff) << 16) + extension), 
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* mov am, (an) */
 void OP_F010 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
-            State.regs[REG_A0 + REG1 (insn)]);
+  store_word (State.regs[REG_A0 + REG0 (insn)],
+             State.regs[REG_A0 + REG1 (insn)]);
 }
 
 /* mov am, (d8,an) */
 void OP_F83000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
-             + SEXT8 (insn & 0xff)), 4,
-            State.regs[REG_A0 + REG1_8 (insn)]);
+  store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
+             State.regs[REG_A0 + REG1_8 (insn)]);
 }
 
 /* mov am, (d16,an) */
 void OP_FA300000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-             + SEXT16 (insn & 0xffff)), 4,
-            State.regs[REG_A0 + REG1_16 (insn)]);
+  store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
+             State.regs[REG_A0 + REG1_16 (insn)]);
 }
 
 /* mov am, (d32,an) */
 void OP_FC300000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-             + ((insn & 0xffff) << 16) + extension), 4,
-            State.regs[REG_A0 + REG1_16 (insn)]);
+  store_word ((State.regs[REG_A0 + REG0_16 (insn)]
+              + ((insn & 0xffff) << 16) + extension),
+             State.regs[REG_A0 + REG1_16 (insn)]);
 }
 
 /* mov am, (d8,sp) */
 void OP_4300 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
-            State.regs[REG_A0 + REG1_8 (insn)]);
+  store_word (State.regs[REG_SP] + (insn & 0xff),
+             State.regs[REG_A0 + REG1_8 (insn)]);
 }
 
 /* mov am, (d16,sp) */
 void OP_FA900000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
-            State.regs[REG_A0 + REG1_16 (insn)]);
+  store_word (State.regs[REG_SP] + (insn & 0xffff),
+             State.regs[REG_A0 + REG1_16 (insn)]);
 }
 
 /* mov am, (d32,sp) */
 void OP_FC900000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
-            State.regs[REG_A0 + REG1_16 (insn)]);
+  store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
+             State.regs[REG_A0 + REG1_16 (insn)]);
 }
 
 /* mov am, (di,an) */
 void OP_F3C0 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0 (insn)]
-             + State.regs[REG_D0 + REG1 (insn)]), 4,
-            State.regs[REG_A0 + REG0_4 (insn)]);
+  store_word ((State.regs[REG_A0 + REG0 (insn)]
+              + State.regs[REG_D0 + REG1 (insn)]),
+             State.regs[REG_A0 + REG0_4 (insn)]);
 }
 
 /* mov am, (abs16) */
 void OP_FA800000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + REG1_16 (insn)]);
+  store_word ((insn & 0xffff), State.regs[REG_A0 + REG1_16 (insn)]);
 }
 
 /* mov am, (abs32) */
 void OP_FC800000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + REG1_16 (insn)]);
+  store_word ((((insn & 0xffff) << 16) + extension), State.regs[REG_A0 + REG1_16 (insn)]);
 }
 
 /* mov sp, (d8,an) */
 void OP_F8F400 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
-            4, State.regs[REG_SP]);
+  store_word (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
+             State.regs[REG_SP]);
 }
 
 /* mov imm16, dn */
@@ -497,7 +494,7 @@ void OP_F040 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1 (insn)]
-    = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
+    = load_byte (State.regs[REG_A0 + REG0 (insn)]);
 }
 
 /* movbu (d8,am), dn */
@@ -505,8 +502,8 @@ void OP_F84000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1_8 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
-                + SEXT8 (insn & 0xff)), 1);
+    = load_byte ((State.regs[REG_A0 + REG0_8 (insn)]
+                 + SEXT8 (insn & 0xff)));
 }
 
 /* movbu (d16,am), dn */
@@ -514,8 +511,8 @@ void OP_FA400000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1_16 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                + SEXT16 (insn & 0xffff)), 1);
+    = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+                 + SEXT16 (insn & 0xffff)));
 }
 
 /* movbu (d32,am), dn */
@@ -523,8 +520,8 @@ void OP_FC400000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1_16 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                + ((insn & 0xffff) << 16) + extension), 1);
+    = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+                 + ((insn & 0xffff) << 16) + extension));
 }
 
 /* movbu (d8,sp), dn */
@@ -532,7 +529,7 @@ void OP_F8B800 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_8 (insn)]
-    = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
+    = load_byte ((State.regs[REG_SP] + (insn & 0xff)));
 }
 
 /* movbu (d16,sp), dn */
@@ -540,7 +537,7 @@ void OP_FAB80000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_16 (insn)]
-    = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
+    = load_byte ((State.regs[REG_SP] + (insn & 0xffff)));
 }
 
 /* movbu (d32,sp), dn */
@@ -548,7 +545,7 @@ void OP_FCB80000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_16 (insn)]
-    = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
+    = load_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
 }
 
 /* movbu (di,am), dn */
@@ -556,15 +553,15 @@ void OP_F400 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_4 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0 (insn)]
-                + State.regs[REG_D0 + REG1 (insn)]), 1);
+    = load_byte ((State.regs[REG_A0 + REG0 (insn)]
+                 + State.regs[REG_D0 + REG1 (insn)]));
 }
 
 /* movbu (abs16), dn */
 void OP_340000 (insn, extension)
      unsigned long insn, extension;
 {
-  State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 1);
+  State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff));
 }
 
 /* movbu (abs32), dn */
@@ -572,89 +569,87 @@ void OP_FCA80000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_16 (insn)]
-    = load_mem ((((insn & 0xffff) << 16) + extension), 1);
+    = load_byte ((((insn & 0xffff) << 16) + extension));
 }
 
 /* movbu dm, (an) */
 void OP_F050 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_A0 + REG0 (insn)], 1,
-            State.regs[REG_D0 + REG1 (insn)]);
+  store_byte (State.regs[REG_A0 + REG0 (insn)],
+             State.regs[REG_D0 + REG1 (insn)]);
 }
 
 /* movbu dm, (d8,an) */
 void OP_F85000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
-             + SEXT8 (insn & 0xff)), 1,
-            State.regs[REG_D0 + REG1_8 (insn)]);
+  store_byte ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
+             State.regs[REG_D0 + REG1_8 (insn)]);
 }
 
 /* movbu dm, (d16,an) */
 void OP_FA500000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-             + SEXT16 (insn & 0xffff)), 1,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movbu dm, (d32,an) */
 void OP_FC500000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-             + ((insn & 0xffff) << 16) + extension), 1,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+              + ((insn & 0xffff) << 16) + extension),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movbu dm, (d8,sp) */
 void OP_F89200 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
-            State.regs[REG_D0 + REG1_8 (insn)]);
+  store_byte (State.regs[REG_SP] + (insn & 0xff),
+             State.regs[REG_D0 + REG1_8 (insn)]);
 }
 
 /* movbu dm, (d16,sp) */
 void OP_FA920000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
-            State.regs[REG_D0 + REG1_8 (insn)]);
+  store_byte (State.regs[REG_SP] + (insn & 0xffff),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movbu dm (d32,sp) */
 void OP_FC920000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
-            State.regs[REG_D0 + REG1_8 (insn)]);
+  store_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movbu dm, (di,an) */
 void OP_F440 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0 (insn)]
-             + State.regs[REG_D0 + REG1 (insn)]), 1,
-            State.regs[REG_D0 + REG0_4 (insn)]);
+  store_byte ((State.regs[REG_A0 + REG0 (insn)]
+              + State.regs[REG_D0 + REG1 (insn)]),
+             State.regs[REG_D0 + REG0_4 (insn)]);
 }
 
 /* movbu dm, (abs16) */
 void OP_20000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + REG1_16 (insn)]);
+  store_byte ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movbu dm, (abs32) */
 void OP_FC820000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + REG1_16 (insn)]);
+  store_byte ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movhu (am), dn */
@@ -662,7 +657,7 @@ void OP_F060 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1 (insn)]
-    = load_mem (State.regs[REG_A0 + REG0 (insn)], 2);
+    = load_half (State.regs[REG_A0 + REG0 (insn)]);
 }
 
 /* movhu (d8,am), dn */
@@ -670,8 +665,8 @@ void OP_F86000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1_8 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
-                + SEXT8 (insn & 0xff)), 2);
+    = load_half ((State.regs[REG_A0 + REG0_8 (insn)]
+                 + SEXT8 (insn & 0xff)));
 }
 
 /* movhu (d16,am), dn */
@@ -679,8 +674,8 @@ void OP_FA600000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1_16 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                + SEXT16 (insn & 0xffff)), 2);
+    = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
+                 + SEXT16 (insn & 0xffff)));
 }
 
 /* movhu (d32,am), dn */
@@ -688,8 +683,8 @@ void OP_FC600000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG1_16 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                + ((insn & 0xffff) << 16) + extension), 2);
+    = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
+                 + ((insn & 0xffff) << 16) + extension));
 }
 
 /* movhu (d8,sp) dn */
@@ -697,7 +692,7 @@ void OP_F8BC00 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_8 (insn)]
-    = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
+    = load_half ((State.regs[REG_SP] + (insn & 0xff)));
 }
 
 /* movhu (d16,sp), dn */
@@ -705,7 +700,7 @@ void OP_FABC0000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_16 (insn)]
-    = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
+    = load_half ((State.regs[REG_SP] + (insn & 0xffff)));
 }
 
 /* movhu (d32,sp), dn */
@@ -713,7 +708,7 @@ void OP_FCBC0000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_16 (insn)]
-    = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
+    = load_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
 }
 
 /* movhu (di,am), dn */
@@ -721,15 +716,15 @@ void OP_F480 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_4 (insn)]
-    = load_mem ((State.regs[REG_A0 + REG0 (insn)]
-                + State.regs[REG_D0 + REG1 (insn)]), 2);
+    = load_half ((State.regs[REG_A0 + REG0 (insn)]
+                 + State.regs[REG_D0 + REG1 (insn)]));
 }
 
 /* movhu (abs16), dn */
 void OP_380000 (insn, extension)
      unsigned long insn, extension;
 {
-  State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 2);
+  State.regs[REG_D0 + REG0_16 (insn)] = load_half ((insn & 0xffff));
 }
 
 /* movhu (abs32), dn */
@@ -737,89 +732,87 @@ void OP_FCAC0000 (insn, extension)
      unsigned long insn, extension;
 {
   State.regs[REG_D0 + REG0_16 (insn)]
-    = load_mem ((((insn & 0xffff) << 16) + extension), 2);
+    = load_half ((((insn & 0xffff) << 16) + extension));
 }
 
 /* movhu dm, (an) */
 void OP_F070 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_A0 + REG0 (insn)], 2,
-            State.regs[REG_D0 + REG1 (insn)]);
+  store_half (State.regs[REG_A0 + REG0 (insn)],
+             State.regs[REG_D0 + REG1 (insn)]);
 }
 
 /* movhu dm, (d8,an) */
 void OP_F87000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
-             + SEXT8 (insn & 0xff)), 2,
-            State.regs[REG_D0 + REG1_8 (insn)]);
+  store_half ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
+             State.regs[REG_D0 + REG1_8 (insn)]);
 }
 
 /* movhu dm, (d16,an) */
 void OP_FA700000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-             + SEXT16 (insn & 0xffff)), 2,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_half ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movhu dm, (d32,an) */
 void OP_FC700000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-             + ((insn & 0xffff) << 16) + extension), 2,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_half ((State.regs[REG_A0 + REG0_16 (insn)]
+              + ((insn & 0xffff) << 16) + extension),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movhu dm,(d8,sp) */
 void OP_F89300 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
-            State.regs[REG_D0 + REG1_8 (insn)]);
+  store_half (State.regs[REG_SP] + (insn & 0xff),
+             State.regs[REG_D0 + REG1_8 (insn)]);
 }
 
 /* movhu dm,(d16,sp) */
 void OP_FA930000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_half (State.regs[REG_SP] + (insn & 0xffff),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movhu dm,(d32,sp) */
 void OP_FC930000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
-            State.regs[REG_D0 + REG1_16 (insn)]);
+  store_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
+             State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movhu dm, (di,an) */
 void OP_F4C0 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((State.regs[REG_A0 + REG0 (insn)]
-             + State.regs[REG_D0 + REG1 (insn)]), 2,
-            State.regs[REG_D0 + REG0_4 (insn)]);
+  store_half ((State.regs[REG_A0 + REG0 (insn)]
+              + State.regs[REG_D0 + REG1 (insn)]),
+             State.regs[REG_D0 + REG0_4 (insn)]);
 }
 
 /* movhu dm, (abs16) */
 void OP_30000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + REG1_16 (insn)]);
+  store_half ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* movhu dm, (abs32) */
 void OP_FC830000 (insn, extension)
      unsigned long insn, extension;
 {
-  store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + REG1_16 (insn)]);
+  store_half ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
 }
 
 /* ext dn */
@@ -873,43 +866,43 @@ void OP_CE00 (insn, extension)
   if (mask & 0x8)
     {
       sp += 4;
-      State.regs[REG_LAR] = load_mem (sp, 4);
+      State.regs[REG_LAR] = load_word (sp);
       sp += 4;
-      State.regs[REG_LIR] = load_mem (sp, 4);
+      State.regs[REG_LIR] = load_word (sp);
       sp += 4;
-      State.regs[REG_MDR] = load_mem (sp, 4);
+      State.regs[REG_MDR] = load_word (sp);
       sp += 4;
-      State.regs[REG_A0 + 1] = load_mem (sp, 4);
+      State.regs[REG_A0 + 1] = load_word (sp);
       sp += 4;
-      State.regs[REG_A0] = load_mem (sp, 4);
+      State.regs[REG_A0] = load_word (sp);
       sp += 4;
-      State.regs[REG_D0 + 1] = load_mem (sp, 4);
+      State.regs[REG_D0 + 1] = load_word (sp);
       sp += 4;
-      State.regs[REG_D0] = load_mem (sp, 4);
+      State.regs[REG_D0] = load_word (sp);
       sp += 4;
     }
 
   if (mask & 0x10)
     {
-      State.regs[REG_A0 + 3] = load_mem (sp, 4);
+      State.regs[REG_A0 + 3] = load_word (sp);
       sp += 4;
     }
 
   if (mask & 0x20)
     {
-      State.regs[REG_A0 + 2] = load_mem (sp, 4);
+      State.regs[REG_A0 + 2] = load_word (sp);
       sp += 4;
     }
 
   if (mask & 0x40)
     {
-      State.regs[REG_D0 + 3] = load_mem (sp, 4);
+      State.regs[REG_D0 + 3] = load_word (sp);
       sp += 4;
     }
 
   if (mask & 0x80)
     {
-      State.regs[REG_D0 + 2] = load_mem (sp, 4);
+      State.regs[REG_D0 + 2] = load_word (sp);
       sp += 4;
     }
 
@@ -929,43 +922,43 @@ void OP_CF00 (insn, extension)
   if (mask & 0x80)
     {
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_D0 + 2]);
+      store_word (sp, State.regs[REG_D0 + 2]);
     }
 
   if (mask & 0x40)
     {
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_D0 + 3]);
+      store_word (sp, State.regs[REG_D0 + 3]);
     }
 
   if (mask & 0x20)
     {
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_A0 + 2]);
+      store_word (sp, State.regs[REG_A0 + 2]);
     }
 
   if (mask & 0x10)
     {
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_A0 + 3]);
+      store_word (sp, State.regs[REG_A0 + 3]);
     }
 
   if (mask & 0x8)
     {
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_D0]);
+      store_word (sp, State.regs[REG_D0]);
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_D0 + 1]);
+      store_word (sp, State.regs[REG_D0 + 1]);
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_A0]);
+      store_word (sp, State.regs[REG_A0]);
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_A0 + 1]);
+      store_word (sp, State.regs[REG_A0 + 1]);
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_MDR]);
+      store_word (sp, State.regs[REG_MDR]);
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_LIR]);
+      store_word (sp, State.regs[REG_LIR]);
       sp -= 4;
-      store_mem (sp, 4, State.regs[REG_LAR]);
+      store_word (sp, State.regs[REG_LAR]);
       sp -= 4;
     }
 
@@ -997,7 +990,7 @@ void OP_E0 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
@@ -1020,7 +1013,7 @@ void OP_F160 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
@@ -1043,7 +1036,7 @@ void OP_F150 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
@@ -1066,7 +1059,7 @@ void OP_F170 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
@@ -1089,7 +1082,7 @@ void OP_2800 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1112,7 +1105,7 @@ void OP_FAC00000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1135,7 +1128,7 @@ void OP_FCC00000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1158,7 +1151,7 @@ void OP_2000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1181,7 +1174,7 @@ void OP_FAD00000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1204,7 +1197,7 @@ void OP_FCD00000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1263,7 +1256,7 @@ void OP_F140 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
@@ -1282,6 +1275,7 @@ void OP_F100 (insn, extension)
   reg1 = State.regs[REG_D0 + REG1 (insn)];
   reg2 = State.regs[REG_D0 + REG0 (insn)];
   value = reg2 - reg1;
+  State.regs[REG_D0 + REG0 (insn)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1292,7 +1286,6 @@ void OP_F100 (insn, extension)
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-  State.regs[REG_D0 + REG0 (insn)] = value;
 }
 
 /* sub dm, an */
@@ -1305,6 +1298,7 @@ void OP_F120 (insn, extension)
   reg1 = State.regs[REG_D0 + REG1 (insn)];
   reg2 = State.regs[REG_A0 + REG0 (insn)];
   value = reg2 - reg1;
+  State.regs[REG_A0 + REG0 (insn)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1315,7 +1309,6 @@ void OP_F120 (insn, extension)
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-  State.regs[REG_A0 + REG0 (insn)] = value;
 }
 
 /* sub am, dn */
@@ -1328,6 +1321,7 @@ void OP_F110 (insn, extension)
   reg1 = State.regs[REG_A0 + REG1 (insn)];
   reg2 = State.regs[REG_D0 + REG0 (insn)];
   value = reg2 - reg1;
+  State.regs[REG_D0 + REG0 (insn)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1338,7 +1332,6 @@ void OP_F110 (insn, extension)
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-  State.regs[REG_D0 + REG0 (insn)] = value;
 }
 
 /* sub am, an */
@@ -1351,6 +1344,7 @@ void OP_F130 (insn, extension)
   reg1 = State.regs[REG_A0 + REG1 (insn)];
   reg2 = State.regs[REG_A0 + REG0 (insn)];
   value = reg2 - reg1;
+  State.regs[REG_A0 + REG0 (insn)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1361,7 +1355,6 @@ void OP_F130 (insn, extension)
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-  State.regs[REG_A0 + REG0 (insn)] = value;
 }
 
 /* sub imm32, dn */
@@ -1374,6 +1367,7 @@ void OP_FCC40000 (insn, extension)
   reg1 = State.regs[REG_D0 + REG0_16 (insn)];
   imm = ((insn & 0xffff) << 16) + extension;
   value = reg1 - imm;
+  State.regs[REG_D0 + REG0_16 (insn)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1384,7 +1378,6 @@ void OP_FCC40000 (insn, extension)
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-  State.regs[REG_D0 + REG0_16 (insn)] = value;
 }
 
 /* sub imm32, an */
@@ -1397,6 +1390,7 @@ void OP_FCD40000 (insn, extension)
   reg1 = State.regs[REG_A0 + REG0_16 (insn)];
   imm = ((insn & 0xffff) << 16) + extension;
   value = reg1 - imm;
+  State.regs[REG_A0 + REG0_16 (insn)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1407,7 +1401,6 @@ void OP_FCD40000 (insn, extension)
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-  State.regs[REG_A0 + REG0_16 (insn)] = value;
 }
 
 /* subc dm, dn */
@@ -1420,6 +1413,7 @@ void OP_F180 (insn, extension)
   reg1 = State.regs[REG_D0 + REG1 (insn)];
   reg2 = State.regs[REG_D0 + REG0 (insn)];
   value = reg2 - reg1 - ((PSW & PSW_C) != 0);
+  State.regs[REG_D0 + REG0 (insn)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1430,7 +1424,6 @@ void OP_F180 (insn, extension)
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
-  State.regs[REG_D0 + REG0 (insn)] = value;
 }
 
 /* mul dm, dn */
@@ -1440,10 +1433,10 @@ void OP_F240 (insn, extension)
   unsigned long long temp;
   int n, z;
 
-  temp = (State.regs[REG_D0 + REG0 (insn)]
-          *  State.regs[REG_D0 + REG1 (insn)]);
+  temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)]
+          *  (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]);
   State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
-  State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + REG0 (insn)] == 0);
   n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1457,10 +1450,10 @@ void OP_F250 (insn, extension)
   unsigned long long temp;
   int n, z;
 
-  temp = (State.regs[REG_D0 + REG0 (insn)]
-          *  State.regs[REG_D0 + REG1 (insn)]);
+  temp = ((unsigned64)State.regs[REG_D0 + REG0 (insn)]
+          * (unsigned64)State.regs[REG_D0 + REG1 (insn)]);
   State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
-  State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[REG_D0 + REG0 (insn)] == 0);
   n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1480,7 +1473,6 @@ void OP_F260 (insn, extension)
   State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)];
   temp /= (long)State.regs[REG_D0 + REG1 (insn)];
   State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
-  State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
   z = (State.regs[REG_D0 + REG0 (insn)] == 0);
   n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1500,7 +1492,6 @@ void OP_F270 (insn, extension)
   State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)];
   temp /= State.regs[REG_D0 + REG1 (insn)];
   State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
-  State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
   z = (State.regs[REG_D0 + REG0 (insn)] == 0);
   n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1521,7 +1512,7 @@ void OP_40 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1884,7 +1875,7 @@ void OP_FAFD0000 (insn, extension)
   PSW |= (insn & 0xffff);
 }
 
-/* xor dm, dn*/
+/* xor dm, dn */
 void OP_F220 (insn, extension)
      unsigned long insn, extension;
 {
@@ -1989,7 +1980,7 @@ void OP_FE020000 (insn, extension)
   unsigned long temp;
   int n, z;
 
-  temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
+  temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
   temp &= (extension & 0xff);
   n = (temp & 0x80000000) != 0;
   z = (temp == 0);
@@ -2004,8 +1995,8 @@ void OP_FAF80000 (insn, extension)
   unsigned long temp;
   int n, z;
 
-  temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                    + SEXT8 ((insn & 0xff00) >> 8)), 1);
+  temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+                     + SEXT8 ((insn & 0xff00) >> 8)));
   temp &= (insn & 0xff);
   n = (temp & 0x80000000) != 0;
   z = (temp == 0);
@@ -2020,10 +2011,10 @@ void OP_F080 (insn, extension)
   unsigned long temp;
   int z;
 
-  temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
+  temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
   z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
   temp |= State.regs[REG_D0 + REG1 (insn)];
-  store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
+  store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
 }
@@ -2035,10 +2026,10 @@ void OP_FE000000 (insn, extension)
   unsigned long temp;
   int z;
 
-  temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
+  temp = load_byte (((insn & 0xffff) << 16 | (extension >> 8)));
   z = (temp & (extension & 0xff)) == 0;
   temp |= (extension & 0xff);
-  store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
+  store_byte ((((insn & 0xffff) << 16) | (extension >> 8)), temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
 }
@@ -2050,11 +2041,12 @@ void OP_FAF00000 (insn, extension)
   unsigned long temp;
   int z;
 
-  temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                    + SEXT8 ((insn & 0xff00) >> 8)), 1);
+  temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+                     + SEXT8 ((insn & 0xff00) >> 8)));
   z = (temp & (insn & 0xff)) == 0;
   temp |= (insn & 0xff);
-  store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
+  store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+              + SEXT8 ((insn & 0xff00) >> 8)), temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
 }
@@ -2066,10 +2058,10 @@ void OP_F090 (insn, extension)
   unsigned long temp;
   int z;
 
-  temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
+  temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
   z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
-  temp = ~temp & State.regs[REG_D0 + REG1 (insn)];
-  store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
+  temp = temp & ~State.regs[REG_D0 + REG1 (insn)];
+  store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
 }
@@ -2081,10 +2073,10 @@ void OP_FE010000 (insn, extension)
   unsigned long temp;
   int z;
 
-  temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
+  temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
   z = (temp & (extension & 0xff)) == 0;
-  temp = ~temp & (extension & 0xff);
-  store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
+  temp = temp & ~(extension & 0xff);
+  store_byte (((insn & 0xffff) << 16) | (extension >> 8), temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
 }
@@ -2096,11 +2088,12 @@ void OP_FAF40000 (insn, extension)
   unsigned long temp;
   int z;
 
-  temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
-                    + SEXT8 ((insn & 0xff00) >> 8)), 1);
+  temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+                     + SEXT8 ((insn & 0xff00) >> 8)));
   z = (temp & (insn & 0xff)) == 0;
-  temp = ~temp & (insn & 0xff);
-  store_mem (State.regs[REG_A0 + REG0_16 (insn)], 1, temp);
+  temp = temp & ~(insn & 0xff);
+  store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+              + SEXT8 ((insn & 0xff00) >> 8)), temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
 }
@@ -2154,7 +2147,7 @@ void OP_F2A0 (insn, extension)
   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
 }
 
-/* lsr dm, dn */
+/* lsr imm8, dn */
 void OP_F8C400 (insn, extension)
      unsigned long insn, extension;
 {
@@ -2162,8 +2155,8 @@ void OP_F8C400 (insn, extension)
 
   c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
   State.regs[REG_D0 + REG0_8 (insn)] >>=  (insn & 0xff);
-  z = (State.regs[REG_D0 + (REG0 (insn) >> 8)] == 0);
-  n = (State.regs[REG_D0 + (REG0 (insn) >> 8)] & 0x80000000) != 0;
+  z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C);
   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
 }
@@ -2253,7 +2246,7 @@ void OP_C800 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (PSW & PSW_Z)
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bne label:8 */
@@ -2263,7 +2256,7 @@ void OP_C900 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (!(PSW & PSW_Z))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bgt label:8 */
@@ -2274,7 +2267,7 @@ void OP_C100 (insn, extension)
      we subtract two here to make things right.  */
   if (!((PSW & PSW_Z)
         || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bge label:8 */
@@ -2284,7 +2277,7 @@ void OP_C200 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* ble label:8 */
@@ -2295,7 +2288,7 @@ void OP_C300 (insn, extension)
      we subtract two here to make things right.  */
   if ((PSW & PSW_Z)
        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* blt label:8 */
@@ -2305,7 +2298,7 @@ void OP_C000 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bhi label:8 */
@@ -2315,7 +2308,7 @@ void OP_C500 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bcc label:8 */
@@ -2325,7 +2318,7 @@ void OP_C600 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (!(PSW & PSW_C))
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bls label:8 */
@@ -2335,7 +2328,7 @@ void OP_C700 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bcs label:8 */
@@ -2345,7 +2338,7 @@ void OP_C400 (insn, extension)
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
   if (PSW & PSW_C)
-    State.pc += SEXT8 (insn & 0xff) - 2;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* bvc label:8 */
@@ -2355,7 +2348,7 @@ void OP_F8E800 (insn, extension)
   /* The dispatching code will add 3 after we return, so
      we subtract two here to make things right.  */
   if (!(PSW & PSW_V))
-    State.pc += SEXT8 (insn & 0xff) - 3;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
 }
 
 /* bvs label:8 */
@@ -2365,7 +2358,7 @@ void OP_F8E900 (insn, extension)
   /* The dispatching code will add 3 after we return, so
      we subtract two here to make things right.  */
   if (PSW & PSW_V)
-    State.pc += SEXT8 (insn & 0xff) - 3;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
 }
 
 /* bnc label:8 */
@@ -2375,7 +2368,7 @@ void OP_F8EA00 (insn, extension)
   /* The dispatching code will add 3 after we return, so
      we subtract two here to make things right.  */
   if (!(PSW & PSW_N))
-    State.pc += SEXT8 (insn & 0xff) - 3;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
 }
 
 /* bns label:8 */
@@ -2385,7 +2378,7 @@ void OP_F8EB00 (insn, extension)
   /* The dispatching code will add 3 after we return, so
      we subtract two here to make things right.  */
   if (PSW & PSW_N)
-    State.pc += SEXT8 (insn & 0xff) - 3;
+    State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
 }
 
 /* bra label:8 */
@@ -2394,123 +2387,156 @@ void OP_CA00 (insn, extension)
 {
   /* The dispatching code will add 2 after we return, so
      we subtract two here to make things right.  */
-  State.pc += SEXT8 (insn & 0xff) - 2;
+  State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
 }
 
 /* leq */
 void OP_D8 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if (PSW & PSW_Z)
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* lne */
 void OP_D9 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if (!(PSW & PSW_Z))
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* lgt */
 void OP_D1 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if (!((PSW & PSW_Z)
+        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* lge */
 void OP_D2 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* lle */
 void OP_D3 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if ((PSW & PSW_Z)
+       || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* llt */
 void OP_D0 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* lhi */
 void OP_D5 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* lcc */
 void OP_D6 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if (!(PSW & PSW_C))
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* lls */
 void OP_D7 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* lcs */
 void OP_D4 (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  /* The dispatching code will add 1 after we return, so
+     we subtract one here to make things right.  */
+  if (PSW & PSW_C)
+    State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* lra */
 void OP_DA (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
 }
 
 /* setlb */
 void OP_DB (insn, extension)
      unsigned long insn, extension;
 {
- abort ();
+  State.regs[REG_LIR] = load_mem_big (State.regs[REG_PC] + 1, 4);
+  State.regs[REG_LAR] = State.regs[REG_PC] + 5;
 }
 
 /* jmp (an) */
 void OP_F0F4 (insn, extension)
      unsigned long insn, extension;
 {
-  State.pc = State.regs[REG_A0 + REG0 (insn)] - 2;
+  State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
 }
 
 /* jmp label:16 */
 void OP_CC0000 (insn, extension)
      unsigned long insn, extension;
 {
-  State.pc += SEXT16 (insn & 0xffff) - 3;
+  State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3;
 }
 
 /* jmp label:32 */
 void OP_DC000000 (insn, extension)
      unsigned long insn, extension;
 {
-  State.pc += (((insn & 0xffffff) << 8) + extension) - 5;
+  State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5;
 }
 
 /* call label:16,reg_list,imm8 */
 void OP_CD000000 (insn, extension)
      unsigned long insn, extension;
 {
-  unsigned int next_pc, sp, adjust;
+  unsigned int next_pc, sp;
   unsigned long mask;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 2;
+  next_pc = State.regs[REG_PC] + 5;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
@@ -2518,54 +2544,55 @@ void OP_CD000000 (insn, extension)
 
   mask = insn & 0xff;
 
-  adjust = 0;
   if (mask & 0x80)
     {
-      adjust -= 4;
-      State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
+      sp -= 4;
+      store_word (sp, State.regs[REG_D0 + 2]);
     }
 
   if (mask & 0x40)
     {
-      adjust -= 4;
-      State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
+      sp -= 4;
+      store_word (sp, State.regs[REG_D0 + 3]);
     }
 
   if (mask & 0x20)
     {
-      adjust -= 4;
-      State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
+      sp -= 4;
+      store_word (sp, State.regs[REG_A0 + 2]);
     }
 
   if (mask & 0x10)
     {
-      adjust -= 4;
-      State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
+      sp -= 4;
+      store_word (sp, State.regs[REG_A0 + 3]);
     }
 
   if (mask & 0x8)
     {
-      adjust -= 4;
-      State.regs[REG_D0] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_A0] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_MDR] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_LIR] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_LAR] = load_mem (sp + adjust, 4);
-      adjust -= 4;
+      sp -= 4;
+      store_word (sp, State.regs[REG_D0]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_D0 + 1]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_A0]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_A0 + 1]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_MDR]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_LIR]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_LAR]);
+      sp -= 4;
     }
 
-  /* And make sure to update the stack pointer.  */
+  /* Update the stack pointer, note that the register saves to do not
+     modify SP.  The SP adjustment is derived totally from the imm8
+     field.  */
   State.regs[REG_SP] -= extension;
   State.regs[REG_MDR] = next_pc;
-  State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
+  State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5;
 }
 
 /* call label:32,reg_list,imm8*/
@@ -2576,7 +2603,7 @@ void OP_DD000000 (insn, extension)
   unsigned long mask;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 2;
+  next_pc = State.regs[REG_PC] + 7;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
@@ -2584,54 +2611,55 @@ void OP_DD000000 (insn, extension)
 
   mask = (extension & 0xff00) >> 8;
 
-  adjust = 0;
   if (mask & 0x80)
     {
-      adjust -= 4;
-      State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
+      sp -= 4;
+      store_word (sp, State.regs[REG_D0 + 2]);
     }
 
   if (mask & 0x40)
     {
-      adjust -= 4;
-      State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
+      sp -= 4;
+      store_word (sp, State.regs[REG_D0 + 3]);
     }
 
   if (mask & 0x20)
     {
-      adjust -= 4;
-      State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
+      sp -= 4;
+      store_word (sp, State.regs[REG_A0 + 2]);
     }
 
   if (mask & 0x10)
     {
-      adjust -= 4;
-      State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
+      sp -= 4;
+      store_word (sp, State.regs[REG_A0 + 3]);
     }
 
   if (mask & 0x8)
     {
-      adjust -= 4;
-      State.regs[REG_D0] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_A0] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_MDR] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_LIR] = load_mem (sp + adjust, 4);
-      adjust -= 4;
-      State.regs[REG_LAR] = load_mem (sp + adjust, 4);
-      adjust -= 4;
+      sp -= 4;
+      store_word (sp, State.regs[REG_D0]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_D0 + 1]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_A0]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_A0 + 1]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_MDR]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_LIR]);
+      sp -= 4;
+      store_word (sp, State.regs[REG_LAR]);
+      sp -= 4;
     }
 
-  /* And make sure to update the stack pointer.  */
+  /* Update the stack pointer, note that the register saves to do not
+     modify SP.  The SP adjustment is derived totally from the imm8
+     field.  */
   State.regs[REG_SP] -= (extension & 0xff);
   State.regs[REG_MDR] = next_pc;
-  State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
+  State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
 }
 
 /* calls (an) */
@@ -2641,13 +2669,13 @@ void OP_F0F0 (insn, extension)
   unsigned int next_pc, sp;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 2;
+  next_pc = State.regs[REG_PC] + 2;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
   State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
   State.regs[REG_MDR] = next_pc;
-  State.pc = State.regs[REG_A0 + REG0 (insn)] - 2;
+  State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
 }
 
 /* calls label:16 */
@@ -2657,13 +2685,13 @@ void OP_FAFF0000 (insn, extension)
   unsigned int next_pc, sp;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 4;
+  next_pc = State.regs[REG_PC] + 4;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
   State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
   State.regs[REG_MDR] = next_pc;
-  State.pc += SEXT16 (insn & 0xffff) - 4;
+  State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4;
 }
 
 /* calls label:32 */
@@ -2673,139 +2701,131 @@ void OP_FCFF0000 (insn, extension)
   unsigned int next_pc, sp;
 
   sp = State.regs[REG_SP];
-  next_pc = State.pc + 6;
+  next_pc = State.regs[REG_PC] + 6;
   State.mem[sp] = next_pc & 0xff;
   State.mem[sp+1] = (next_pc & 0xff00) >> 8;
   State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
   State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
   State.regs[REG_MDR] = next_pc;
-  State.pc += (((insn & 0xffff) << 16) + extension) - 6;
+  State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6;
 }
 
 /* ret reg_list, imm8 */
 void OP_DF0000 (insn, extension)
      unsigned long insn, extension;
 {
-  unsigned int sp;
+  unsigned int sp, offset;
   unsigned long mask;
 
   State.regs[REG_SP] += insn & 0xff;
   sp = State.regs[REG_SP];
 
+  offset = -4;
   mask = (insn & 0xff00) >> 8;
 
-  if (mask & 0x8)
+  if (mask & 0x80)
     {
-      sp += 4;
-      State.regs[REG_LAR] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_LIR] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_MDR] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_A0 + 1] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_A0] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_D0 + 1] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_D0] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_D0 + 2] = load_word (sp + offset);
+      offset -= 4;
     }
 
-  if (mask & 0x10)
+  if (mask & 0x40)
     {
-      State.regs[REG_A0 + 3] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_D0 + 3] = load_word (sp + offset);
+      offset -= 4;
     }
 
   if (mask & 0x20)
     {
-      State.regs[REG_A0 + 2] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_A0 + 2] = load_word (sp + offset);
+      offset -= 4;
     }
 
-  if (mask & 0x40)
+  if (mask & 0x10)
     {
-      State.regs[REG_D0 + 3] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_A0 + 3] = load_word (sp + offset);
+      offset -= 4;
     }
 
-  if (mask & 0x80)
+  if (mask & 0x8)
     {
-      State.regs[REG_D0 + 2] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_D0] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_D0 + 1] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_A0] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_A0 + 1] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_MDR] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_LIR] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_LAR] = load_word (sp + offset);
+      offset -= 4;
     }
 
-  /* And make sure to update the stack pointer.  */
-  State.regs[REG_SP] = sp;
-
   /* Restore the PC value.  */
-  State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
+  State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
              | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
-  State.pc -= 3;
+  State.regs[REG_PC] -= 3;
 }
 
 /* retf reg_list,imm8 */
 void OP_DE0000 (insn, extension)
      unsigned long insn, extension;
 {
-  unsigned int sp;
+  unsigned int sp, offset;
   unsigned long mask;
 
-  sp = State.regs[REG_SP] + (insn & 0xff);
-  State.regs[REG_SP] = sp;
-  State.pc = State.regs[REG_MDR] - 3;
-
+  State.regs[REG_SP] += (insn & 0xff);
   sp = State.regs[REG_SP];
+  State.regs[REG_PC] = State.regs[REG_MDR] - 3;
 
+  offset = -4;
   mask = (insn & 0xff00) >> 8;
 
-  if (mask & 0x8)
+  if (mask & 0x80)
     {
-      sp += 4;
-      State.regs[REG_LAR] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_LIR] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_MDR] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_A0 + 1] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_A0] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_D0 + 1] = load_mem (sp, 4);
-      sp += 4;
-      State.regs[REG_D0] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_D0 + 2] = load_word (sp + offset);
+      offset -= 4;
     }
 
-  if (mask & 0x10)
+  if (mask & 0x40)
     {
-      State.regs[REG_A0 + 3] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_D0 + 3] = load_word (sp + offset);
+      offset -= 4;
     }
 
   if (mask & 0x20)
     {
-      State.regs[REG_A0 + 2] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_A0 + 2] = load_word (sp + offset);
+      offset -= 4;
     }
 
-  if (mask & 0x40)
+  if (mask & 0x10)
     {
-      State.regs[REG_D0 + 3] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_A0 + 3] = load_word (sp + offset);
+      offset -= 4;
     }
 
-  if (mask & 0x80)
+  if (mask & 0x8)
     {
-      State.regs[REG_D0 + 2] = load_mem (sp, 4);
-      sp += 4;
+      State.regs[REG_D0] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_D0 + 1] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_A0] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_A0 + 1] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_MDR] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_LIR] = load_word (sp + offset);
+      offset -= 4;
+      State.regs[REG_LAR] = load_word (sp + offset);
+      offset -= 4;
     }
-
-  /* And make sure to update the stack pointer.  */
-  State.regs[REG_SP] = sp;
 }
 
 /* rets */
@@ -2815,21 +2835,42 @@ void OP_F0FC (insn, extension)
   unsigned int sp;
 
   sp = State.regs[REG_SP];
-  State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
+  State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
              | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
-  State.pc -= 2;
+  State.regs[REG_PC] -= 2;
 }
 
 /* rti */
 void OP_F0FD (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  unsigned int sp, next_pc;
+
+  sp = State.regs[REG_SP];
+  PSW = State.mem[sp] | (State.mem[sp + 1] << 8);
+  State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8)
+             | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24));
+  State.regs[REG_SP] += 8;
 }
 
 /* trap */
 void OP_F0FE (insn, extension)
      unsigned long insn, extension;
+{
+  unsigned int sp, next_pc;
+
+  sp = State.regs[REG_SP];
+  next_pc = State.regs[REG_PC] + 2;
+  State.mem[sp] = next_pc & 0xff;
+  State.mem[sp+1] = (next_pc & 0xff00) >> 8;
+  State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
+  State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
+  State.regs[REG_PC] = 0x40000010 - 2;
+}
+
+/* syscall */
+void OP_F0C0 (insn, extension)
+     unsigned long insn, extension;
 {
   /* We use this for simulated system calls; we may need to change
      it to a reserved instruction if we conflict with uses at
@@ -2840,12 +2881,12 @@ void OP_F0FE (insn, extension)
 /* Registers passed to trap 0 */
 
 /* Function number.  */
-#define FUNC   (load_mem (State.regs[REG_SP] + 4, 4))
+#define FUNC   (State.regs[0])
 
 /* Parameters.  */
-#define PARM1   (load_mem (State.regs[REG_SP] + 8, 4))
-#define PARM2   (load_mem (State.regs[REG_SP] + 12, 4))
-#define PARM3   (load_mem (State.regs[REG_SP] + 16, 4))
+#define PARM1   (State.regs[1])
+#define PARM2   (load_word (State.regs[REG_SP] + 12))
+#define PARM3   (load_word (State.regs[REG_SP] + 16))
 
 /* Registers set by trap 0 */
 
@@ -2859,49 +2900,52 @@ void OP_F0FE (insn, extension)
   switch (FUNC)
     {
 #if !defined(__GO32__) && !defined(_WIN32)
-      case SYS_fork:
+#ifdef TARGET_SYS_fork
+      case TARGET_SYS_fork:
       RETVAL = fork ();
       break;
-    case SYS_execve:
+#endif
+#ifdef TARGET_SYS_execve
+    case TARGET_SYS_execve:
       RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
                       (char **)MEMPTR (PARM3));
       break;
-    case SYS_execv:
+#endif
+#ifdef TARGET_SYS_execv
+    case TARGET_SYS_execv:
       RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
       break;
 #endif
+#endif /* ! GO32 and ! WIN32 */
 
-    case SYS_read:
+    case TARGET_SYS_read:
       RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
                                    MEMPTR (PARM2), PARM3);
       break;
-    case SYS_write:
-      if (PARM1 == 1)
-       RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
-                                                  MEMPTR (PARM2), PARM3);
-      else
-       RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
-                                           MEMPTR (PARM2), PARM3);
+    case TARGET_SYS_write:
+      RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
+                                            MEMPTR (PARM2), PARM3);
       break;
-    case SYS_lseek:
+    case TARGET_SYS_lseek:
       RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
       break;
-    case SYS_close:
+    case TARGET_SYS_close:
       RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
       break;
-    case SYS_open:
+    case TARGET_SYS_open:
       RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
       break;
-    case SYS_exit:
+    case TARGET_SYS_exit:
       /* EXIT - caller can look in PARM1 to work out the 
         reason */
-      if (PARM1 == 0xdead || PARM1 == 0x1)
+      if (PARM1 == 0xdead)
        State.exception = SIGABRT;
       else
        State.exception = SIGQUIT;
+      State.exited = 1;
       break;
 
-    case SYS_stat:     /* added at hmsi */
+    case TARGET_SYS_stat:      /* added at hmsi */
       /* stat system call */
       {
        struct stat host_stat;
@@ -2912,55 +2956,65 @@ void OP_F0FE (insn, extension)
        buf = PARM2;
 
        /* Just wild-assed guesses.  */
-       store_mem (buf, 2, host_stat.st_dev);
-       store_mem (buf + 2, 2, host_stat.st_ino);
-       store_mem (buf + 4, 4, host_stat.st_mode);
-       store_mem (buf + 8, 2, host_stat.st_nlink);
-       store_mem (buf + 10, 2, host_stat.st_uid);
-       store_mem (buf + 12, 2, host_stat.st_gid);
-       store_mem (buf + 14, 2, host_stat.st_rdev);
-       store_mem (buf + 16, 4, host_stat.st_size);
-       store_mem (buf + 20, 4, host_stat.st_atime);
-       store_mem (buf + 28, 4, host_stat.st_mtime);
-       store_mem (buf + 36, 4, host_stat.st_ctime);
+       store_half (buf, host_stat.st_dev);
+       store_half (buf + 2, host_stat.st_ino);
+       store_word (buf + 4, host_stat.st_mode);
+       store_half (buf + 8, host_stat.st_nlink);
+       store_half (buf + 10, host_stat.st_uid);
+       store_half (buf + 12, host_stat.st_gid);
+       store_half (buf + 14, host_stat.st_rdev);
+       store_word (buf + 16, host_stat.st_size);
+       store_word (buf + 20, host_stat.st_atime);
+       store_word (buf + 28, host_stat.st_mtime);
+       store_word (buf + 36, host_stat.st_ctime);
       }
       break;
 
-    case SYS_chown:
+#ifdef TARGET_SYS_chown
+    case TARGET_SYS_chown:
       RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
       break;
-    case SYS_chmod:
+#endif
+    case TARGET_SYS_chmod:
       RETVAL = chmod (MEMPTR (PARM1), PARM2);
       break;
-    case SYS_time:
-      RETVAL = time (MEMPTR (PARM1));
+#ifdef TARGET_SYS_time
+    case TARGET_SYS_time:
+      RETVAL = time ((void*) MEMPTR (PARM1));
       break;
-    case SYS_times:
+#endif
+#ifdef TARGET_SYS_times
+    case TARGET_SYS_times:
       {
        struct tms tms;
        RETVAL = times (&tms);
-       store_mem (PARM1, 4, tms.tms_utime);
-       store_mem (PARM1 + 4, 4, tms.tms_stime);
-       store_mem (PARM1 + 8, 4, tms.tms_cutime);
-       store_mem (PARM1 + 12, 4, tms.tms_cstime);
+       store_word (PARM1, tms.tms_utime);
+       store_word (PARM1 + 4, tms.tms_stime);
+       store_word (PARM1 + 8, tms.tms_cutime);
+       store_word (PARM1 + 12, tms.tms_cstime);
        break;
       }
-    case SYS_gettimeofday:
+#endif
+#ifdef TARGET_SYS_gettimeofday
+    case TARGET_SYS_gettimeofday:
       {
        struct timeval t;
        struct timezone tz;
        RETVAL = gettimeofday (&t, &tz);
-       store_mem (PARM1, 4, t.tv_sec);
-       store_mem (PARM1 + 4, 4, t.tv_usec);
-       store_mem (PARM2, 4, tz.tz_minuteswest);
-       store_mem (PARM2 + 4, 4, tz.tz_dsttime);
+       store_word (PARM1, t.tv_sec);
+       store_word (PARM1 + 4, t.tv_usec);
+       store_word (PARM2, tz.tz_minuteswest);
+       store_word (PARM2 + 4, tz.tz_dsttime);
        break;
       }
-    case SYS_utime:
+#endif
+#ifdef TARGET_SYS_utime
+    case TARGET_SYS_utime:
       /* Cast the second argument to void *, to avoid type mismatch
         if a prototype is present.  */
       RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
       break;
+#endif
     default:
       abort ();
     }
@@ -2981,95 +3035,197 @@ void OP_CB (insn, extension)
 {
 }
 
-/* putx */
+/* putx dm,dm */
 void OP_F500 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  State.regs[REG_MDRQ] = State.regs[REG_D0 + REG0 (insn)];
 }
 
-/* getx */
+/* getx dm,dm */
 void OP_F6F0 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  int z, n;
+  z = (State.regs[REG_MDRQ] == 0);
+  n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
+  State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDRQ];
+
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
 }
 
-/* mulq */
+/* mulq dm,dn */
 void OP_F600 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  unsigned long long temp;
+  int n, z;
+
+  temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)]
+          *  (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]);
+  State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
+  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+  z = (State.regs[REG_D0 + REG0 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 }
 
-/* mulq */
+/* mulq imm8,dn */
 void OP_F90000 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  unsigned long long temp;
+  int n, z;
+
+  temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_8 (insn)]
+          * (signed64)(signed32)SEXT8 (insn & 0xff));
+  State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff;
+  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+  z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 }
 
-/* mulq */
+/* mulq imm16,dn */
 void OP_FB000000 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  unsigned long long temp;
+  int n, z;
+
+  temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)]
+          * (signed64)(signed32)SEXT16 (insn & 0xffff));
+  State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
+  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+  z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 }
 
-/* mulq */
+/* mulq imm32,dn */
 void OP_FD000000 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  unsigned long long temp;
+  int n, z;
+
+  temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)]
+          * (signed64)(signed32)(((insn & 0xffff) << 16) + extension));
+  State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
+  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+  z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 }
 
-/* mulqu */
+/* mulqu dm,dn */
 void OP_F610 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  unsigned long long temp;
+  int n, z;
+
+  temp = ((unsigned64) State.regs[REG_D0 + REG0 (insn)]
+         * (unsigned64) State.regs[REG_D0 + REG1 (insn)]);
+  State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
+  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+  z = (State.regs[REG_D0 + REG0 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 }
 
-/* mulqu */
+/* mulqu imm8,dn */
 void OP_F91400 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  unsigned long long temp;
+  int n, z;
+
+  temp = ((unsigned64)State.regs[REG_D0 + REG0_8 (insn)]
+         * (unsigned64)SEXT8 (insn & 0xff));
+  State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff;
+  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+  z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 }
 
-/* mulqu */
+/* mulqu imm16,dn */
 void OP_FB140000 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  unsigned long long temp;
+  int n, z;
+
+  temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)]
+         * (unsigned64) SEXT16 (insn & 0xffff));
+  State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
+  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+  z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 }
 
-/* mulqu */
+/* mulqu imm32,dn */
 void OP_FD140000 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  unsigned long long temp;
+  int n, z;
+
+  temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)]
+          * (unsigned64)(((insn & 0xffff) << 16) + extension));
+  State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
+  State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+  z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
+  n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
+  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
 }
 
-/* sat16 */
+/* sat16 dm,dn */
 void OP_F640 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  int temp;
+
+  temp = State.regs[REG_D0 + REG1 (insn)];
+  temp = (temp > 0x7fff ? 0x7fff : temp);
+  temp = (temp < -0x8000 ? -0x8000 : temp);
+  State.regs[REG_D0 + REG0 (insn)] = temp;
 }
 
-/* sat24 */
+/* sat24 dm,dn */
 void OP_F650 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  int temp;
+
+  temp = State.regs[REG_D0 + REG1 (insn)];
+  temp = (temp > 0x7fffff ? 0x7fffff : temp);
+  temp = (temp < -0x800000 ? -0x800000 : temp);
+  State.regs[REG_D0 + REG0 (insn)] = temp;
 }
 
-/* bsch */
+/* bsch dm,dn */
 void OP_F670 (insn, extension)
      unsigned long insn, extension;
 {
-  abort ();
+  int temp, c;
+
+  temp = State.regs[REG_D0 + REG1 (insn)];
+  temp <<= (State.regs[REG_D0 + REG0 (insn)] & 0x1f);
+  c = (temp != 0 ? 1 : 0);
+  PSW &= ~(PSW_C);
+  PSW |= (c ? PSW_C : 0);
 }
 
 /* breakpoint */