/* Simulator for the moxie processor
- Copyright (C) 2008-2015 Free Software Foundation, Inc.
+ Copyright (C) 2008-2018 Free Software Foundation, Inc.
Contributed by Anthony Green
This file is part of GDB, the GNU debugger.
return hflags;
}
-/* TODO: Move to sim-trace.h. */
-static FILE *tracefile;
-static const int tracing = 0;
-#define TRACE(str) if (tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);
+/* TODO: Split this up into finger trace levels than just insn. */
+#define MOXIE_TRACE_INSN(str) \
+ TRACE_INSN (scpu, "0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x", \
+ opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], \
+ cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], \
+ cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], \
+ cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], \
+ cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], \
+ cpu.asregs.regs[14], cpu.asregs.regs[15])
void
sim_engine_run (SIM_DESC sd,
{
case 0x00: /* beq */
{
- TRACE("beq");
+ MOXIE_TRACE_INSN ("beq");
if (cpu.asregs.cc & CC_EQ)
pc += INST2OFFSET(inst);
}
break;
case 0x01: /* bne */
{
- TRACE("bne");
+ MOXIE_TRACE_INSN ("bne");
if (! (cpu.asregs.cc & CC_EQ))
pc += INST2OFFSET(inst);
}
break;
case 0x02: /* blt */
{
- TRACE("blt");
+ MOXIE_TRACE_INSN ("blt");
if (cpu.asregs.cc & CC_LT)
pc += INST2OFFSET(inst);
} break;
case 0x03: /* bgt */
{
- TRACE("bgt");
+ MOXIE_TRACE_INSN ("bgt");
if (cpu.asregs.cc & CC_GT)
pc += INST2OFFSET(inst);
}
break;
case 0x04: /* bltu */
{
- TRACE("bltu");
+ MOXIE_TRACE_INSN ("bltu");
if (cpu.asregs.cc & CC_LTU)
pc += INST2OFFSET(inst);
}
break;
case 0x05: /* bgtu */
{
- TRACE("bgtu");
+ MOXIE_TRACE_INSN ("bgtu");
if (cpu.asregs.cc & CC_GTU)
pc += INST2OFFSET(inst);
}
break;
case 0x06: /* bge */
{
- TRACE("bge");
+ MOXIE_TRACE_INSN ("bge");
if (cpu.asregs.cc & (CC_GT | CC_EQ))
pc += INST2OFFSET(inst);
}
break;
case 0x07: /* ble */
{
- TRACE("ble");
+ MOXIE_TRACE_INSN ("ble");
if (cpu.asregs.cc & (CC_LT | CC_EQ))
pc += INST2OFFSET(inst);
}
break;
case 0x08: /* bgeu */
{
- TRACE("bgeu");
+ MOXIE_TRACE_INSN ("bgeu");
if (cpu.asregs.cc & (CC_GTU | CC_EQ))
pc += INST2OFFSET(inst);
}
break;
case 0x09: /* bleu */
{
- TRACE("bleu");
+ MOXIE_TRACE_INSN ("bleu");
if (cpu.asregs.cc & (CC_LTU | CC_EQ))
pc += INST2OFFSET(inst);
}
break;
default:
{
- TRACE("SIGILL3");
- sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
+ MOXIE_TRACE_INSN ("SIGILL3");
+ sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL);
break;
}
}
unsigned av = cpu.asregs.regs[a];
unsigned v = (inst & 0xff);
- TRACE("inc");
+ MOXIE_TRACE_INSN ("inc");
cpu.asregs.regs[a] = av + v;
}
break;
unsigned av = cpu.asregs.regs[a];
unsigned v = (inst & 0xff);
- TRACE("dec");
+ MOXIE_TRACE_INSN ("dec");
cpu.asregs.regs[a] = av - v;
}
break;
int a = (inst >> 8) & 0xf;
unsigned v = (inst & 0xff);
- TRACE("gsr");
+ MOXIE_TRACE_INSN ("gsr");
cpu.asregs.regs[a] = cpu.asregs.sregs[v];
}
break;
int a = (inst >> 8) & 0xf;
unsigned v = (inst & 0xff);
- TRACE("ssr");
+ MOXIE_TRACE_INSN ("ssr");
cpu.asregs.sregs[v] = cpu.asregs.regs[a];
}
break;
default:
- TRACE("SIGILL2");
- sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
+ MOXIE_TRACE_INSN ("SIGILL2");
+ sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL);
break;
}
}
{
case 0x00: /* bad */
opc = opcode;
- TRACE("SIGILL0");
- sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
+ MOXIE_TRACE_INSN ("SIGILL0");
+ sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL);
break;
case 0x01: /* ldi.l (immediate) */
{
int reg = (inst >> 4) & 0xf;
unsigned int val = EXTRACT_WORD(pc+2);
- TRACE("ldi.l");
+ MOXIE_TRACE_INSN ("ldi.l");
cpu.asregs.regs[reg] = val;
pc += 4;
}
int dest = (inst >> 4) & 0xf;
int src = (inst ) & 0xf;
- TRACE("mov");
+ MOXIE_TRACE_INSN ("mov");
cpu.asregs.regs[dest] = cpu.asregs.regs[src];
}
break;
unsigned int fn = EXTRACT_WORD(pc+2);
unsigned int sp = cpu.asregs.regs[1];
- TRACE("jsra");
+ MOXIE_TRACE_INSN ("jsra");
/* Save a slot for the static chain. */
sp -= 4;
{
unsigned int sp = cpu.asregs.regs[0];
- TRACE("ret");
+ MOXIE_TRACE_INSN ("ret");
/* Pop the frame pointer. */
cpu.asregs.regs[0] = rlat (scpu, opc, sp);
unsigned av = cpu.asregs.regs[a];
unsigned bv = cpu.asregs.regs[b];
- TRACE("add.l");
+ MOXIE_TRACE_INSN ("add.l");
cpu.asregs.regs[a] = av + bv;
}
break;
int b = inst & 0xf;
int sp = cpu.asregs.regs[a] - 4;
- TRACE("push");
+ MOXIE_TRACE_INSN ("push");
wlat (scpu, opc, sp, cpu.asregs.regs[b]);
cpu.asregs.regs[a] = sp;
}
int b = inst & 0xf;
int sp = cpu.asregs.regs[a];
- TRACE("pop");
+ MOXIE_TRACE_INSN ("pop");
cpu.asregs.regs[b] = rlat (scpu, opc, sp);
cpu.asregs.regs[a] = sp + 4;
}
int reg = (inst >> 4) & 0xf;
unsigned int addr = EXTRACT_WORD(pc+2);
- TRACE("lda.l");
+ MOXIE_TRACE_INSN ("lda.l");
cpu.asregs.regs[reg] = rlat (scpu, opc, addr);
pc += 4;
}
int reg = (inst >> 4) & 0xf;
unsigned int addr = EXTRACT_WORD(pc+2);
- TRACE("sta.l");
+ MOXIE_TRACE_INSN ("sta.l");
wlat (scpu, opc, addr, cpu.asregs.regs[reg]);
pc += 4;
}
int dest = (inst >> 4) & 0xf;
int xv;
- TRACE("ld.l");
+ MOXIE_TRACE_INSN ("ld.l");
xv = cpu.asregs.regs[src];
cpu.asregs.regs[dest] = rlat (scpu, opc, xv);
}
int dest = (inst >> 4) & 0xf;
int val = inst & 0xf;
- TRACE("st.l");
+ MOXIE_TRACE_INSN ("st.l");
wlat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
}
break;
int a = (inst >> 4) & 0xf;
int b = inst & 0xf;
- TRACE("ldo.l");
+ MOXIE_TRACE_INSN ("ldo.l");
addr += cpu.asregs.regs[b];
cpu.asregs.regs[a] = rlat (scpu, opc, addr);
pc += 2;
int a = (inst >> 4) & 0xf;
int b = inst & 0xf;
- TRACE("sto.l");
+ MOXIE_TRACE_INSN ("sto.l");
addr += cpu.asregs.regs[a];
wlat (scpu, opc, addr, cpu.asregs.regs[b]);
pc += 2;
int va = cpu.asregs.regs[a];
int vb = cpu.asregs.regs[b];
- TRACE("cmp");
+ MOXIE_TRACE_INSN ("cmp");
if (va == vb)
cc = CC_EQ;
else
int b = inst & 0xf;
signed char bv = cpu.asregs.regs[b];
- TRACE("sex.b");
+ MOXIE_TRACE_INSN ("sex.b");
cpu.asregs.regs[a] = (int) bv;
}
break;
int b = inst & 0xf;
signed short bv = cpu.asregs.regs[b];
- TRACE("sex.s");
+ MOXIE_TRACE_INSN ("sex.s");
cpu.asregs.regs[a] = (int) bv;
}
break;
int b = inst & 0xf;
signed char bv = cpu.asregs.regs[b];
- TRACE("zex.b");
+ MOXIE_TRACE_INSN ("zex.b");
cpu.asregs.regs[a] = (int) bv & 0xff;
}
break;
int b = inst & 0xf;
signed short bv = cpu.asregs.regs[b];
- TRACE("zex.s");
+ MOXIE_TRACE_INSN ("zex.s");
cpu.asregs.regs[a] = (int) bv & 0xffff;
}
break;
unsigned long long r =
(unsigned long long) av * (unsigned long long) bv;
- TRACE("umul.x");
+ MOXIE_TRACE_INSN ("umul.x");
cpu.asregs.regs[a] = r >> 32;
}
break;
signed long long r =
(signed long long) av * (signed long long) bv;
- TRACE("mul.x");
+ MOXIE_TRACE_INSN ("mul.x");
cpu.asregs.regs[a] = r >> 32;
}
break;
case 0x18: /* bad */
{
opc = opcode;
- TRACE("SIGILL0");
- sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
+ MOXIE_TRACE_INSN ("SIGILL0");
+ sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL);
break;
}
case 0x19: /* jsr */
unsigned int fn = cpu.asregs.regs[(inst >> 4) & 0xf];
unsigned int sp = cpu.asregs.regs[1];
- TRACE("jsr");
+ MOXIE_TRACE_INSN ("jsr");
/* Save a slot for the static chain. */
sp -= 4;
{
unsigned int tgt = EXTRACT_WORD(pc+2);
- TRACE("jmpa");
+ MOXIE_TRACE_INSN ("jmpa");
pc = tgt - 2;
}
break;
int reg = (inst >> 4) & 0xf;
unsigned int val = EXTRACT_WORD(pc+2);
- TRACE("ldi.b");
+ MOXIE_TRACE_INSN ("ldi.b");
cpu.asregs.regs[reg] = val;
pc += 4;
}
int dest = (inst >> 4) & 0xf;
int xv;
- TRACE("ld.b");
+ MOXIE_TRACE_INSN ("ld.b");
xv = cpu.asregs.regs[src];
cpu.asregs.regs[dest] = rbat (scpu, opc, xv);
}
int reg = (inst >> 4) & 0xf;
unsigned int addr = EXTRACT_WORD(pc+2);
- TRACE("lda.b");
+ MOXIE_TRACE_INSN ("lda.b");
cpu.asregs.regs[reg] = rbat (scpu, opc, addr);
pc += 4;
}
int dest = (inst >> 4) & 0xf;
int val = inst & 0xf;
- TRACE("st.b");
+ MOXIE_TRACE_INSN ("st.b");
wbat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
}
break;
int reg = (inst >> 4) & 0xf;
unsigned int addr = EXTRACT_WORD(pc+2);
- TRACE("sta.b");
+ MOXIE_TRACE_INSN ("sta.b");
wbat (scpu, opc, addr, cpu.asregs.regs[reg]);
pc += 4;
}
unsigned int val = EXTRACT_WORD(pc+2);
- TRACE("ldi.s");
+ MOXIE_TRACE_INSN ("ldi.s");
cpu.asregs.regs[reg] = val;
pc += 4;
}
int dest = (inst >> 4) & 0xf;
int xv;
- TRACE("ld.s");
+ MOXIE_TRACE_INSN ("ld.s");
xv = cpu.asregs.regs[src];
cpu.asregs.regs[dest] = rsat (scpu, opc, xv);
}
int reg = (inst >> 4) & 0xf;
unsigned int addr = EXTRACT_WORD(pc+2);
- TRACE("lda.s");
+ MOXIE_TRACE_INSN ("lda.s");
cpu.asregs.regs[reg] = rsat (scpu, opc, addr);
pc += 4;
}
int dest = (inst >> 4) & 0xf;
int val = inst & 0xf;
- TRACE("st.s");
+ MOXIE_TRACE_INSN ("st.s");
wsat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
}
break;
int reg = (inst >> 4) & 0xf;
unsigned int addr = EXTRACT_WORD(pc+2);
- TRACE("sta.s");
+ MOXIE_TRACE_INSN ("sta.s");
wsat (scpu, opc, addr, cpu.asregs.regs[reg]);
pc += 4;
}
{
int reg = (inst >> 4) & 0xf;
- TRACE("jmp");
+ MOXIE_TRACE_INSN ("jmp");
pc = cpu.asregs.regs[reg] - 2;
}
break;
int b = inst & 0xf;
int av, bv;
- TRACE("and");
+ MOXIE_TRACE_INSN ("and");
av = cpu.asregs.regs[a];
bv = cpu.asregs.regs[b];
cpu.asregs.regs[a] = av & bv;
int av = cpu.asregs.regs[a];
int bv = cpu.asregs.regs[b];
- TRACE("lshr");
+ MOXIE_TRACE_INSN ("lshr");
cpu.asregs.regs[a] = (unsigned) ((unsigned) av >> bv);
}
break;
int av = cpu.asregs.regs[a];
int bv = cpu.asregs.regs[b];
- TRACE("ashl");
+ MOXIE_TRACE_INSN ("ashl");
cpu.asregs.regs[a] = av << bv;
}
break;
unsigned av = cpu.asregs.regs[a];
unsigned bv = cpu.asregs.regs[b];
- TRACE("sub.l");
+ MOXIE_TRACE_INSN ("sub.l");
cpu.asregs.regs[a] = av - bv;
}
break;
int b = inst & 0xf;
int bv = cpu.asregs.regs[b];
- TRACE("neg");
+ MOXIE_TRACE_INSN ("neg");
cpu.asregs.regs[a] = - bv;
}
break;
int b = inst & 0xf;
int av, bv;
- TRACE("or");
+ MOXIE_TRACE_INSN ("or");
av = cpu.asregs.regs[a];
bv = cpu.asregs.regs[b];
cpu.asregs.regs[a] = av | bv;
int b = inst & 0xf;
int bv = cpu.asregs.regs[b];
- TRACE("not");
+ MOXIE_TRACE_INSN ("not");
cpu.asregs.regs[a] = 0xffffffff ^ bv;
}
break;
int av = cpu.asregs.regs[a];
int bv = cpu.asregs.regs[b];
- TRACE("ashr");
+ MOXIE_TRACE_INSN ("ashr");
cpu.asregs.regs[a] = av >> bv;
}
break;
int b = inst & 0xf;
int av, bv;
- TRACE("xor");
+ MOXIE_TRACE_INSN ("xor");
av = cpu.asregs.regs[a];
bv = cpu.asregs.regs[b];
cpu.asregs.regs[a] = av ^ bv;
unsigned av = cpu.asregs.regs[a];
unsigned bv = cpu.asregs.regs[b];
- TRACE("mul.l");
+ MOXIE_TRACE_INSN ("mul.l");
cpu.asregs.regs[a] = av * bv;
}
break;
{
unsigned int inum = EXTRACT_WORD(pc+2);
- TRACE("swi");
+ MOXIE_TRACE_INSN ("swi");
/* Set the special registers appropriately. */
cpu.asregs.sregs[2] = 3; /* MOXIE_EX_SWI */
cpu.asregs.sregs[3] = inum;
{
case 0x1: /* SYS_exit */
{
- sim_engine_halt (sd, NULL, NULL, pc, sim_exited,
+ sim_engine_halt (sd, scpu, NULL, pc, sim_exited,
cpu.asregs.regs[2]);
break;
}
int av = cpu.asregs.regs[a];
int bv = cpu.asregs.regs[b];
- TRACE("div.l");
+ MOXIE_TRACE_INSN ("div.l");
cpu.asregs.regs[a] = av / bv;
}
break;
unsigned int av = cpu.asregs.regs[a];
unsigned int bv = cpu.asregs.regs[b];
- TRACE("udiv.l");
+ MOXIE_TRACE_INSN ("udiv.l");
cpu.asregs.regs[a] = (av / bv);
}
break;
int av = cpu.asregs.regs[a];
int bv = cpu.asregs.regs[b];
- TRACE("mod.l");
+ MOXIE_TRACE_INSN ("mod.l");
cpu.asregs.regs[a] = av % bv;
}
break;
unsigned int av = cpu.asregs.regs[a];
unsigned int bv = cpu.asregs.regs[b];
- TRACE("umod.l");
+ MOXIE_TRACE_INSN ("umod.l");
cpu.asregs.regs[a] = (av % bv);
}
break;
case 0x35: /* brk */
- TRACE("brk");
- sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGTRAP);
+ MOXIE_TRACE_INSN ("brk");
+ sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
pc -= 2; /* Adjust pc */
break;
case 0x36: /* ldo.b */
int a = (inst >> 4) & 0xf;
int b = inst & 0xf;
- TRACE("ldo.b");
+ MOXIE_TRACE_INSN ("ldo.b");
addr += cpu.asregs.regs[b];
cpu.asregs.regs[a] = rbat (scpu, opc, addr);
pc += 2;
int a = (inst >> 4) & 0xf;
int b = inst & 0xf;
- TRACE("sto.b");
+ MOXIE_TRACE_INSN ("sto.b");
addr += cpu.asregs.regs[a];
wbat (scpu, opc, addr, cpu.asregs.regs[b]);
pc += 2;
int a = (inst >> 4) & 0xf;
int b = inst & 0xf;
- TRACE("ldo.s");
+ MOXIE_TRACE_INSN ("ldo.s");
addr += cpu.asregs.regs[b];
cpu.asregs.regs[a] = rsat (scpu, opc, addr);
pc += 2;
int a = (inst >> 4) & 0xf;
int b = inst & 0xf;
- TRACE("sto.s");
+ MOXIE_TRACE_INSN ("sto.s");
addr += cpu.asregs.regs[a];
wsat (scpu, opc, addr, cpu.asregs.regs[b]);
pc += 2;
break;
default:
opc = opcode;
- TRACE("SIGILL1");
- sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
+ MOXIE_TRACE_INSN ("SIGILL1");
+ sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL);
break;
}
}
cpu.asregs.insts++;
pc += 2;
cpu.asregs.regs[PC_REGNO] = pc;
+
+ if (sim_events_tick (sd))
+ sim_events_process (sd);
+
} while (1);
}
-int
-sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
+static int
+moxie_reg_store (SIM_CPU *scpu, int rn, unsigned char *memory, int length)
{
if (rn < NUM_MOXIE_REGS && rn >= 0)
{
return 0;
}
-int
-sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
+static int
+moxie_reg_fetch (SIM_CPU *scpu, int rn, unsigned char *memory, int length)
{
if (rn < NUM_MOXIE_REGS && rn >= 0)
{
}
SIM_DESC
-sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
+sim_open (SIM_OPEN_KIND kind, host_callback *cb,
+ struct bfd *abfd, char * const *argv)
{
int i;
SIM_DESC sd = sim_state_alloc (kind, cb);
return 0;
}
- /* getopt will print the error message so we just have to exit if this fails.
- FIXME: Hmmm... in the case of gdb we need getopt to call
- print_filtered. */
+ /* The parser will print an error message for us, so we silently return. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
free_state (sd);
{
SIM_CPU *cpu = STATE_CPU (sd, i);
+ CPU_REG_FETCH (cpu) = moxie_reg_fetch;
+ CPU_REG_STORE (cpu) = moxie_reg_store;
CPU_PC_FETCH (cpu) = moxie_pc_get;
CPU_PC_STORE (cpu) = moxie_pc_set;
return sd;
}
-void
-sim_close (SIM_DESC sd, int quitting)
-{
- /* nothing to do */
-}
-
-
/* Load the device tree blob. */
static void
if (size != fread (buf, 1, size, f))
{
sim_io_eprintf (sd, "ERROR: error reading ``%s''.\n", filename);
+ fclose (f);
return;
}
sim_core_write_buffer (sd, scpu, write_map, buf, 0xE0000000, size);
}
SIM_RC
-sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
+sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd,
+ char * const *argv, char * const *env)
{
char ** avp;
int l, argc, i, tp;