/* Simulator for the moxie processor
- Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+ Copyright (C) 2008-2014 Free Software Foundation, Inc.
Contributed by Anthony Green
This file is part of GDB, the GNU debugger.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
+#include "config.h"
+#include <fcntl.h>
#include <signal.h>
#include <stdlib.h>
#include "sysdep.h"
cpu.asregs.sregs[i] = 0;
}
-static void
-interrupt ()
-{
- cpu.asregs.exception = SIGINT;
-}
-
/* Write a 1 byte value to memory. */
static void INLINE
word pc, opc;
unsigned long long insts;
unsigned short inst;
- void (* sigsave)();
sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
address_word cia = CIA_GET (scpu);
- sigsave = signal (SIGINT, interrupt);
cpu.asregs.exception = step ? SIGTRAP: 0;
pc = cpu.asregs.regs[PC_REGNO];
insts = cpu.asregs.insts;
{
TRACE("beq");
if (cpu.asregs.cc & CC_EQ)
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
}
break;
case 0x01: /* bne */
{
TRACE("bne");
if (! (cpu.asregs.cc & CC_EQ))
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
}
break;
case 0x02: /* blt */
{
TRACE("blt");
if (cpu.asregs.cc & CC_LT)
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
} break;
case 0x03: /* bgt */
{
TRACE("bgt");
if (cpu.asregs.cc & CC_GT)
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
}
break;
case 0x04: /* bltu */
{
TRACE("bltu");
if (cpu.asregs.cc & CC_LTU)
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
}
break;
case 0x05: /* bgtu */
{
TRACE("bgtu");
if (cpu.asregs.cc & CC_GTU)
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
}
break;
case 0x06: /* bge */
{
TRACE("bge");
if (cpu.asregs.cc & (CC_GT | CC_EQ))
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
}
break;
case 0x07: /* ble */
{
TRACE("ble");
if (cpu.asregs.cc & (CC_LT | CC_EQ))
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
}
break;
case 0x08: /* bgeu */
{
TRACE("bgeu");
if (cpu.asregs.cc & (CC_GTU | CC_EQ))
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
}
break;
case 0x09: /* bleu */
{
TRACE("bleu");
if (cpu.asregs.cc & (CC_LTU | CC_EQ))
- pc += INST2OFFSET(inst) - 2;
+ pc += INST2OFFSET(inst);
}
break;
default:
int opcode = inst >> 8;
switch (opcode)
{
- case 0x00: /* nop */
+ case 0x00: /* bad */
+ opc = opcode;
+ TRACE("SIGILL0");
+ cpu.asregs.exception = SIGILL;
break;
case 0x01: /* ldi.l (immediate) */
{
cpu.asregs.cc = cc;
}
break;
- case 0x0f:
- case 0x10:
- case 0x11:
- case 0x12:
- case 0x13:
- case 0x14:
- case 0x15:
- case 0x16:
- case 0x17:
- case 0x18:
+ case 0x0f: /* nop */
+ break;
+ case 0x10: /* bad */
+ case 0x11: /* bad */
+ case 0x12: /* bad */
+ case 0x13: /* bad */
+ case 0x14: /* bad */
+ case 0x15: /* bad */
+ case 0x16: /* bad */
+ case 0x17: /* bad */
+ case 0x18: /* bad */
{
opc = opcode;
TRACE("SIGILL0");
/* Hide away the things we've cached while executing. */
cpu.asregs.regs[PC_REGNO] = pc;
cpu.asregs.insts += insts; /* instructions done ... */
-
- signal (SIGINT, sigsave);
}
int
sim_write (sd, addr, buffer, size)
SIM_DESC sd;
SIM_ADDR addr;
- unsigned char * buffer;
+ const unsigned char * buffer;
int size;
{
sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
char ** argv;
{
SIM_DESC sd = sim_state_alloc (kind, cb);
- printf ("0x%x 0x%x\n", sd, STATE_MAGIC(sd));
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
SIM_RC
sim_load (sd, prog, abfd, from_tty)
SIM_DESC sd;
- char * prog;
+ const char * prog;
bfd * abfd;
int from_tty;
{
set_initial_gprs ();
issue_messages = l;
- cpu.asregs.regs[PC_REGNO] = bfd_get_start_address (prog_bfd);
+ if (prog_bfd != NULL)
+ cpu.asregs.regs[PC_REGNO] = bfd_get_start_address (prog_bfd);
/* Copy args into target memory. */
avp = argv;
- for (argc = 0; *avp; avp++)
+ for (argc = 0; avp && *avp; avp++)
argc++;
/* Target memory looks like this: