#
# This file is part of the program psim.
#
-# Copyright 1994, 1995, 1996, 1997, 2003 Andrew Cagney
+# Copyright 1994, 1995, 1996, 1997, 2003, 2004 Andrew Cagney
#
# --
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
+# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# along with this program; if not, see <http://www.gnu.org/licenses/>.
#
:cache::::RA:RA:
busy_ptr->nr_writebacks = 1;
TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR)));
-# Schedule a MFCR instruction that moves the CR into an integer regsiter
+# Schedule a MFCR instruction that moves the CR into an integer register
void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, unsigned32 int_mask
const unsigned32 cr_mask = 0xff;
model_busy *busy_ptr;
tail->suffix_singular = "";
}
- for (j = 0; j < (sizeof(ppc_branch_conditional_name) / sizeof(ppc_branch_conditional_name[0])) ; j++) {
+ for (j = 0; j < ARRAY_SIZE (ppc_branch_conditional_name); j++) {
if (model_ptr->nr_branch_conditional[j]) {
tail->next = ZALLOC(model_print);
tail = tail->next;
/* FPSCR[fprf] = undefined */
}
/**/
- LABEL(Done):
+ LABEL(Done):;
# extract out raw fields of a FP number
}
PPC_INSN_INT(0, (RA_BITMASK & ~1) | RB_BITMASK | RS_BITMASK, 1/*Rc*/);
-0.31,6./,11./,16./,21.598,31./:X::sync:Synchronize
+0.31,6./,9.L,11./,16./,21.598,31./:X::sync:Synchronize
*601: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603: PPC_UNIT_SRU, PPC_UNIT_SRU, 1, 1, 0
*603e:PPC_UNIT_SRU, PPC_UNIT_SRU, 1, 1, 0
spreg new_val = (spr_length(n) == 64
? *rS
: MASKED(*rS, 32, 63));
- /* HACK - time base registers need to be updated immediatly */
+ /* HACK - time base registers need to be updated immediately */
if (WITH_TIME_BASE) {
switch (n) {
case spr_tbu:
case spr_dec:
*rT = cpu_get_decrementer(processor);
break;
+ case spr_tbrl:
+ if (is_64bit_implementation) *rT = TB;
+ else *rT = EXTRACTED64(TB, 32, 63);
+ break;
+ case spr_tbru:
+ if (is_64bit_implementation) *rT = EXTRACTED64(TB, 0, 31);
+ else *rT = EXTRACTED64(TB, 0, 31);
+ break;
case spr_tbu:
case spr_tbl:
/* NOTE - these SPR's are not readable. Use mftb[ul] */
STORE(EA, 8, *frS);
PPC_INSN_INT_FLOAT(0, 0, (RA_BITMASK & ~1) | RB_BITMASK, FRS_BITMASK);
+0.31,6.FRS,11.RA,16.RB,21.983,31./:X:f::Store Floating-Point Integer Word Indexed
+*603: PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 2, 0
+*603e:PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 2, 0
+*604: PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 3, 0
+ unsigned_word b;
+ unsigned_word EA;
+ if (RA_is_0) b = 0;
+ else b = *rA;
+ EA = b + *rB;
+ STORE(EA, 4, *frS);
+ PPC_INSN_INT_FLOAT(0, 0, (RA_BITMASK & ~1) | RB_BITMASK, FRS_BITMASK);
+
0.55,6.FRS,11.RA,16.D:D:f::Store Floating-Point Double with Update
*601: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603: PPC_UNIT_LSU, PPC_UNIT_LSU, 1, 2, 0
fpscr_vxsnan | fpscr_vximz,
0, /*single?*/
0) /*negate?*/) {
+ union { double d; unsigned64 u; } tmp;
invalid_arithemetic_operation(processor, cia,
- (unsigned64*)&product, *frA, 0, *frC,
+ &tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
0, /*instruction_is_convert_to_64bit*/
0, /*instruction_is_convert_to_32bit*/
0); /*single-precision*/
+ product = tmp.d;
}
else {
/*HACK!*/
fpscr_vxsnan | fpscr_vximz,
1, /*single?*/
0) /*negate?*/) {
+ union { double d; unsigned64 u; } tmp;
invalid_arithemetic_operation(processor, cia,
- (unsigned64*)&product, *frA, 0, *frC,
+ &tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
0, /*instruction_is_convert_to_64bit*/
0, /*instruction_is_convert_to_32bit*/
0); /*single-precision*/
+ product = tmp.d;
}
else {
/*HACK!*/
fpscr_vxsnan | fpscr_vximz,
0, /*single?*/
0) /*negate?*/) {
+ union { double d; unsigned64 u; } tmp;
invalid_arithemetic_operation(processor, cia,
- (unsigned64*)&product, *frA, 0, *frC,
+ &tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
0, /*instruction_is_convert_to_64bit*/
0, /*instruction_is_convert_to_32bit*/
0); /*single-precision*/
+ product = tmp.d;
}
else {
/*HACK!*/
fpscr_vxsnan | fpscr_vximz,
1, /*single?*/
0) /*negate?*/) {
+ union { double d; unsigned64 u; } tmp;
invalid_arithemetic_operation(processor, cia,
- (unsigned64*)&product, *frA, 0, *frC,
+ &tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
0, /*instruction_is_convert_to_64bit*/
0, /*instruction_is_convert_to_32bit*/
0); /*single-precision*/
+ product = tmp.d;
}
else {
/*HACK!*/
fpscr_vxsnan | fpscr_vximz,
0, /*single?*/
0) /*negate?*/) {
+ union { double d; unsigned64 u; } tmp;
invalid_arithemetic_operation(processor, cia,
- (unsigned64*)&product, *frA, 0, *frC,
+ &tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
0, /*instruction_is_convert_to_64bit*/
0, /*instruction_is_convert_to_32bit*/
0); /*single-precision*/
+ product = tmp.d;
}
else {
/*HACK!*/
fpscr_vxsnan | fpscr_vximz,
1, /*single?*/
0) /*negate?*/) {
+ union { double d; unsigned64 u; } tmp;
invalid_arithemetic_operation(processor, cia,
- (unsigned64*)&product, *frA, 0, *frC,
+ &tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
0, /*instruction_is_convert_to_64bit*/
0, /*instruction_is_convert_to_32bit*/
0); /*single-precision*/
+ product = tmp.d;
}
else {
/*HACK!*/
fpscr_vxsnan | fpscr_vximz,
0, /*single?*/
0) /*negate?*/) {
+ union { double d; unsigned64 u; } tmp;
invalid_arithemetic_operation(processor, cia,
- (unsigned64*)&product, *frA, 0, *frC,
+ &tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
0, /*instruction_is_convert_to_64bit*/
0, /*instruction_is_convert_to_32bit*/
0); /*single-precision*/
+ product = tmp.d;
}
else {
/*HACK!*/
fpscr_vxsnan | fpscr_vximz,
1, /*single?*/
0) /*negate?*/) {
+ union { double d; unsigned64 u; } tmp;
invalid_arithemetic_operation(processor, cia,
- (unsigned64*)&product, *frA, 0, *frC,
+ &tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
0, /*instruction_is_convert_to_64bit*/
0, /*instruction_is_convert_to_32bit*/
0); /*single-precision*/
+ product = tmp.d;
}
else {
/*HACK!*/
FPSCR |= bit;
FPSCR_END(Rc);
-
-#
-# I.A.1.1 Floating-Point Store Instruction
-#
-0.31,6.FRS,11.RA,16.RB,21.983,31./:X:f,o::Store Floating-Point as Integer Word Indexed
- program_interrupt(processor, cia, optional_instruction_program_interrupt);
-
#
# I.A.1.2 Floating-Point Arithmetic Instructions
#
projects / deliverable / binutils-gdb.git / blobdiff