Handle correctly passing a bad interpreter name to new-ui

[deliverable/binutils-gdb.git] / sim / rx / rx.c

diff --git a/sim/rx/rx.c b/sim/rx/rx.c
index 1deef91656b0f67ce8c01c534ade0014075e51b7..b49c13d7e75b27e66602e5f0210eec997820ab27 100644 (file)
--- a/sim/rx/rx.c
+++ b/sim/rx/rx.c
@@ -1,6 +1,6 @@
 /* rx.c --- opcode semantics for stand-alone RX simulator.
 
-Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+Copyright (C) 2008-2016 Free Software Foundation, Inc.
 Contributed by Red Hat, Inc.
 
 This file is part of the GNU simulators.
@@ -80,6 +80,10 @@ static const char * id_names[] = {
   "RXO_nop",
   "RXO_nop2",
   "RXO_nop3",
+  "RXO_nop4",
+  "RXO_nop5",
+  "RXO_nop6",
+  "RXO_nop7",
 
   "RXO_scmpu",
   "RXO_smovu",
@@ -136,7 +140,7 @@ static const char * id_names[] = {
 };
 
 static const char * optype_names[] = {
-  "    ",
+  " -  ",
   "#Imm",      /* #addend */
   " Rn ",      /* Rn */
   "[Rn]",      /* [Rn + addend] */
@@ -149,7 +153,7 @@ static const char * optype_names[] = {
 
 #define N_RXO (sizeof(id_names)/sizeof(id_names[0]))
 #define N_RXT (sizeof(optype_names)/sizeof(optype_names[0]))
-#define N_MAP 30
+#define N_MAP 90
 
 static unsigned long long benchmark_start_cycle;
 static unsigned long long benchmark_end_cycle;
@@ -264,6 +268,52 @@ cycles (int throughput)
       new_rt = r;                              \
     }
 
+static int
+lsb_count (unsigned long v, int is_signed)
+{
+  int i, lsb;
+  if (is_signed && (v & 0x80000000U))
+    v = (unsigned long)(long)(-v);
+  for (i=31; i>=0; i--)
+    if (v & (1 << i))
+      {
+       /* v is 0..31, we want 1=1-2, 2=3-4, 3=5-6, etc. */
+       lsb = (i + 2) / 2;
+       return lsb;
+      }
+  return 0;
+}
+
+static int
+divu_cycles(unsigned long num, unsigned long den)
+{
+  int nb = lsb_count (num, 0);
+  int db = lsb_count (den, 0);
+  int rv;
+
+  if (nb < db)
+    rv = 2;
+  else
+    rv = 3 + nb - db;
+  E (rv);
+  return rv;
+}
+
+static int
+div_cycles(long num, long den)
+{
+  int nb = lsb_count ((unsigned long)num, 1);
+  int db = lsb_count ((unsigned long)den, 1);
+  int rv;
+
+  if (nb < db)
+    rv = 3;
+  else
+    rv = 5 + nb - db;
+  E (rv);
+  return rv;
+}
+
 #else /* !CYCLE_ACCURATE */
 
 #define cycles(t)
@@ -274,6 +324,9 @@ cycles (int throughput)
 #define RL(r)
 #define RLD(r)
 
+#define divu_cycles(n,d)
+#define div_cycles(n,d)
+
 #endif /* else CYCLE_ACCURATE */
 
 static int size2bytes[] = {
@@ -298,6 +351,14 @@ static unsigned char *get_byte_base;
 static RX_Opcode_Decoded **decode_cache_base;
 static SI get_byte_page;
 
+void
+reset_decoder (void)
+{
+  get_byte_base = 0;
+  decode_cache_base = 0;
+  get_byte_page = 0;
+}
+
 static inline void
 maybe_get_mem_page (SI tpc)
 {
@@ -349,6 +410,7 @@ get_op (const RX_Opcode_Decoded *rd, int i)
       put_reg (o->reg, get_reg (o->reg) - size2bytes[o->size]);
       /* fall through */
     case RX_Operand_Postinc:   /* [Rn+] */
+    case RX_Operand_Zero_Indirect:     /* [Rn + 0] */
     case RX_Operand_Indirect:  /* [Rn + addend] */
     case RX_Operand_TwoReg:    /* [Rn + scale * R2] */
 #ifdef CYCLE_ACCURATE
@@ -376,6 +438,7 @@ get_op (const RX_Opcode_Decoded *rd, int i)
 
       switch (o->size)
        {
+       default:
        case RX_AnySize:
          rx_abort ();
 
@@ -416,6 +479,7 @@ get_op (const RX_Opcode_Decoded *rd, int i)
      to the size.  */
   switch (o->size)
     {
+    default:
     case RX_AnySize:
       rx_abort ();
 
@@ -461,6 +525,7 @@ put_op (const RX_Opcode_Decoded *rd, int i, int v)
 
   switch (o->size)
     {
+    default:
     case RX_AnySize:
       if (o->type != RX_Operand_Register)
        rx_abort ();
@@ -517,6 +582,7 @@ put_op (const RX_Opcode_Decoded *rd, int i, int v)
       put_reg (o->reg, get_reg (o->reg) - size2bytes[o->size]);
       /* fall through */
     case RX_Operand_Postinc:   /* [Rn+] */
+    case RX_Operand_Zero_Indirect:     /* [Rn + 0] */
     case RX_Operand_Indirect:  /* [Rn + addend] */
     case RX_Operand_TwoReg:    /* [Rn + scale * R2] */
 
@@ -540,6 +606,7 @@ put_op (const RX_Opcode_Decoded *rd, int i, int v)
 
       switch (o->size)
        {
+       default:
        case RX_AnySize:
          rx_abort ();
 
@@ -675,8 +742,7 @@ poppc()
       c = val & carry_mask; \
       val OP 1; \
     } \
-  if (count) \
-    set_oszc (val, 4, c); \
+  set_oszc (val, 4, c); \
   PD (val); \
 }
 
@@ -878,7 +944,7 @@ decode_opcode ()
   unsigned long long prev_cycle_count;
 #endif
 #ifdef CYCLE_ACCURATE
-  int tx;
+  unsigned int tx;
 #endif
 
 #ifdef CYCLE_STATS
@@ -1030,10 +1096,10 @@ decode_opcode ()
       break;
 
     case RXO_branchrel:
-      if (GS())
+      if (opcode->op[1].type == RX_Operand_None || GS())
        {
          int delta = GD();
-         regs.r_pc += delta;
+         regs.r_pc = opcode_pc + delta;
 #ifdef CYCLE_ACCURATE
          /* Note: specs say 3, chip says 2.  */
          if (delta >= 0 && delta < 16
@@ -1118,6 +1184,7 @@ decode_opcode ()
        {
          tprintf("#NAN\n");
          set_flags (FLAGBIT_O, FLAGBIT_O);
+         cycles (3);
        }
       else
        {
@@ -1125,9 +1192,8 @@ decode_opcode ()
          tprintf("%d\n", v);
          set_flags (FLAGBIT_O, 0);
          PD (v);
+         div_cycles (mb, ma);
        }
-      /* Note: spec says 3 to 22 cycles, we are pessimistic.  */
-      cycles (22);
       break;
 
     case RXO_divu: /* d = d / s */
@@ -1138,6 +1204,7 @@ decode_opcode ()
        {
          tprintf("#NAN\n");
          set_flags (FLAGBIT_O, FLAGBIT_O);
+         cycles (2);
        }
       else
        {
@@ -1145,9 +1212,8 @@ decode_opcode ()
          tprintf("%u\n", v);
          set_flags (FLAGBIT_O, 0);
          PD (v);
+         divu_cycles (umb, uma);
        }
-      /* Note: spec says 2 to 20 cycles, we are pessimistic.  */
-      cycles (20);
       break;
 
     case RXO_emul:
@@ -1224,7 +1290,9 @@ decode_opcode ()
       v = GS ();
       if (v == 255)
        {
-         DO_RETURN (rx_syscall (regs.r[5]));
+         int rc = rx_syscall (regs.r[5]);
+         if (! RX_STEPPED (rc))
+           DO_RETURN (rc);
        }
       else
        {
@@ -1320,6 +1388,14 @@ decode_opcode ()
     case RXO_mov:
       v = GS ();
 
+      if (opcode->op[1].type == RX_Operand_Register
+         && opcode->op[1].reg == 17 /* PC */)
+       {
+         /* Special case.  We want the address of the insn, not the
+            address of the next insn.  */
+         v = opcode_pc;
+       }
+
       if (opcode->op[0].type == RX_Operand_Register
          && opcode->op[0].reg == 16 /* PSW */)
        {
@@ -1438,6 +1514,10 @@ decode_opcode ()
     case RXO_nop:
     case RXO_nop2:
     case RXO_nop3:
+    case RXO_nop4:
+    case RXO_nop5:
+    case RXO_nop6:
+    case RXO_nop7:
       E1;
       break;
 
@@ -1735,6 +1815,22 @@ decode_opcode ()
       E1;
       break;
 
+    case RXO_satr:
+      if (FLAG_O && ! FLAG_S)
+       {
+         put_reg (6, 0x0);
+         put_reg (5, 0x7fffffff);
+         put_reg (4, 0xffffffff);
+       }
+      else if (FLAG_O && FLAG_S)
+       {
+         put_reg (6, 0xffffffff);
+         put_reg (5, 0x80000000);
+         put_reg (4, 0x0);
+       }
+      E1;
+      break;
+      
     case RXO_sbb:
       MATH_OP (-, ! carry);
       break;
@@ -1810,6 +1906,9 @@ decode_opcode ()
       break;
 
     case RXO_smovu:
+#ifdef CYCLE_ACCURATE
+      tx = regs.r[3];
+#endif
       while (regs.r[3] != 0)
        {
          uma = mem_get_qi (regs.r[2] ++);
@@ -1818,6 +1917,7 @@ decode_opcode ()
          if (uma == 0)
            break;
        }
+      cycles (2 + 3 * (int)(tx / 4) + 3 * (tx % 4));
       break;
 
     case RXO_shar: /* d = ma >> mb */
@@ -1892,7 +1992,7 @@ decode_opcode ()
     case RXO_suntil:
       RL(3);
 #ifdef CYCLE_ACCURATE
-      tx = regs.r[3];
+      tx = 0;
 #endif
       if (regs.r[3] == 0)
        {
@@ -1908,10 +2008,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_si (get_reg (1));
              regs.r[1] += 4;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb == uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * tx);
+#endif
          break;
        case RX_Word:
          uma = get_reg (2) & 0xffff;
@@ -1920,10 +2025,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_hi (get_reg (1));
              regs.r[1] += 2;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb == uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * (tx / 2) + 3 * (tx % 2));
+#endif
          break;
        case RX_Byte:
          uma = get_reg (2) & 0xff;
@@ -1932,10 +2042,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_qi (regs.r[1]);
              regs.r[1] += 1;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb == uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * (tx / 4) + 3 * (tx % 4));
+#endif
          break;
        default:
          abort();
@@ -1949,7 +2064,7 @@ decode_opcode ()
     case RXO_swhile:
       RL(3);
 #ifdef CYCLE_ACCURATE
-      tx = regs.r[3];
+      tx = 0;
 #endif
       if (regs.r[3] == 0)
        break;
@@ -1962,10 +2077,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_si (get_reg (1));
              regs.r[1] += 4;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb != uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * tx);
+#endif
          break;
        case RX_Word:
          uma = get_reg (2) & 0xffff;
@@ -1974,10 +2094,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_hi (get_reg (1));
              regs.r[1] += 2;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb != uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * (tx / 2) + 3 * (tx % 2));
+#endif
          break;
        case RX_Byte:
          uma = get_reg (2) & 0xff;
@@ -1986,10 +2111,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_qi (regs.r[1]);
              regs.r[1] += 1;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb != uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * (tx / 4) + 3 * (tx % 4));
+#endif
          break;
        default:
          abort();